FME-MB96380 rev 10
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development. http://edevice.fujitsu.com/micom/en-support/
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96380 Series
MB96384*1/385*1
MB96F385*1/F386/F387/F388*1/F389*1
■DESCRIPTION
MB96380 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage
regulatorthatreducestheinternalCPUvoltage.Aflexibleclocktreeallowstoselectsuitableoperationfrequencies
for peripheral resources independent of the CPU speed.
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
MB96380 Series
2 FME-MB96380 rev 10
■FEATURES
Feature Description
Technology • 0.18µm CMOS
CPU
•F
2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
System clock
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 56 MHz external clock for devices with fast clock input feature
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
On-chip voltage regula-
tor • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
Low voltage reset • Reset is generated when supply voltage is below minimum.
Code Security • Protects ROM content from unintended read-out
Memory Patch Function • Replaces ROM content
• Can also be used to implement embedded debug support
DMA • Automatic transfer function independent of CPU, can be assigned freely to resources
Interrupts
• Fast Interrupt processing
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
Timers • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
MB96380 Series
FME-MB96380 rev 10 3
CAN
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
USART
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
I2C• Up to 400 kbps
• Master and Slave functionality, 7-bit and 10-bit addressing
A/D converter
• SAR-type
• 10-bit resolution
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
A/D Converter Refer-
ence Voltage switch • 2 independent positive A/D converter reference voltages available
Reload Timers
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Free Running Timers • Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28of
peripheral clock frequency
Input Capture Units
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
Output Compare Units
• 16-bit wide
• Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
Feature Description
MB96380 Series
4 FME-MB96380 rev 10
Programmable Pulse
Generator
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer underflow as clock input
• Can be triggered by software or reload timer
Stepper Motor Control-
ler
• Stepper Motor Controller with integrated high current output drivers
• Four high current outputs for each channel
• Two synchronized 8/10-bit PWMs per channel
• Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral
clock
• Separate power supply for high current output drivers
LCD Controller
• LCD controller with up to 4 COM × 65 SEG
• Internal or external voltage generation
• Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
• Fixed 1/3 bias
• Programmable frame period
• Clock source selectable from three options (peripheral clock, subclock or RC
oscillator clock)
• On-chip drivers for internal divider resistors or external divider resistors
• On-chip data memory for display
• LCD display can be operated in Timer Mode
• Blank display: selectable
• All SEG, COM and V pins can be switched between general and specialized
purposes
• External divided resistors can be also used to shut off the current when LCD is
deactivated
Sound Generator • 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
• PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock
Real Time Clock
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
Feature Description
MB96380 Series
FME-MB96380 rev 10 5
External Interrupts
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
Non Maskable Interrupt
• Disabled after reset
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
• Pin shared with external interrupt 0.
External bus interface
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
• Multiplexed address/data lines
• Non-multiplexed address/data lines
• Wait state request
• External bus master possible
• Timing programmable
Alarm comparator
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
I/O Ports
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
Package • 120-pin plastic LQFP
Flash Memory
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
• Data retention time: 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
Feature Description
MB96380 Series
6 FME-MB96380 rev 10
■PRODUCT LINEUP
Features MB96V300B MB96(F)38x
Product type Evaluation sample Flash product: MB96F38x
Mask ROM product: MB9638x
Product options
YS
NA
Low voltage reset persistently on / Single clock
RS Low voltage reset can be disabled / Single clock
YW Low voltage reset persistently on / Dual clock
RW Low voltage reset can be disabled / Dual clock
TS indep. 32KB Flash / Low voltage reset persistently on / Single clock
HS indep. 32KB Flash / Low voltage reset can be disabled / Single clock
TW indep. 32KB Flash / Low voltage reset persistently on / Dual clock
HW indep. 32KB Flash / Low voltage reset can be disabled / Dual clock
Flash/ROM RAM
128KB 6KB
ROM/Flash
memory emulation
by external RAM,
92KB internal RAM
MB96384Y*1, MB96384R*1
160KB 8KB MB96385Y*1, MB96385R*1, MB96F385Y*1, MB96F385R*1
288KB 16KB MB96F386Y, MB96F386R
416KB 16KB MB96F387Y, MB96F387R
576KB
[Flash A: 544KB,
Flash B: 32KB] 28KB MB96F388T*1, MB96F388H*1
832KB
[Flash A: 544KB,
Flash B: 288KB] 32KB MB96F389Y*1, MB96F389R*1,
Package BGA416 FPT-120P-M21
DMA 16 channels 7 channels
USART 10 channels 5 channels
I2C 2 channels 1 channel
A/D Converter 40 channels 16 channels
A/D Converter Reference
Voltage switch yes Only for MB96F386Y, MB96F386R, MB96F387Y, MB96F387R
16-bit Reload Timer 6 channels + 1
channel (for PPG) 4 channels + 1 channel (for PPG)
16-bit Free-Running Timer 4 channels 2 channels
16-bit Output Compare 12 channels 4 channels
MB96380 Series
FME-MB96380 rev 10 7
*1:Thesedevices are under developmentandspecificationispreliminary. These products under development may
change its specification without notice.
16-bit Input Capture 12 channels 8 channels
16-bit Programmable Pulse
Generator 20 channels 8 channels
CAN Interface 5 channels Other than below: 2 channels
MB96384Y*1, MB96384R*1, MB96(F)385Y*1, MB96(F)385R*1,:
1 channel
Stepping Motor Controller 6 channels 5 channels
External Interrupts 16 channels 8 channels
Non-Maskable Interrupt 1 channel
Sound generator 2 channels 2 channels
LCD Controller 4 COM x 72 SEG 4 COM x 65 SEG
Real Time Clock 1
I/O Ports 136 94 for part number with suffix "W", 96 for part number with suffix "S"
Alarm comparator 2 channels Other than below: 2 channels
MB96384Y*1, MB96384R*1, MB96(F)385Y*1, MB96(F)385R*1,:
1 channel
External bus interface Yes
Chip select 6 signals
Clock output function 2 channels
Low voltage reset Yes
On-chip RC-oscillator Yes
Features MB96V300B MB96(F)38x
MB96380 Series
8 FME-MB96380 rev 10
■BLOCK DIAGRAM
Block diagram of MB96(F)38x
5 ch.
PWM1M0 ... PWM1M4
PWM1P0 ... PWM1P4
PWM2M0 ... PWM2M4
PWM2P0 ... PWM2P4
DVCC
DVSS
DMA
Controller Boot ROM
Peripheral
Bus Bridge Peripheral
Bus Bridge
16FX Core Bus (CLKB)
USART
5 ch.
10-bit ADC
16 ch.
Alarm
Comparator
2 ch. 3)
CAN
Interface
2 ch. *3
External
Interrupt
Sound
Generator
LCD
driver
Real Time
Clock
controller/
Watchdog RAM Voltage
Regulator
SIN0...SIN2,SIN4,SIN5
SOT0...SOT2,SOT4,SOT5
SCK0...SCK2,SCK4,SCK5
ALARM0
ALARM1 *3
WOT
SGO0, SGO1, SGO0_R, SGO1_R
SGA0, SGA1, SGA0_R, SGA1_R
AVCC
AVSS
AVRH
AVRL/AVRH2 *4
AN0 ... AN15
ADTG
FRCK0
FRCK0_R
INT0 ... INT7
V0 ... V3
COM0 ... COM3
SEG0 ... SEG64
TX0, TX1 *3
RX0, RX1 *3
Peripheral Bus 1 (CLKP1)
Peripheral Bus 2 (CLKP2)
VCC
VSS
C
Stepper
Motor
Controller
I/O Timer 1
ICU 4/5/6/7
FRCK1
IN6 ... IN7
2 ch.
16FX
CPU Interrupt
Controller Clock &
Mode Controller
Flash
Memory A Memory Patch
Unit
AD00 ... AD15
A00 ... A23
ALE
RDX
WR(L)X, WRHX
HRQ
HAKX
RDY
ECLK
External Bus
Interface
LBX, UBX
CS0 ... CS5, CS3_R
NMI
CKOT0, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
I2C
1 ch.
SDA0
SCL0
16-bit Reload
Timer
4 ch.
TIN2_R
TIN0 ... TIN3
TOT1_R, TOT2_R
TOT0 ... TOT3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
IN0, IN1
IN0_R ... IN3_R
OUT0 ... OUT3
OUT0_R...OUT3_R
INT1_R ... INT7_R
IN4_R ... IN7_R
*1: X0A, X1A only available on devices with suffix “W”
Flash
Memory B
*2
*2: Flash B only available on MB96F388 and MB96F389 *3: CAN1 and ALARM1 not available on MB96384 and MB96(F)385
*4: AVRH2 only available on MB96F386 and MB96F387
16-bit PPG
8 ch.
RLT6 PPG0 ... PPG7
TTG0 ... TTG7
PPG0_R ... PPG5_R
MB96380 Series
FME-MB96380 rev 10 9
■PIN ASSIGNMENT
Pin assignment of MB96(F)38x
LQFP - 120
Package code (mold)
FPT-120P-M21
(FPT-120P-M21)
8912345 76 101112131415161718192021222324252627282930
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
616263646566676869707172737475767778798081828384858687888990
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
91
92
93
94
95
96
97
98
99
Vss
P00_3/INT6_R/A00/CS3_R/SEG15
P00_4/INT7_R/ALE/SEG16
P00_5/TTG2/TTG6/IN6/RDX/SEG17
P00_6/TTG3/IN7/WR(L)X/TTG7/SEG18
P00_7/SGO0/ECLK/SEG19
P01_0/SGA0/AD00/SEG20
P01_1/OUT0/CKOT1/AD01/SEG21
P01_2/OUT1/CKOTX1/AD02/SEG22
P01_3/PPG5/AD03/SEG23
P01_4/AD04/SIN4/SEG24
P01_5/AD05/SOT4/SEG25
P01_6/AD06/SCK4/SEG26
P01_7/CKOTX1_R/AD07/SEG27
P02_0/CKOT1_R/AD08/SEG28
P02_1/IN6_R/AD09/SEG29
P02_2/IN7_R/AD10/SEG30
P02_3/SGO0_R/AD11/SEG31
P02_4/SGA0_R/AD12/SEG32
P02_5/OUT0_R/AD13/SEG33
P02_6/OUT1_R/AD14/SEG34
P02_7/PPG5_R/AD15/SEG35
P03_0/V0/A16/SEG36
P03_1/V1/A17/SEG37
P03_2/V2/A18/SEG38
P03_3/V3/A19/SEG39
P03_4/INT4/RX0
P03_5/TX0
P03_6/NMI/INT0
Vcc
Vss
C
P03_7/INT1/SIN1/CS0/A20/SEG40
P13_0/INT2/SOT1/CS1/A21/SEG41
P13_1/INT3/SCK1/CS2/A22/SEG42
P13_2/PPG0/TIN0/FRCK1/CS3/A23/SEG43
P13_3/PPG1/TOT0/WOT/UBX/SEG44
P13_4/SIN0/INT6/SEG45
P13_5/SOT0/ADTG/INT7/SEG46
P13_6/SCK0/CKOTX0/LBX/SEG47
P13_7/PPG2/CKOT0/CS4/SEG48
P04_4/PPG3/SDA0
P04_5/PPG4/SCL0
P06_0/AN0/SCK5/IN2_R/SEG49
P06_1/AN1/SOT5/IN3_R/SEG50
P06_2/AN2/INT5/SIN5/SEG51
P06_3/AN3/FRCK0/SEG52
P06_4/AN4/IN0/TTG0/TTG4/SEG53
P06_5/AN5/IN1/TTG1/TTG5/SEG54
P06_6/AN6/TIN1/IN4_R/SEG55
P06_7/AN7/TOT1/IN5_R/SEG56
AVcc
AVRH
AVRL/AVRH2 *4
AVss
P05_0/AN8/ALARM0/SEG57
P05_1/AN9/ALARM1/SEG58 *2
P05_2/AN10/OUT2/SGO1/SEG59
P05_3/AN11/OUT3/SGA1/SEG60
Vcc
Vcc
P10_3/PWM2M4/PPG7
P10_2/PWM2P4/SCK2/PPG6
P10_1/PWM1M4/SOT2/TOT3
P10_0/PWM1P4/SIN2/TIN3
DVss
DVcc
P09_6/PWM2P3
P09_7/PWM2M3
P09_5/PWM1M3
P09_4/PWM1P3
P09_3/PWM2M2
P09_2/PWM2P2
P09_1/PWM1M2
P09_0/PWM1P2
P08_7/PWM2M1
P08_6/PWM2P1
P08_5/PWM1M1
DVss
DVcc
P08_4/PWM1P1
P08_3/PWM2M0
P08_2/PWM2P0
P08_1/PWM1M0
P08_0/PWM1P0
P05_7/AN15/TOT2/SGA1_R/SEG64
P05_6/AN14/TIN2/SGO1_R/SEG63
P05_5/AN13/TX1/SEG62 *3
P05_4/AN12/RX1/INT2_R/SEG61 *3
Vss
Vcc
P00_2/INT5_R/RDY/SEG14
P00_1/INT4_R/WRHX/SEG13
P00_0/INT3_R/HAKX/SEG12
P12_7/INT1_R/HRQ/SEG11
P12_6/TOT2_R/A15/SEG10
P12_5/TIN2_R/A14/SEG9
P12_4/OUT3_R/A13/SEG8
P12_3/OUT2_R/A12/SEG7
P12_2/TOT1_R/A11/SEG6
P12_1/TIN1_R/A10/SEG5
P12_0/IN1_R/A09/SEG4
P11_7/IN0_R/A08/SEG3
P11_6/FRCK0_R/A07/SEG2
P11_5/PPG4_R/A06/SEG1
P11_4/PPG3_R/A05/SEG0
P11_3/PPG2_R/A04/COM3
P11_2/PPG1_R/A03/COM2
P11_1/PPG0_R/A02/COM1
P11_0/A01/COM0/CS5
RSTX
X1A/P04_1 *1
X0A/P04_0 *1
Vss
X1
X0
MD2
MD1
MD0
Vss
*2: Alarm1 not available on MB96384 and MB96(F)385
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
*3: TX1 resp. RX1 not available on MB96384 and MB96(F)385
*4: AVRH2 only available on MB96F386 and MB96F387
MB96380 Series
10 FME-MB96380 rev 10
■PIN FUNCTION DESCRIPTION
Pin Function description (1 of 3)
Pin name Feature Description
ADn External bus
External bus interface (non multiplexed mode) data input/
output. External bus interface (multiplexed mode) address
output and data input/output
ADTG ADC A/D converter trigger input
ALARMn Alarm comparator Alarm Comparator n input
ALE External bus External bus Address Latch Enable output
An External bus External bus non-multiplexed address output
ANn ADC A/D converter channel n input
AVCC Supply Analog circuits power supply
AVRH ADC A/D converter high reference voltage input
AVRH2 ADC Alternative A/D converter high reference voltage input
AVRL ADC A/D converter low reference voltage input
AVSS Supply Analog circuits power supply
C Voltage regulator Internally regulated power supply stabilization capacitor pin
CKOTn Clock output function Clock Output function n output
CKOTn_R Clock output function Relocated Clock Output function n output
CKOTXn Clock output function Clock Output function n inverted output
CKOTXn_R Clock output function Relocated Clock Output function n inverted output
COMn LCD LCD COM pins
ECLK External bus External bus clock output
CSn External bus External bus chip select n output
CSn_R External bus Relocated External bus chip select n output
DVCC Supply SMC pins power supply
FRCKn Free Running Timer Free Running Timer n input
FRCKn_R Free Running Timer Relocated Free Running Timer n input
HAKX External bus External bus Hold Acknowledge
HRQ External bus External bus Hold Request
INn ICU Input Capture Unit n input
INn_R ICU Relocated Input Capture Unit n input
INTn External Interrupt External Interrupt n input
MB96380 Series
FME-MB96380 rev 10 11
INTn_R External Interrupt Relocated External Interrupt n input
LBX External bus External Bus Interface Lower Byte select strobe output
MDn Core Input pins for specifying the operating mode.
NMI External Interrupt Non-Maskable Interrupt input
OUTn OCU Output Compare Unit n waveform output
OUTn_R OCU Relocated Output Compare Unit n waveform output
Pxx_n GPIO General purpose IO
PPGn PPG Programmable Pulse Generator n output
PPGn_R PPG Relocated Programmable Pulse Generator n output
PWMn SMC SMC PWM high current
RDX External bus External bus interface read strobe output
RDY External bus External bus interface external wait state request input
RSTX Core Reset input
RXn CAN CAN interface n RX input
SCKn USART USART n serial clock input/output
SCLn I2C I2C interface n clock I/O input/output
SDAn I2C I2C interface n serial data I/O input/output
SEGn LCD LCD segment n
SGA Sound Generator SG amplitude output
SGO Sound Generator SG sound/tone output
SGA_R Sound Generator Relocated SG amplitude output
SGO_R Sound Generator Relocated SG sound/tone output
SINn USART USART n serial data input
SOTn USART USART n serial data output
TINn Reload Timer Reload Timer n event input
TINn_R Reload Timer Relocated Reload Timer n event input
TOTn Reload Timer Reload Timer n output
TOTn_R Reload Timer Relocated Reload Timer n output
TTGn PPG Programmable Pulse Generator n trigger input
TXn CAN CAN interface n TX output
Pin Function description (2 of 3)
Pin name Feature Description
MB96380 Series
12 FME-MB96380 rev 10
UBX External bus External Bus Interface Upper Byte select strobe output
Vn LCD LCD voltage references
VCC Supply Power supply
VSS Supply Power supply
WOT RTC Real Timer clock output
WRHX External bus External bus High byte write strobe output
WRLX/WRX External bus External bus Low byte / Word write strobe output
X0 Clock Oscillator input
X0A Clock Subclock Oscillator input (only for devices with suffix "W")
X1 Clock Oscillator output
X1A Clock Subclock Oscillator output (only for devices with suffix "W")
Pin Function description (3 of 3)
Pin name Feature Description
MB96380 Series
FME-MB96380 rev 10 13
■PIN CIRCUIT TYPE
Pin circuit types (1 of 2)
FPT-120P-M21
Pin no. Circuit
type *1
1 Supply
2F
3 to 11 J
12,13 N
14 to 21 K
22 Supply
23 to 24 G
25 Supply
26 to 29 K
30,31 Supply
32 to 35 K
36 to 40 M
41,42 Supply
43 to 52 M
53,54 Supply
55 to 59 M
60, 61 Supply
62 to 64 C
65, 66 A
67 Supply
68,69 B *2
68,69 H *3
70 E
71 to 89 J
90 to 91 Supply
92 to 112 J
113 to
116 L
MB96380 Series
FME-MB96380 rev 10 15
■I/O CIRCUIT TYPE
Type Circuit Remarks
A High-speed oscillation circuit:
• Programmable between oscillation mode (ex-
ternalcrystal or resonator connected to X0/X1
pins)andFastexternalClockInput(FCI)mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
B Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2*5MΩ. Feedback resistor is grounded in the
center when the oscillator is disabled
C • Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
E • CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
X1
X0
R
R
MRFBE
Xout
FCI
0
1
FCI or osc disable
X1A
X0A
R
R
SRFBE
Xout
osc disable
RHysteresis
inputs
R
Pull-up
Resistor
Hysteresis
inputs
MB96380 Series
16 FME-MB96380 rev 10
F • Power supply input protection circuit
G • A/Dconverterref+(AVRH/AVRH2)powersup-
ply input pin with protection circuit
• Flash devices do not have a protection circuit
against VCC for pins AVRH/AVRH2
• DeviceswithoutAVRHreferenceswitchdonot
have an analog switch for the AVRL pin
H • CMOS level output (programmable IOL =5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
Type Circuit Remarks
ANE
AVR
ANE
Pout
pull-up control
Nout
R
Hysteresis input
Automotive input
TTL input
Hysteresis input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
MB96380 Series
FME-MB96380 rev 10 17
J • CMOS level output (programmable IOL =5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• SEG or COM output
K • CMOS level output (programmable IOL =5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• SEG output
Type Circuit Remarks
Pout
pull-up control
Nout
R
Hysteresis input
Automotive input
TTL input
Hysteresis input
SEG, COM output
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Pout
pull-up control
Nout
R
Hysteresis input
Automotive input
TTL input
Hysteresis input
SEG output
Analog input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
MB96380 Series
18 FME-MB96380 rev 10
L • CMOS level output (programmable IOL =5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• Vx input
• SEG output
M • CMOS level output (programmable IOL =5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL =
30mA, IOH = -30mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
Type Circuit Remarks
Standby control
for input shutdown
Pout
pull-up control
Nout
R
Hysteresis input
Hysteresis input
SEG output
Analog input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Vx input
TTL input
Automotive input
Pout
pull-up control
Nout
R
Hysteresis input
Automotive input
TTL input
Hysteresis input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
MB96380 Series
FME-MB96380 rev 10 19
N • CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
*1:N-channeltransistorhasslewratecontrolac-
cording to I2C spec, irrespective of usage
Type Circuit Remarks
Pout
pull-up control
Nout *1
R
Hysteresis input
Automotive input
TTL input
Hysteresis input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
MB96380 Series
20 FME-MB96380 rev 10
■MEMORY MAP
MB96V300B MB96(F)38x
FF:FFFFH
Emulation ROM USER ROM /
External Bus*4
DE:0000H
External Bus External Bus
10:0000H
0F:E000HBoot-ROM Boot-ROM
Reserved
Reserved
0E:0000H
External RAM
02:0000H
Internal RAM
bank 1
Reserved
RAMEND1*2 Internal RAM
bank 1 RAM availability de-
pending on the device
RAMSTART12
01:0000HReserved
ROM/RAM MIRROR ROM/RAM MIRROR
00:8000H
Internal RAM
bank 0
Internal RAM
bank 0
RAMSTART0*2
Reserved
RAMSTART0*3 External Bus
External Bus end
address*2
00:0C00HExternal Bus
Peripherals Peripherals
00:0380H
00:0180HGPR*1 GPR*1
00:0100HDMA DMA
00:00F0HExternal Bus External Bus
00:0000HPeripheral Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the ■USER ROM MEMORY MAP FOR FLASH DEVICES and
■ USER ROM MEMORY MAP FOR MASK ROM DEVICES on the following pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
MB96380 Series
FME-MB96380 rev 10 21
■RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Devices Bank 0
RAM size Bank 1
RAM size External Bus
end address RAMSTART0 RAMSTART1 RAMEND1
MB96384 6KByte - 00:61FFH00:6A40H--
MB96385/F385 8KByte - 00:61FFH00:6240H--
MB96F386,
MB96F387 16KByte - 00:41FFH00:4240H--
MB96F388 28KByte - 00:11FFH00:1240H--
MB96F389 28KByte 4KByte 00:11FFH00:1240H01:8000H01:8FFFH
MB96380 Series
22 FME-MB96380 rev 10
■USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F385R MB96F386R MB96F387R
MB96F385Y MB96F386Y MB96F387Y
Alternative mode
CPU address Flash memory
mode address Flash size
160kByte Flash size
288kByte Flash size
416kByte
FF:FFFFH
FF:0000H3F:FFFFH
3F:0000HS39 - 64K S39 - 64K S39 - 64K
Flash A
FE:FFFFH
FE:0000H3E:FFFFH
3E:0000HS38 - 64K S38 - 64K S38 - 64K
FD:FFFFH
FD:0000H3D:FFFFH
3D:0000H
External bus
S37 - 64K S37 - 64K
FC:FFFFH
FC:0000H3C:FFFFH
3C:0000HS36 - 64K S36 - 64K
FB:FFFFH
FB:0000H3B:FFFFH
3B:0000H
External bus
S35 - 64K
FA:FFFFH
FA:0000H3A:FFFFH
3A:0000HS34 - 64K
F9:FFFFH
F9:0000H39:FFFFH
39:0000H
External bus
F8:FFFFH
F8:0000H38:FFFFH
38:0000H
F7:FFFFH
F7:0000H37:FFFFH
37:0000H
F6:FFFFH
F6:0000H36:FFFFH
36:0000H
F5:FFFFH
F5:0000H35:FFFFH
35:0000H
F4:FFFFH
F4:0000H34:FFFFH
34:0000H
F3:FFFFH
F3:0000H33:FFFFH
33:0000H
F2:FFFFH
F2:0000H32:FFFFH
32:0000H
F1:FFFFH
F1:0000H31:FFFFH
31:0000H
F0:FFFFH
F0:0000H30:FFFFH
30:0000H
E0:FFFFH
E0:0000H
DF:FFFFH
DF:8000HReserved Reserved Reserved
DF:7FFFH
DF:6000H1F:7FFFH
1F:6000HSA3 - 8K SA3 - 8K SA3 - 8K
Flash A
DF:5FFFH
DF:4000H1F:5FFFH
1F:4000HSA2 - 8K SA2 - 8K SA2 - 8K
DF:3FFFH
DF:2000H1F:3FFFH
1F:2000HSA1 - 8K SA1 - 8K SA1 - 8K
DF:1FFFH
DF:0000H1F:1FFFH
1F:0000HSA0 - 8K *1 SA0 - 8K *1 SA0 - 8K *1
DE:FFFFH
DE:0000HReserved Reserved Reserved
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
MB96380 Series
FME-MB96380 rev 10 23
MB96F388T MB96F389R
MB96F388H MB96F389Y
Alternative mode
CPU address Flash memory
mode address Flash size
576kByte Flash size
832kByte
FF:FFFFH
FF:0000H3F:FFFFH
3F:0000HS39 - 64K S39 - 64K
FE:FFFFH
FE:0000H3E:FFFFH
3E:0000HS38 - 64K S38 - 64K
Flash A
FD:FFFFH
FD:0000H3D:FFFFH
3D:0000HS37 - 64K S37 - 64K
FC:FFFFH
FC:0000H3C:FFFFH
3C:0000HS36 - 64K S36 - 64K
FB:FFFFH
FB:0000H3B:FFFFH
3B:0000HS35 - 64K S35 - 64K
FA:FFFFH
FA:0000H3A:FFFFH
3A:0000HS34 - 64K S34 - 64K
F9:FFFFH
F9:0000H39:FFFFH
39:0000HS33 - 64K S33 - 64K
F8:FFFFH
F8:0000H38:FFFFH
38:0000HS32 - 64K S32 - 64K
F7:FFFFH
F7:0000H37:FFFFH
37:0000H
External bus
S31 - 64K
Flash B
F6:FFFFH
F6:0000H36:FFFFH
36:0000HS30 - 64K
F5:FFFFH
F5:0000H35:FFFFH
35:0000HS29 - 64K
F4:FFFFH
F4:0000H34:FFFFH
34:0000HS28 - 64K
F3:FFFFH
F3:0000H33:FFFFH
33:0000H
External bus
F2:FFFFH
F2:0000H32:FFFFH
32:0000H
F1:FFFFH
F1:0000H31:FFFFH
31:0000H
F0:FFFFH
F0:0000H30:FFFFH
30:0000H
E0:FFFFH
E0:0000H
DF:FFFFH
DF:8000HReserved Reserved
DF:7FFFH
DF:6000H1F:7FFFH
1F:6000HSA3 - 8K SA3 - 8K
Flash A
DF:5FFFH
DF:4000H1F:5FFFH
1F:4000HSA2 - 8K SA2 - 8K
DF:3FFFH
DF:2000H1F:3FFFH
1F:2000HSA1 - 8K SA1 - 8K
DF:1FFFH
DF:0000H1F:1FFFH
1F:0000HSA0 - 8K *1 SA0 - 8K *1
DE:FFFFH
DE:8000HReserved Reserved
DE:7FFFH
DE:6000H1E:7FFFH
1E:6000HSB3 - 8K SB3 - 8K
Flash B
DE:5FFFH
DE:4000H1E:5FFFH
1E:4000HSB2 - 8K SB2 - 8K
DE:3FFFH
DE:2000H1E:3FFFH
1E:2000HSB1 - 8K SB1 - 8K
DE:1FFFH
DE:0000H1E:1FFFH
1E:0000HSB0 - 8K *2 SB0 - 8K *2
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
*2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH
MB96380 Series
24 FME-MB96380 rev 10
■USER ROM MEMORY MAP FOR MASK ROM DEVICES
MB96384 MB96385
CPU address ROM size
128kByte ROM size
160kByte
FF:FFFFH
FF:0000H128K ROM 128K ROM
FE:FFFFH
FE:0000H
FD:FFFFH
E0:0000H
External bus External bus
DF:FFFFH
DF:8000HReserved Reserved
DF:7FFFH
DF:0080H32K ROM
DF:007FH
DF:0000HROM configuration
block RCB ROM configuration
block RCB
DE:FFFFH
DE:0000HReserved Reserved
MB96380 Series
FME-MB96380 rev 10 25
■SERIAL PROGRAMMING COMMUNICATION INTERFACE
Note:If aFlashprogrammerand its softwareneeds touse a handshakingpin,Fujitsu suggeststothe tool vendor
to support at least port P00_1 on pin 88.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode)
MB96F38x
Pin number USART Number Normal function
LQFP-120
8
USART0
SIN0
9SOT0
10 SCK0
3
USART1
SIN1
4SOT1
5 SCK1
56
USART2
SIN2
57 SOT2
58 SCK2
MB96380 Series
26 FME-MB96380 rev 10
■I/O MAP
I/O map MB96(F)38x (1 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
000000HI/O Port P00 - Port Data Register PDR00 - R/W
000001HI/O Port P01 - Port Data Register PDR01 - R/W
000002HI/O Port P02 - Port Data Register PDR02 - R/W
000003HI/O Port P03 - Port Data Register PDR03 - R/W
000004HI/O Port P04 - Port Data Register PDR04 - R/W
000005HI/O Port P05 - Port Data Register PDR05 - R/W
000006HI/O Port P06 - Port Data Register PDR06 - R/W
000007HReserved - - -
000008HI/O Port P08 - Port Data Register PDR08 - R/W
000009HI/O Port P09 - Port Data Register PDR09 - R/W
00000AHI/O Port P10 - Port Data Register PDR10 - R/W
00000BHI/O Port P11 - Port Data Register PDR11 - R/W
00000CHI/O Port P12 - Port Data Register PDR12 - R/W
00000DHI/O Port P13 - Port Data Register PDR13 - R/W
00000EH-
000017HReserved - - -
000018HADC0 - Control Status register Low ADCSL ADCS R/W
000019HADC0 - Control Status register High ADCSH - R/W
00001AHADC0 - Data Register Low ADCRL ADCR R
00001BHADC0 - Data Register High ADCRH - R
00001CHADC0 - Setting Register - ADSR R/W
00001DHADC0 - Setting Register - - R/W
00001EHADC0 - Extended Configuration Register ADECR - R/W
00001FHReserved - - -
000020HFRT0 - Data register of free-running timer - TCDT0 R/W
000021HFRT0 - Data register of free-running timer - - R/W
000022HFRT0 - Control status register of free-running timer
Low TCCSL0 TCCS0 R/W
000023HFRT0 - Control status register of free-running timer
High TCCSH0 - R/W
MB96380 Series
FME-MB96380 rev 10 27
000024HFRT1 - Data register of free-running timer - TCDT1 R/W
000025HFRT1 - Data register of free-running timer - - R/W
000026HFRT1 - Control status register of free-running timer
Low TCCSL1 TCCS1 R/W
000027HFRT1 - Control status register of free-running timer
High TCCSH1 - R/W
000028HOCU0 - Output Compare Control Status OCS0 - R/W
000029HOCU1 - Output Compare Control Status OCS1 - R/W
00002AHOCU0 - Compare Register - OCCP0 R/W
00002BHOCU0 - Compare Register - - R/W
00002CHOCU1 - Compare Register - OCCP1 R/W
00002DHOCU1 - Compare Register - - R/W
00002EHOCU2 - Output Compare Control Status OCS2 - R/W
00002FHOCU3 - Output Compare Control Status OCS3 - R/W
000030HOCU2 - Compare Register - OCCP2 R/W
000031HOCU2 - Compare Register - R/W
000032HOCU3 - Compare Register - OCCP3 R/W
000033HOCU3 - Compare Register - - R/W
000034H-
00003FHReserved - - -
000040HICU0/ICU1 - Control Status Register ICS01 - R/W
000041HICU0/ICU1 - Edge register ICE01 - R/W
000042HICU0 - Capture Register Low IPCPL0 IPCP0 R
000043HICU0 - Capture Register High IPCPH0 - R
000044HICU1 - Capture Register Low IPCPL1 IPCP1 R
000045HICU1 - Capture Register High IPCPH1 - R
000046HICU2/ICU3 - Control Status Register ICS23 - R/W
000047HICU2/ICU3 - Edge register ICE23 - R/W
000048HICU2 - Capture Register Low IPCPL2 IPCP2 R
000049HICU2 - Capture Register High IPCPH2 - R
00004AHICU3 - Capture Register Low IPCPL3 IPCP3 R
I/O map MB96(F)38x (2 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
28 FME-MB96380 rev 10
00004BHICU3 - Capture Register High IPCPH3 - R
00004CHICU4/ICU5 - Control Status Register ICS45 - R/W
00004DHICU4/ICU5 - Edge register ICE45 - R/W
00004EHICU4 - Capture Register Low IPCPL4 IPCP4 R
00004FHICU4 - Capture Register High IPCPH4 - R
000050HICU5 - Capture Register Low IPCPL5 IPCP5 R
000051HICU5 - Capture Register High IPCPH5 - R
000052HICU6/ICU7 - Control Status Register ICS67 - R/W
000053HICU6/ICU7 - Edge register ICE67 - R/W
000054HICU6 - Capture Register Low IPCPL6 IPCP6 R
000055HICU6 - Capture Register High IPCPH6 - R
000056HICU7 - Capture Register Low IPCPL7 IPCP7 R
000057HICU7 - Capture Register High IPCPH7 - R
000058HEXTINT0 - External Interrupt Enable Register ENIR0 - R/W
000059HEXTINT0 - External Interrupt Interrupt request
Register EIRR0 - R/W
00005AHEXTINT0 - External Interrupt Level Select Low ELVRL0 ELVR0 R/W
00005BHEXTINT0 - External Interrupt Level Select High ELVRH0 - R/W
00005CH-
00005FHReserved - - -
000060HRLT0 - Timer Control Status Register Low TMCSRL0 TMCSR0 R/W
000061HRLT0 - Timer Control Status Register High TMCSRH0 - R/W
000062HRLT0 - Reload Register - for writing - TMRLR0 W
000062HRLT0 - Reload Register - for reading - TMR0 R
000063HRLT0 - Reload Register - for writing - - W
000063HRLT0 - Reload Register - for reading - - R
000064HRLT1 - Timer Control Status Register Low TMCSRL1 TMCSR1 R/W
000065HRLT1 - Timer Control Status Register High TMCSRH1 - R/W
000066HRLT1 - Reload Register - for writing - TMRLR1 W
000066HRLT1 - Reload Register - for reading - TMR1 R
000067HRLT1 - Reload Register - for writing - - W
I/O map MB96(F)38x (3 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 29
000067HRLT1 - Reload Register - for reading - - R
000068HRLT2 - Timer Control Status Register Low TMCSRL2 TMCSR2 R/W
000069HRLT2 - Timer Control Status Register High TMCSRH2 - R/W
00006AHRLT2 - Reload Register - for writing - TMRLR2 W
00006AHRLT2 - Reload Register - for reading - TMR2 R
00006BHRLT2 - Reload Register - for writing - - W
00006BHRLT2 - Reload Register - for reading R
00006CHRLT3 - Timer Control Status Register Low TMCSRL3 TMCSR3 R/W
00006DHRLT3 - Timer Control Status Register High TMCSRH3 - R/W
00006EHRLT3 - Reload Register - for writing - TMRLR3 W
00006EHRLT3 - Reload Register - for reading - TMR3 R
00006FHRLT3 - Reload Register - for writing - - W
00006FHRLT3 - Reload Register - for reading - R
000070HRLT6 - Timer Control Status Register Low (dedic.
RLT for PPG) TMCSRL6 TMCSR6 R/W
000071HRLT6 - Timer Control Status Register High (dedic.
RLT for PPG) TMCSRH6 - R/W
000072HRLT6 - Reload Register (dedic. RLT for PPG) - for
writing - TMRLR6 W
000072HRLT6 - Reload Register (dedic. RLT for PPG) - for
reading -TMR6R
000073HRLT6 - Reload Register (dedic. RLT for PPG) - for
writing --W
000073HRLT6 - Reload Register (dedic. RLT for PPG) - for
reading --R
000074HPPG3-PPG0 - General Control register 1 Low GCN1L0 GCN10 R/W
000075HPPG3-PPG0 - General Control register 1 High GCN1H0 - R/W
000076HPPG3-PPG0 - General Control register 2 Low GCN2L0 GCN20 R/W
000077HPPG3-PPG0 - General Control register 2 High GCN2H0 - R/W
000078HPPG0 - Timer register - PTMR0 R
000079HPPG0 - Timer register - - R
00007AHPPG0 - Period setting register - PCSR0 W
I/O map MB96(F)38x (4 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
30 FME-MB96380 rev 10
00007BHPPG0 - Period setting register - - W
00007CHPPG0 - Duty cycle register - PDUT0 W
00007DHPPG0 - Duty cycle register - - W
00007EHPPG0 - Control status register Low PCNL0 PCN0 R/W
00007FHPPG0 - Control status register High PCNH0 - R/W
000080HPPG1 - Timer register - PTMR1 R
000081HPPG1 - Timer register - - R
000082HPPG1 - Period setting register - PCSR1 W
000083HPPG1 - Period setting register - - W
000084HPPG1 - Duty cycle register - PDUT1 W
000085HPPG1 - Duty cycle register - - W
000086HPPG1 - Control status register Low PCNL1 PCN1 R/W
000087HPPG1 - Control status register High PCNH1 - R/W
000088HPPG2 - Timer register - PTMR2 R
000089HPPG2 - Timer register - - R
00008AHPPG2 - Period setting register - PCSR2 W
00008BHPPG2 - Period setting register - - W
00008CHPPG2 - Duty cycle register - PDUT2 W
00008DHPPG2 - Duty cycle register - - W
00008EHPPG2 - Control status register Low PCNL2 PCN2 R/W
00008FHPPG2 - Control status register High PCNH2 - R/W
000090HPPG3 - Timer register - PTMR3 R
000091HPPG3 - Timer register - - R
000092HPPG3 - Period setting register - PCSR3 W
000093HPPG3 - Period setting register - - W
000094HPPG3 - Duty cycle register - PDUT3 W
000095HPPG3 - Duty cycle register - - W
000096HPPG3 - Control status register Low PCNL3 PCN3 R/W
000097HPPG3 - Control status register High PCNH3 - R/W
000098HPPG7-PPG4 - General Control register 1 Low GCN1L1 GCN11 R/W
I/O map MB96(F)38x (5 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 31
000099HPPG7-PPG4 - General Control register 1 High GCN1H1 - R/W
00009AHPPG7-PPG4 - General Control register 2 Low GCN2L1 GCN21 R/W
00009BHPPG7-PPG4 - General Control register 2 High GCN2H1 - R/W
00009CHPPG4 - Timer register - PTMR4 R
00009DHPPG4 - Timer register - - R
00009EHPPG4 - Period setting register - PCSR4 W
00009FHPPG4 - Period setting register - - W
0000A0HPPG4 - Duty cycle register - PDUT4 W
0000A1HPPG4 - Duty cycle register - - W
0000A2HPPG4 - Control status register Low PCNL4 PCN4 R/W
0000A3HPPG4 - Control status register High PCNH4 - R/W
0000A4HPPG5 - Timer register - PTMR5 R
0000A5HPPG5 - Timer register - - R
0000A6HPPG5 - Period setting register - PCSR5 W
0000A7HPPG5 - Period setting register - - W
0000A8HPPG5 - Duty cycle register - PDUT5 W
0000A9HPPG5 - Duty cycle register - - W
0000AAHPPG5 - Control status register Low PCNL5 PCN5 R/W
0000ABHPPG5 - Control status register High PCNH5 - R/W
0000ACHI2C0 - Bus Status Register IBSR0 - R
0000ADHI2C0 - Bus Control Register IBCR0 - R/W
0000AEHI2C0 - Ten bit Slave address Register Low ITBAL0 ITBA0 R/W
0000AFHI2C0 - Ten bit Slave address Register High ITBAH0 - R/W
0000B0HI2C0 - Ten bit Address mask Register Low ITMKL0 ITMK0 R/W
0000B1HI2C0 - Ten bit Address mask Register High ITMKH0 - R/W
0000B2HI2C0 - Seven bit Slave address Register ISBA0 - R/W
0000B3HI2C0 - Seven bit Address mask Register ISMK0 - R/W
0000B4HI2C0 - Data Register IDAR0 - R/W
0000B5HI2C0 - Clock Control Register ICCR0 - R/W
I/O map MB96(F)38x (6 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
32 FME-MB96380 rev 10
0000B6H-
0000BFHReserved - - -
0000C0HUSART0 - Serial Mode Register SMR0 - R/W
0000C1HUSART0 - Serial Control Register SCR0 - R/W
0000C2HUSART0 - TX Register TDR0 - W
0000C2HUSART0 - RX Register RDR0 - R
0000C3HUSART0 - Serial Status SSR0 - R/W
0000C4HUSART0 - Control/Com. Register ECCR0 - R/W
0000C5HUSART0 - Ext. Status Register ESCR0 - R/W
0000C6HUSART0 - Baud Rate Generator Register Low BGRL0 BGR0 R/W
0000C7HUSART0 - Baud Rate Generator Register High BGRH0 - R/W
0000C8HUSART0 - Extended Serial Interrupt Register ESIR0 - R/W
0000C9HReserved - - -
0000CAHUSART1 - Serial Mode Register SMR1 - R/W
0000CBHUSART1 - Serial Control Register SCR1 - R/W
0000CCHUSART1 - TX Register TDR1 - W
0000CCHUSART1 - RX Register RDR1 - R
0000CDHUSART1 - Serial Status SSR1 - R/W
0000CEHUSART1 - Control/Com. Register ECCR1 - R/W
0000CFHUSART1 - Ext. Status Register ESCR1 - R/W
0000D0HUSART1 - Baud Rate Generator Register Low BGRL1 BGR1 R/W
0000D1HUSART1 - Baud Rate Generator Register High BGRH1 - R/W
0000D2HUSART1 - Extended Serial Interrupt Register ESIR1 - R/W
0000D3HReserved - - -
0000D4HUSART2 - Serial Mode Register SMR2 - R/W
0000D5HUSART2 - Serial Control Register SCR2 - R/W
0000D6HUSART2 - TX Register TDR2 - W
0000D6HUSART2 - RX Register RDR2 - R
0000D7HUSART2 - Serial Status SSR2 - R/W
0000D8HUSART2 - Control/Com. Register ECCR2 - R/W
I/O map MB96(F)38x (7 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 33
0000D9HUSART2 - Ext. Status Register ESCR2 - R/W
0000DAHUSART2 - Baud Rate Generator Register Low BGRL2 BGR2 R/W
0000DBHUSART2 - Baud Rate Generator Register High BGRH2 - R/W
0000DCHUSART2 - Extended Serial Interrupt Register ESIR2 - R/W
0000DDH-
0000EFHReserved - - -
0000F0H-
0000FFHExternal Bus area EXTBUS0 - R/W
000100HDMA0 - Buffer address pointer low byte BAPL0 - R/W
000101HDMA0 - Buffer address pointer middle byte BAPM0 - R/W
000102HDMA0 - Buffer address pointer high byte BAPH0 - R/W
000103HDMA0 - DMA control register DMACS0 - R/W
000104HDMA0 - I/O register address pointer low byte IOAL0 IOA0 R/W
000105HDMA0 - I/O register address pointer high byte IOAH0 - R/W
000106HDMA0 - Data counter low byte DCTL0 DCT0 R/W
000107HDMA0 - Data counter high byte DCTH0 - R/W
000108HDMA1 - Buffer address pointer low byte BAPL1 - R/W
000109HDMA1 - Buffer address pointer middle byte BAPM1 - R/W
00010AHDMA1 - Buffer address pointer high byte BAPH1 - R/W
00010BHDMA1 - DMA control register DMACS1 - R/W
00010CHDMA1 - I/O register address pointer low byte IOAL1 IOA1 R/W
00010DHDMA1 - I/O register address pointer high byte IOAH1 - R/W
00010EHDMA1 - Data counter low byte DCTL1 DCT1 R/W
00010FHDMA1 - Data counter high byte DCTH1 - R/W
000110HDMA2 - Buffer address pointer low byte BAPL2 - R/W
000111HDMA2 - Buffer address pointer middle byte BAPM2 - R/W
000112HDMA2 - Buffer address pointer high byte BAPH2 - R/W
000113HDMA2 - DMA control register DMACS2 - R/W
000114HDMA2 - I/O register address pointer low byte IOAL2 IOA2 R/W
000115HDMA2 - I/O register address pointer high byte IOAH2 - R/W
000116HDMA2 - Data counter low byte DCTL2 DCT2 R/W
I/O map MB96(F)38x (8 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
34 FME-MB96380 rev 10
000117HDMA2 - Data counter high byte DCTH2 - R/W
000118HDMA3 - Buffer address pointer low byte BAPL3 - R/W
000119HDMA3 - Buffer address pointer middle byte BAPM3 - R/W
00011AHDMA3 - Buffer address pointer high byte BAPH3 - R/W
00011BHDMA3 - DMA control register DMACS3 - R/W
00011CHDMA3 - I/O register address pointer low byte IOAL3 IOA3 R/W
00011DHDMA3 - I/O register address pointer high byte IOAH3 - R/W
00011EHDMA3 - Data counter low byte DCTL3 DCT3 R/W
00011FHDMA3 - Data counter high byte DCTH3 - R/W
000120HDMA4 - Buffer address pointer low byte BAPL4 - R/W
000121HDMA4 - Buffer address pointer middle byte BAPM4 - R/W
000122HDMA4 - Buffer address pointer high byte BAPH4 - R/W
000123HDMA4 - DMA control register DMACS4 - R/W
000124HDMA4 - I/O register address pointer low byte IOAL4 IOA4 R/W
000125HDMA4 - I/O register address pointer high byte IOAH4 - R/W
000126HDMA4 - Data counter low byte DCTL4 DCT4 R/W
000127HDMA4 - Data counter high byte DCTH4 - R/W
000128HDMA5 - Buffer address pointer low byte BAPL5 - R/W
000129HDMA5 - Buffer address pointer middle byte BAPM5 - R/W
00012AHDMA5 - Buffer address pointer high byte BAPH5 - R/W
00012BHDMA5 - DMA control register DMACS5 - R/W
00012CHDMA5 - I/O register address pointer low byte IOAL5 IOA5 R/W
00012DHDMA5 - I/O register address pointer high byte IOAH5 - R/W
00012EHDMA5 - Data counter low byte DCTL5 DCT5 R/W
00012FHDMA5 - Data counter high byte DCTH5 - R/W
000130HDMA6 - Buffer address pointer low byte BAPL6 - R/W
000131HDMA6 - Buffer address pointer middle byte BAPM6 - R/W
000132HDMA6 - Buffer address pointer high byte BAPH6 - R/W
000133HDMA6 - DMA control register DMACS6 - R/W
000134HDMA6 - I/O register address pointer low byte IOAL6 IOA6 R/W
I/O map MB96(F)38x (9 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 35
000135HDMA6 - I/O register address pointer high byte IOAH6 - R/W
000136HDMA6 - Data counter low byte DCTL6 DCT6 R/W
000137HDMA6 - Data counter high byte DCTH6 - R/W
000138H-
00017FHReserved - - -
000180H-
00037FHCPU - General Purpose registers (RAM access) GPR_RAM - R/W
000380HDMA0 - Interrupt select DISEL0 - R/W
000381HDMA1 - Interrupt select DISEL1 - R/W
000382HDMA2 - Interrupt select DISEL2 - R/W
000383HDMA3 - Interrupt select DISEL3 - R/W
000384HDMA4 - Interrupt select DISEL4 - R/W
000385HDMA5 - Interrupt select DISEL5 - R/W
000386HDMA6 - Interrupt select DISEL6 - R/W
000387H-
00038FHReserved - - -
000390HDMA - Status register low byte DSRL DSR R/W
000391HDMA - Status register high byte DSRH - R/W
000392HDMA - Stop status register low byte DSSRL DSSR R/W
000393HDMA - Stop status register high byte DSSRH - R/W
000394HDMA - Enable register low byte DERL DER R/W
000395HDMA - Enable register high byte DERH - R/W
000396H-
00039FHReserved - - -
0003A0HInterrupt level register ILR ICR R/W
0003A1HInterrupt index register IDX - R/W
0003A2HInterrupt vector table base register Low TBRL TBR R/W
0003A3HInterrupt vector table base register High TBRH - R/W
0003A4HDelayed Interrupt register DIRR - R/W
0003A5HNon Maskable Interrupt register NMI - R/W
0003A6H-
0003ABHReserved - - -
I/O map MB96(F)38x (10 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
36 FME-MB96380 rev 10
0003ACHEDSU communication interrupt selection Low EDSU2L EDSU2 R/W
0003ADHEDSU communication interrupt selection High EDSU2H - R/W
0003AEHROM mirror control register ROMM - R/W
0003AFHEDSU configuration register EDSU - R/W
0003B0HMemory patch control/status register ch 0/1 - PFCS0 R/W
0003B1HMemory patch control/status register ch 0/1 - - R/W
0003B2HMemory patch control/status register ch 2/3 - PFCS1 R/W
0003B3HMemory patch control/status register ch 2/3 - - R/W
0003B4HMemory patch control/status register ch 4/5 - PFCS2 R/W
0003B5HMemory patch control/status register ch 4/5 - - R/W
0003B6HMemory patch control/status register ch 6/7 - PFCS3 R/W
0003B7HMemory patch control/status register ch 6/7 - - R/W
0003B8HMemory Patch function - Patch address 0 low PFAL0 - R/W
0003B9HMemory Patch function - Patch address 0 middle PFAM0 - R/W
0003BAHMemory Patch function - Patch address 0 high PFAH0 - R/W
0003BBHMemory Patch function - Patch address 1 low PFAL1 - R/W
0003BCHMemory Patch function - Patch address 1 middle PFAM1 - R/W
0003BDHMemory Patch function - Patch address 1 high PFAH1 - R/W
0003BEHMemory Patch function - Patch address 2 low PFAL2 - R/W
0003BFHMemory Patch function - Patch address 2 middle PFAM2 - R/W
0003C0HMemory Patch function - Patch address 2 high PFAH2 - R/W
0003C1HMemory Patch function - Patch address 3 low PFAL3 - R/W
0003C2HMemory Patch function - Patch address 3 middle PFAM3 - R/W
0003C3HMemory Patch function - Patch address 3 high PFAH3 - R/W
0003C4HMemory Patch function - Patch address 4 low PFAL4 - R/W
0003C5HMemory Patch function - Patch address 4 middle PFAM4 - R/W
0003C6HMemory Patch function - Patch address 4 high PFAH4 - R/W
0003C7HMemory Patch function - Patch address 5 low PFAL5 - R/W
0003C8HMemory Patch function - Patch address 5 middle PFAM5 - R/W
0003C9HMemory Patch function - Patch address 5 high PFAH5 - R/W
I/O map MB96(F)38x (11 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 37
0003CAHMemory Patch function - Patch address 6 low PFAL6 - R/W
0003CBHMemory Patch function - Patch address 6 middle PFAM6 - R/W
0003CCHMemory Patch function - Patch address 6 high PFAH6 - R/W
0003CDHMemory Patch function - Patch address 7 low PFAL7 - R/W
0003CEHMemory Patch function - Patch address 7 middle PFAM7 - R/W
0003CFHMemory Patch function - Patch address 7 high PFAH7 - R/W
0003D0HMemory Patch function - Patch data 0 Low PFDL0 PFD0 R/W
0003D1HMemory Patch function - Patch data 0 High PFDH0 - R/W
0003D2HMemory Patch function - Patch data 1 Low PFDL1 PFD1 R/W
0003D3HMemory Patch function - Patch data 1 High PFDH1 - R/W
0003D4HMemory Patch function - Patch data 2 Low PFDL2 PFD2 R/W
0003D5HMemory Patch function - Patch data 2 High PFDH2 - R/W
0003D6HMemory Patch function - Patch data 3 Low PFDL3 PFD3 R/W
0003D7HMemory Patch function - Patch data 3 High PFDH3 - R/W
0003D8HMemory Patch function - Patch data 4 Low PFDL4 PFD4 R/W
0003D9HMemory Patch function - Patch data 4 High PFDH4 - R/W
0003DAHMemory Patch function - Patch data 5 Low PFDL5 PFD5 R/W
0003DBHMemory Patch function - Patch data 5 High PFDH5 - R/W
0003DCHMemory Patch function - Patch data 6 Low PFDL6 PFD6 R/W
0003DDHMemory Patch function - Patch data 6 High PFDH6 - R/W
0003DEHMemory Patch function - Patch data 7 Low PFDL7 PFD7 R/W
0003DFHMemory Patch function - Patch data 7 High PFDH7 - R/W
0003E0H-
0003F0HReserved - - -
0003F1HMemory Control Status Register A MCSRA - R/W
0003F2HMemory Timing Configuration Register A Low MTCRAL MTCRA R/W
0003F3HMemory Timing Configuration Register A High MTCRAH - R/W
0003F4HReserved - - -
0003F5HMemory Control Status Register B MCSRB - R/W
0003F6HMemory Timing Configuration Register B Low MTCRBL MTCRB R/W
I/O map MB96(F)38x (12 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
38 FME-MB96380 rev 10
0003F7HMemory Timing Configuration Register B High MTCRBH - R/W
0003F8HFlash Memory Write Control register 0 FMWC0 - R/W
0003F9HFlash Memory Write Control register 1 FMWC1 - R/W
0003FAHFlash Memory Write Control register 2 FMWC2 - R/W
0003FBHFlash Memory Write Control register 3 FMWC3 - R/W
0003FCHFlash Memory Write Control register 4 FMWC4 - R/W
0003FDHFlash Memory Write Control register 5 FMWC5 - R/W
0003FEH-
0003FFHReserved - - -
000400HStandby Mode control register SMCR - R/W
000401HClock select register CKSR - R/W
000402HClock Stabilization select register CKSSR - R/W
000403HClock monitor register CKMR - R
000404HClock Frequency control register Low CKFCRL CKFCR R/W
000405HClock Frequency control register High CKFCRH - R/W
000406HPLL Control register Low PLLCRL PLLCR R/W
000407HPLL Control register High PLLCRH - R/W
000408HRC clock timer control register RCTCR - R/W
000409HMain clock timer control register MCTCR - R/W
00040AHSub clock timer control register SCTCR - R/W
00040BHReset cause and clock status register with clear
function RCCSRC - R
00040CHReset configuration register RCR - R/W
00040DHReset cause and clock status register RCCSR - R
00040EHWatch dog timer configuration register WDTC - R/W
00040FHWatch dog timer clear pattern register WDTCP - W
000410H-
000414HReserved - - -
000415HClock output activation register COAR - R/W
000416HClock output configuration register 0 COCR0 - R/W
000417HClock output configuration register 1 COCR1 - R/W
I/O map MB96(F)38x (13 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 39
000418HClock Modulator control register CMCR - R/W
000419HReserved - - -
00041AHClock Modulator Parameter register Low CMPRL CMPR R/W
00041BHClock Modulator Parameter register High CMPRH - R/W
00041CH-
00042BHReserved - - -
00042CHVoltage Regulator Control register VRCR - R/W
00042DHClock Input and LVD Control Register CILCR - R/W
00042EH-
00042FHReserved - - -
000430HI/O Port P00 - Data Direction Register DDR00 - R/W
000431HI/O Port P01 - Data Direction Register DDR01 - R/W
000432HI/O Port P02 - Data Direction Register DDR02 - R/W
000433HI/O Port P03 - Data Direction Register DDR03 - R/W
000434HI/O Port P04 - Data Direction Register DDR04 - R/W
000435HI/O Port P05 - Data Direction Register DDR05 - R/W
000436HI/O Port P06 - Data Direction Register DDR06 - R/W
000437HReserved - - -
000438HI/O Port P08 - Data Direction Register DDR08 - R/W
000439HI/O Port P09 - Data Direction Register DDR09 - R/W
00043AHI/O Port P10 - Data Direction Register DDR10 - R/W
00043BHI/O Port P11 - Data Direction Register DDR11 - R/W
00043CHI/O Port P12 - Data Direction Register DDR12 - R/W
00043DHI/O Port P13 - Data Direction Register DDR13 - R/W
00043EH-
000443HReserved - - -
000444HI/O Port P00 - Port Input Enable Register PIER00 - R/W
000445HI/O Port P01 - Port Input Enable Register PIER01 - R/W
000446HI/O Port P02 - Port Input Enable Register PIER02 - R/W
000447HI/O Port P03 - Port Input Enable Register PIER03 - R/W
000448HI/O Port P04 - Port Input Enable Register PIER04 - R/W
I/O map MB96(F)38x (14 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
40 FME-MB96380 rev 10
000449HI/O Port P05 - Port Input Enable Register PIER05 - R/W
00044AHI/O Port P06 - Port Input Enable Register PIER06 - R/W
00044BHReserved - - -
00044CHI/O Port P08 - Port Input Enable Register PIER08 - R/W
00044DHI/O Port P09 - Port Input Enable Register PIER09 - R/W
00044EHI/O Port P10 - Port Input Enable Register PIER10 - R/W
00044FHI/O Port P11 - Port Input Enable Register PIER11 - R/W
000450HI/O Port P12 - Port Input Enable Register PIER12 - R/W
000451HI/O Port P13 - Port Input Enable Register PIER13 - R/W
000452H-
000457HReserved - - -
000458HI/O Port P00 - Port Input Level Register PILR00 - R/W
000459HI/O Port P01 - Port Input Level Register PILR01 - R/W
00045AHI/O Port P02 - Port Input Level Register PILR02 - R/W
00045BHI/O Port P03 - Port Input Level Register PILR03 - R/W
00045CHI/O Port P04 - Port Input Level Register PILR04 - R/W
00045DHI/O Port P05 - Port Input Level Register PILR05 - R/W
00045EHI/O Port P06 - Port Input Level Register PILR06 - R/W
00045FHReserved - - -
000460HI/O Port P08 - Port Input Level Register PILR08 - R/W
000461HI/O Port P09 - Port Input Level Register PILR09 - R/W
000462HI/O Port P10 - Port Input Level Register PILR10 - R/W
000463HI/O Port P11 - Port Input Level Register PILR11 - R/W
000464HI/O Port P12 - Port Input Level Register PILR12 - R/W
000465HI/O Port P13 - Port Input Level Register PILR13 - R/W
000466H-
00046BHReserved - - -
00046CHI/O Port P00 - Extended Port Input Level Register EPILR00 - R/W
00046DHI/O Port P01 - Extended Port Input Level Register EPILR01 - R/W
00046EHI/O Port P02 - Extended Port Input Level Register EPILR02 - R/W
00046FHI/O Port P03 - Extended Port Input Level Register EPILR03 - R/W
I/O map MB96(F)38x (15 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 41
000470HI/O Port P04 - Extended Port Input Level Register EPILR04 - R/W
000471HI/O Port P05 - Extended Port Input Level Register EPILR05 - R/W
000472HI/O Port P06 - Extended Port Input Level Register EPILR06 - R/W
000473HReserved - - -
000474HI/O Port P08 - Extended Port Input Level Register EPILR08 - R/W
000475HI/O Port P09 - Extended Port Input Level Register EPILR09 - R/W
000476HI/O Port P10 - Extended Port Input Level Register EPILR10 - R/W
000477HI/O Port P11 - Extended Port Input Level Register EPILR11 - R/W
000478HI/O Port P12 - Extended Port Input Level Register EPILR12 - R/W
000479HI/O Port P13 - Extended Port Input Level Register EPILR13 - R/W
00047AH-
00047FHReserved - - -
000480HI/O Port P00 - Port Output Drive Register PODR00 - R/W
000481HI/O Port P01 - Port Output Drive Register PODR01 - R/W
000482HI/O Port P02 - Port Output Drive Register PODR02 - R/W
000483HI/O Port P03 - Port Output Drive Register PODR03 - R/W
000484HI/O Port P04 - Port Output Drive Register PODR04 - R/W
000485HI/O Port P05 - Port Output Drive Register PODR05 - R/W
000486HI/O Port P06 - Port Output Drive Register PODR06 - R/W
000487HReserved - - -
000488HI/O Port P08 - Port Output Drive Register PODR08 - R/W
000489HI/O Port P09 - Port Output Drive Register PODR09 - R/W
00048AHI/O Port P10 - Port Output Drive Register PODR10 - R/W
00048BHI/O Port P11 - Port Output Drive Register PODR11 - R/W
00048CHI/O Port P12 - Port Output Drive Register PODR12 - R/W
00048DHI/O Port P13 - Port Output Drive Register PODR13 - R/W
00048EH-
00049BHReserved - - -
00049CHI/O Port P08 - Port High Drive Register PHDR08 - R/W
00049DHI/O Port P09 - Port High Drive Register PHDR09 - R/W
00049EHI/O Port P10 - Port High Drive Register PHDR10 - R/W
I/O map MB96(F)38x (16 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
42 FME-MB96380 rev 10
00049FH-
0004A7HReserved - - -
0004A8HI/O Port P00 - Pull-Up resistor Control Register PUCR00 - R/W
0004A9HI/O Port P01 - Pull-Up resistor Control Register PUCR01 - R/W
0004AAHI/O Port P02 - Pull-Up resistor Control Register PUCR02 - R/W
0004ABHI/O Port P03 - Pull-Up resistor Control Register PUCR03 - R/W
0004ACHI/O Port P04 - Pull-Up resistor Control Register PUCR04 - R/W
0004ADHI/O Port P05 - Pull-Up resistor Control Register PUCR05 - R/W
0004AEHI/O Port P06 - Pull-Up resistor Control Register PUCR06 - R/W
0004AFHReserved - - -
0004B0HI/O Port P08 - Pull-Up resistor Control Register PUCR08 - R/W
0004B1HI/O Port P09 - Pull-Up resistor Control Register PUCR09 - R/W
0004B2HI/O Port P10 - Pull-Up resistor Control Register PUCR10 - R/W
0004B3HI/O Port P11 - Pull-Up resistor Control Register PUCR11 - R/W
0004B4HI/O Port P12 - Pull-Up resistor Control Register PUCR12 - R/W
0004B5HI/O Port P13 - Pull-Up resistor Control Register PUCR13 - R/W
0004B6H-
0004BBHReserved - - -
0004BCHI/O Port P00 - External Pin State Register EPSR00 - R
0004BDHI/O Port P01 - External Pin State Register EPSR01 - R
0004BEHI/O Port P02 - External Pin State Register EPSR02 - R
0004BFHI/O Port P03 - External Pin State Register EPSR03 - R
0004C0HI/O Port P04 - External Pin State Register EPSR04 - R
0004C1HI/O Port P05 - External Pin State Register EPSR05 - R
0004C2HI/O Port P06 - External Pin State Register EPSR06 - R
0004C3HReserved - - -
0004C4HI/O Port P08 - External Pin State Register EPSR08 - R
0004C5HI/O Port P09 - External Pin State Register EPSR09 - R
0004C6HI/O Port P10 - External Pin State Register EPSR10 - R
0004C7HI/O Port P11 - External Pin State Register EPSR11 - R
0004C8HI/O Port P12 - External Pin State Register EPSR12 - R
I/O map MB96(F)38x (17 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 43
0004C9HI/O Port P13 - External Pin State Register EPSR13 - R
0004CAH-
0004CFHReserved - - -
0004D0HADC analog input enable register 0 ADER0 - R/W
0004D1HADC analog input enable register 1 ADER1 - R/W
0004D2HADC analog input enable register 2 ADER2 - R/W
0004D3HADC analog input enable register 3 ADER3 - R/W
0004D4HADC analog input enable register 4 ADER4 - R/W
0004D5HReserved - - -
0004D6HPeripheral Resource Relocation Register 0 PRRR0 - R/W
0004D7HPeripheral Resource Relocation Register 1 PRRR1 - R/W
0004D8HPeripheral Resource Relocation Register 2 PRRR2 - R/W
0004D9HPeripheral Resource Relocation Register 3 PRRR3 - R/W
0004DAHPeripheral Resource Relocation Register 4 PRRR4 - R/W
0004DBHPeripheral Resource Relocation Register 5 PRRR5 - R/W
0004DCHPeripheral Resource Relocation Register 6 PRRR6 - R/W
0004DDHPeripheral Resource Relocation Register 7 PRRR7 - R/W
0004DEHPeripheral Resource Relocation Register 8 PRRR8 - R/W
0004DFHPeripheral Resource Relocation Register 9 PRRR9 - R/W
0004E0HRTC - Sub Second Register L WTBRL0 WTBR0 R/W
0004E1HRTC - Sub Second Register M WTBRH0 - R/W
0004E2HRTC - Sub-Second Register H WTBR1 - R/W
0004E3HRTC - Second Register WTSR - R/W
0004E4HRTC - Minutes WTMR - R/W
0004E5HRTC - Hour WTHR - R/W
0004E6HRTC - Timer Control Extended Register WTCER - R/W
0004E7HRTC - Clock select register WTCKSR - R/W
0004E8HRTC - Timer Control Register Low WTCRL WTCR R/W
0004E9HRTC - Timer Control Register High WTCRH - R/W
0004EAHCAL - Calibration unit Control register CUCR - R/W
I/O map MB96(F)38x (18 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
44 FME-MB96380 rev 10
0004EBHReserved - - -
0004ECHCAL - Duration Timer Data Register Low CUTDL CUTD R/W
0004EDHCAL - Duration Timer Data Register High CUTDH - R/W
0004EEHCAL - Calibration Timer Register 2 Low CUTR2L CUTR2 R
0004EFHCAL - Calibration Timer Register 2 High CUTR2H - R
0004F0HCAL - Calibration Timer Register 1 Low CUTR1L CUTR1 R
0004F1HCAL - Calibration Timer Register 1 High CUTR1H - R
0004F2H-
0004F9HReserved - - -
0004FAHRLT - Timer input select (for Cascading) TMISR - R/W
0004FBH-
00051FHReserved - - -
000520HUSART4 - Serial Mode Register SMR4 - R/W
000521HUSART4 - Serial Control Register SCR4 - R/W
000522HUSART4 - TX Register TDR4 - W
000522HUSART4 - RX Register RDR4 - R
000523HUSART4 - Serial Status SSR4 - R/W
000524HUSART4 - Control/Com. Register (internal) ECCR4 - R/W
000525HUSART4 - Ext. Status Register ESCR4 - R/W
000526HUSART4 - Baud Rate Generator Register Low BGRL4 BGR4 R/W
000527HUSART4 - Baud Rate Generator Register High BGRH4 - R/W
000528HUSART4 - Extended Serial Interrupt Register ESIR4 - R/W
000529HReserved - - -
00052AHUSART5 - Serial Mode Register SMR5 - R/W
00052BHUSART5 - Serial Control Register SCR5 - R/W
00052CHUSART5 - RX Register TDR5 - W
00052CHUSART5 - TX Register RDR5 - R
00052DHUSART5 - Serial Status SSR5 - R/W
00052EHUSART5 - Control/Com. Register ECCR5 - R/W
00052FHUSART5 - Ext. Status Register ESCR5 - R/W
000530HUSART5 - Baud Rate Generator Register Low BGRL5 BGR5 R/W
I/O map MB96(F)38x (19 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 45
000531HUSART5 - Baud Rate Generator Register High BGRH5 - R/W
000532HUSART5 - Extended Serial Interrupt Register ESIR5 - R/W
000533H-
00055FHReserved - - -
000560HALARM0 - Control Status Register ACSR0 - R/W
000561HALARM0 - Extended Control Status Register AECSR0 - R/W
000562HALARM1 - Control Status Register ACSR1 - R/W
000563HALARM1 - Extended Control Status Register AECSR1 - R/W
000564HPPG6 - Timer register - PTMR6 R
000565HPPG6 - Timer register - - R
000566HPPG6 - Period setting register - PCSR6 W
000567HPPG6 - Period setting register - - W
000568HPPG6 - Duty cycle register - PDUT6 W
000569HPPG6 - Duty cycle register - - W
00056AHPPG6 - Control status register Low PCNL6 PCN6 R/W
00056BHPPG6 - Control status register High PCNH6 - R/W
00056CHPPG7 - Timer register - PTMR7 R
00056DHPPG7 - Timer register - - R
00056EHPPG7 - Period setting register - PCSR7 W
00056FHPPG7 - Period setting register - W
000570HPPG7 - Duty cycle register - PDUT7 W
000571HPPG7 - Duty cycle register - - W
000572HPPG7 - Control status register Low PCNL7 PCN7 R/W
000573HPPG7 - Control status register High PCNH7 - R/W
000574H-
0005DFHReserved - - -
0005E0HSMC0 - PWM control register PWC0 - R/W
0005E1HSMC0 - Extended control register (Output enable) PWEC0 - R/W
0005E2HSMC0 - PWM compare register PWM 1 - PWC10 R/W
0005E3HSMC0 - PWM compare register PWM 1 - - R/W
0005E4HSMC0 - PWM compare register PWM 2 - PWC20 R/W
I/O map MB96(F)38x (20 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
46 FME-MB96380 rev 10
0005E5HSMC0 - PWM compare register PWM 2 - - R/W
0005E6HSMC0 - PWM Select register PWS10 - R/W
0005E7HSMC0 - PWM Select register PWS20 - R/W
0005E8H-
0005E9HReserved - - -
0005EAHSMC1 - PWM control register PWC1 - R/W
0005EBHSMC1 - Extended control register (Output enable) PWEC1 - R/W
0005ECHSMC1 - PWM compare register PWM 1 - PWC11 R/W
0005EDHSMC1 - PWM compare register PWM 1 - - R/W
0005EEHSMC1 - PWM compare register PWM 2 - PWC21 R/W
0005EFHSMC1 - PWM compare register PWM 2 - - R/W
0005F0HSMC1 - PWM Select register PWS11 - R/W
0005F1HSMC1 - PWM Select register PWS21 - R/W
0005F2H-
0005F3HReserved - - -
0005F4HSMC2 - PWM control register PWC2 - R/W
0005F5HSMC2 - Extended control register (Output enable) PWEC2 - R/W
0005F6HSMC2 - PWM compare register PWM 1 - PWC12 R/W
0005F7HSMC2 - PWM compare register PWM 1 - - R/W
0005F8HSMC2 - PWM compare register PWM 2 - PWC22 R/W
0005F9HSMC2 - PWM compare register PWM 2 - - R/W
0005FAHSMC2 - PWM Select register PWS12 - R/W
0005FBHSMC2 - PWM Select register PWS22 - R/W
0005FCH-
0005FDHReserved - - -
0005FEHSMC3 - PWM control register PWC3 - R/W
0005FFHSMC3 - Extended control register (Output enable) PWEC3 - R/W
000600HSMC3 - PWM compare register PWM 1 - PWC13 R/W
000601HSMC3 - PWM compare register PWM 1 - - R/W
000602HSMC3 - PWM compare register PWM 2 - PWC23 R/W
000603HSMC3 - PWM compare register PWM 2 - - R/W
I/O map MB96(F)38x (21 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 47
000604HSMC3 - PWM Select register PWS13 - R/W
000605HSMC3 - PWM Select register PWS23 - R/W
000606H-
000607HReserved - - -
000608HSMC4 - PWM control register PWC4 - R/W
000609HSMC4 - Extended control register (Output enable) PWEC4 - R/W
00060AHSMC4 - PWM compare register PWM 1 - PWC14 R/W
00060BHSMC4 - PWM compare register PWM 1 - - R/W
00060CHSMC4 - PWM compare register PWM 2 - PWC24 R/W
00060DHSMC4 - PWM compare register PWM 2 - - R/W
00060EHSMC4 - PWM Select register PWS14 - R/W
00060FHSMC4 - PWM Select register PWS24 - R/W
000610H-
00061BHReserved - - -
00061CHLCD - Output Enable Register 0 (Seg 7-0) LCDER0 - R/W
00061DHLCD - Output Enable Register 1 (Seg 15-8) LCDER1 - R/W
00061EHLCD - Output Enable Register 2 (Seg 23-16) LCDER2 - R/W
00061FHLCD - Output Enable Register 3 (Seg 31-24) LCDER3 - R/W
000620HLCD - Output Enable Register 4 (Seg 39-32) LCDER4 - R/W
000621HLCD - Output Enable Register 5 (Seg 47-40) LCDER5 - R/W
000622HLCD - Output Enable Register 6 (Seg 55-48) LCDER6 - R/W
000623HLCD - Output Enable Register 7 (Seg 63-56) LCDER7 - R/W
000624HLCD - Output Enable Register 8 (Seg 71-64) LCDER8 - R/W
000625HReserved - - -
000626HLCD - Output Enable Register V (Vx) LCDVER - R/W
000627HLCD - Extended Control Register LECR - R/W
000628HLCD - Common pin switching register LCDCMR - R/W
000629HLCD - Control Register LCR - R/W
00062AHLCD - Data register for Segment 1-0 VRAM0 - R/W
00062BHLCD - Data register for Segment 3-2 VRAM1 - R/W
00062CHLCD - Data register for Segment 5-4 VRAM2 - R/W
I/O map MB96(F)38x (22 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
48 FME-MB96380 rev 10
00062DHLCD - Data register for Segment 7-6 VRAM3 - R/W
00062EHLCD - Data register for Segment 9-8 VRAM4 - R/W
00062FHLCD - Data register for Segment 11-10 VRAM5 - R/W
000630HLCD - Data register for Segment 13-12 VRAM6 - R/W
000631HLCD - Data register for Segment 15-14 VRAM7 - R/W
000632HLCD - Data register for Segment 17-16 VRAM8 - R/W
000633HLCD - Data register for Segment 19-18 VRAM9 - R/W
000634HLCD - Data register for Segment 21-20 VRAM10 - R/W
000635HLCD - Data register for Segment 23-22 VRAM11 - R/W
000636HLCD - Data register for Segment 25-24 VRAM12 - R/W
000637HLCD - Data register for Segment 27-26 VRAM13 - R/W
000638HLCD - Data register for Segment 29-28 VRAM14 - R/W
000639HLCD - Data register for Segment 31-30 VRAM15 - R/W
00063AHLCD - Data register for Segment 33-32 VRAM16 - R/W
00063BHLCD - Data register for Segment 35-34 VRAM17 - R/W
00063CHLCD - Data register for Segment 37-36 VRAM18 - R/W
00063DHLCD - Data register for Segment 39-38 VRAM19 - R/W
00063EHLCD - Data register for Segment 41-40 VRAM20 - R/W
00063FHLCD - Data register for Segment 43-42 VRAM21 - R/W
000640HLCD - Data register for Segment 45-44 VRAM22 - R/W
000641HLCD - Data register for Segment 47-46 VRAM23 - R/W
000642HLCD - Data register for Segment 49-48 VRAM24 - R/W
000643HLCD - Data register for Segment 51-50 VRAM25 - R/W
000644HLCD - Data register for Segment 53-52 VRAM26 - R/W
000645HLCD - Data register for Segment 55-54 VRAM27 - R/W
000646HLCD - Data register for Segment 57-56 VRAM28 - R/W
000647HLCD - Data register for Segment 59-58 VRAM29 - R/W
000648HLCD - Data register for Segment 61-60 VRAM30 - R/W
000649HLCD - Data register for Segment 63-62 VRAM31 - R/W
00064AHLCD - Data register for Segment 65-64 VRAM32 - R/W
I/O map MB96(F)38x (23 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 49
00064BH-
00065FHReserved - - -
000660HPeripheral Resource Relocation Register 10 PRRR10 - R/W
000661HPeripheral Resource Relocation Register 11 PRRR11 - R/W
000662HPeripheral Resource Relocation Register 12 PRRR12 - R/W
000663HPeripheral Resource Relocation Register 13 PRRR13 - W
000664H-
0006DFHReserved - - -
0006E0HExternal Bus - Area configuration register 0 Low EACL0 EAC0 R/W
0006E1HExternal Bus - Area configuration register 0 High EACH0 - R/W
0006E2HExternal Bus - Area configuration register 1 Low EACL1 EAC1 R/W
0006E3HExternal Bus - Area configuration register 1 High EACH1 - R/W
0006E4HExternal Bus - Area configuration register 2 Low EACL2 EAC2 R/W
0006E5HExternal Bus - Area configuration register 2 High EACH2 - R/W
0006E6HExternal Bus - Area configuration register 3 Low EACL3 EAC3 R/W
0006E7HExternal Bus - Area configuration register 3 High EACH3 - R/W
0006E8HExternal Bus - Area configuration register 4 Low EACL4 EAC4 R/W
0006E9HExternal Bus - Area configuration register 4 High EACH4 - R/W
0006EAHExternal Bus - Area configuration register 5 Low EACL5 EAC5 R/W
0006EBHExternal Bus - Area configuration register 5 High EACH5 - R/W
0006ECHExternal Bus - Area select register 2 EAS2 - R/W
0006EDHExternal Bus - Area select register 3 EAS3 - R/W
0006EEHExternal Bus - Area select register 4 EAS4 - R/W
0006EFHExternal Bus - Area select register 5 EAS5 - R/W
0006F0HExternal Bus - Mode register EBM - R/W
0006F1HExternal Bus - Clock and Function register EBCF - R/W
0006F2HExternal Bus - Address output enable register 0 EBAE0 - R/W
0006F3HExternal Bus - Address output enable register 1 EBAE1 - R/W
0006F4HExternal Bus - Address output enable register 2 EBAE2 - R/W
0006F5HExternal Bus - Control signal register EBCS - R/W
I/O map MB96(F)38x (24 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
50 FME-MB96380 rev 10
0006F6H-
0006FFHReserved - - -
000700HCAN0 - Control register Low CTRLRL0 CTRLR0 R/W
000701HCAN0 - Control register High (reserved) CTRLRH0 - R
000702HCAN0 - Status register Low STATRL0 STATR0 R/W
000703HCAN0 - Status register High (reserved) STATRH0 - R
000704HCAN0 - Error Counter Low (Transmit) ERRCNTL0 ERRCNT0 R
000705HCAN0 - Error Counter High (Receive) ERRCNTH0 - R
000706HCAN0 - Bit Timing Register Low BTRL0 BTR0 R/W
000707HCAN0 - Bit Timing Register High BTRH0 - R/W
000708HCAN0 - Interrupt Register Low INTRL0 INTR0 R
000709HCAN0 - Interrupt Register High INTRH0 - R
00070AHCAN0 - Test Register Low TESTRL0 TESTR0 R/W
00070BHCAN0 - Test Register High (reserved) TESTRH0 - R
00070CHCAN0 - BRP Extension register Low BRPERL0 BRPER0 R/W
00070DHCAN0 - BRP Extension register High (reserved) BRPERH0 - R
00070EH-
00070FHReserved - - -
000710HCAN0 - IF1 Command request register Low IF1CREQL0 IF1CREQ0 R/W
000711HCAN0 - IF1 Command request register High IF1CREQH0 - R/W
000712HCAN0 - IF1 Command Mask register Low IF1CMSKL0 IF1CMSK0 R/W
000713HCAN0 - IF1 Command Mask register High
(reserved) IF1CMSKH0 - R
000714HCAN0 - IF1 Mask 1 Register Low IF1MSK1L0 IF1MSK10 R/W
000715HCAN0 - IF1 Mask 1 Register High IF1MSK1H0 - R/W
000716HCAN0 - IF1 Mask 2 Register Low IF1MSK2L0 IF1MSK20 R/W
000717HCAN0 - IF1 Mask 2 Register High IF1MSK2H0 - R/W
000718HCAN0 - IF1 Arbitration 1 Register Low IF1ARB1L0 IF1ARB10 R/W
000719HCAN0 - IF1 Arbitration 1 Register High IF1ARB1H0 - R/W
00071AHCAN0 - IF1 Arbitration 2 Register Low IF1ARB2L0 IF1ARB20 R/W
00071BHCAN0 - IF1 Arbitration 2 Register High IF1ARB2H0 - R/W
I/O map MB96(F)38x (25 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 51
00071CHCAN0 - IF1 Message Control Register Low IF1MCTRL0 IF1MCTR0 R/W
00071DHCAN0 - IF1 Message Control Register High IF1MCTRH0 - R/W
00071EHCAN0 - IF1 Data A1 Low IF1DTA1L0 IF1DTA10 R/W
00071FHCAN0 - IF1 Data A1 High IF1DTA1H0 - R/W
000720HCAN0 - IF1 Data A2 Low IF1DTA2L0 IF1DTA20 R/W
000721HCAN0 - IF1 Data A2 High IF1DTA2H0 - R/W
000722HCAN0 - IF1 Data B1 Low IF1DTB1L0 IF1DTB10 R/W
000723HCAN0 - IF1 Data B1 High IF1DTB1H0 - R/W
000724HCAN0 - IF1 Data B2 Low IF1DTB2L0 IF1DTB20 R/W
000725HCAN0 - IF1 Data B2 High IF1DTB2H0 - R/W
000726H-
00073FHReserved - - -
000740HCAN0 - IF2 Command request register Low IF2CREQL0 IF2CREQ0 R/W
000741HCAN0 - IF2 Command request register High IF2CREQH0 - R/W
000742HCAN0 - IF2 Command Mask register Low IF2CMSKL0 IF2CMSK0 R/W
000743HCAN0 - IF2 Command Mask register High
(reserved) IF2CMSKH0 - R
000744HCAN0 - IF2 Mask 1 Register Low IF2MSK1L0 IF2MSK10 R/W
000745HCAN0 - IF2 Mask 1 Register High IF2MSK1H0 - R/W
000746HCAN0 - IF2 Mask 2 Register Low IF2MSK2L0 IF2MSK20 R/W
000747HCAN0 - IF2 Mask 2 Register High IF2MSK2H0 - R/W
000748HCAN0 - IF2 Arbitration 1 Register Low IF2ARB1L0 IF2ARB10 R/W
000749HCAN0 - IF2 Arbitration 1 Register High IF2ARB1H0 - R/W
00074AHCAN0 - IF2 Arbitration 2 Register Low IF2ARB2L0 IF2ARB20 R/W
00074BHCAN0 - IF2 Arbitration 2 Register High IF2ARB2H0 - R/W
00074CHCAN0 - IF2 Message Control Register Low IF2MCTRL0 IF2MCTR0 R/W
00074DHCAN0 - IF2 Message Control Register High IF2MCTRH0 - R/W
00074EHCAN0 - IF2 Data A1 Low IF2DTA1L0 IF2DTA10 R/W
00074FHCAN0 - IF2 Data A1 High IF2DTA1H0 - R/W
000750HCAN0 - IF2 Data A2 Low IF2DTA2L0 IF2DTA20 R/W
000751HCAN0 - IF2 Data A2 High IF2DTA2H0 - R/W
I/O map MB96(F)38x (26 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
52 FME-MB96380 rev 10
000752HCAN0 - IF2 Data B1 Low IF2DTB1L0 IF2DTB10 R/W
000753HCAN0 - IF2 Data B1 High IF2DTB1H0 - R/W
000754HCAN0 - IF2 Data B2 Low IF2DTB2L0 IF2DTB20 R/W
000755HCAN0 - IF2 Data B2 High IF2DTB2H0 - R/W
000756H-
00077FHReserved - - -
000780HCAN0 - Transmission Request 1 Register Low TREQR1L0 TREQR10 R
000781HCAN0 - Transmission Request 1 Register High TREQR1H0 - R
000782HCAN0 - Transmission Request 2 Register Low TREQR2L0 TREQR20 R
000783HCAN0 - Transmission Request 2 Register High TREQR2H0 - R
000784H-
00078FHReserved - - -
000790HCAN0 - New Data 1 Register Low NEWDT1L0 NEWDT10 R
000791HCAN0 - New Data 1 Register High NEWDT1H0 - R
000792HCAN0 - New Data 2 Register Low NEWDT2L0 NEWDT20 R
000793HCAN0 - New Data 2 Register High NEWDT2H0 - R
000794H-
00079FHReserved - - -
0007A0HCAN0 - Interrupt Pending 1 Register Low INTPND1L0 INTPND10 R
0007A1HCAN0 - Interrupt Pending 1 Register High INTPND1H0 - R
0007A2HCAN0 - Interrupt Pending 2 Register Low INTPND2L0 INTPND20 R
0007A3HCAN0 - Interrupt Pending 2 Register High INTPND2H0 - R
0007A4H-
0007AFHReserved - - -
0007B0HCAN0 - Message Valid 1 Register Low MSGVAL1L0 MSGVAL10 R
0007B1HCAN0 - Message Valid 1 Register High MSGVAL1H0 - R
0007B2HCAN0 - Message Valid 2 Register Low MSGVAL2L0 MSGVAL20 R
0007B3HCAN0 - Message Valid 2 Register High MSGVAL2H0 - R
0007B4H-
0007CDHReserved - - -
0007CEHCAN0 - Output enable register COER0 - R/W
0007CFHReserved - - -
I/O map MB96(F)38x (27 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 53
0007D0HSG0 - Sound Generator Control Register Low SGCRL0 SGCR0 R/W
0007D1HSG0 - Sound Generator Control Register High SGCRH0 - R/W
0007D2HSG0 - Sound Generator Frequency Register SGFR0 - R/W
0007D3HSG0 - Sound Generator Amplitude Register SGAR0 - R/W
0007D4HSG0 - Sound Generator Decrement Register SGDR0 - R/W
0007D5HSG0 - Sound Generator Tone Register SGTR0 - R/W
0007D6HSG1 - Sound Generator Control Register Low SGCRL1 SGCR1 R/W
0007D7HSG1 - Sound Generator Control Register High SGCRH1 - R/W
0007D8HSG1 - Sound Generator Frequency Register SGFR1 - R/W
0007D9HSG1 - Sound Generator Amplitude Register SGAR1 - R/W
0007DAHSG1 - Sound Generator Decrement Register SGDR1 - R/W
0007DBHSG1 - Sound Generator Tone Register SGTR1 - R/W
0007DCH-
0007FFHReserved - - -
000800HCAN1 - Control register Low CTRLRL1 CTRLR1 R/W
000801HCAN1 - Control register High (reserved) CTRLRH1 - R
000802HCAN1 - Status register Low STATRL1 STATR1 R/W
000803HCAN1 - Status register High (reserved) STATRH1 - R
000804HCAN1 - Error Counter Low (Transmit) ERRCNTL1 ERRCNT1 R
000805HCAN1 - Error Counter High (Receive) ERRCNTH1 - R
000806HCAN1 - Bit Timing Register Low BTRL1 BTR1 R/W
000807HCAN1 - Bit Timing Register High BTRH1 - R/W
000808HCAN1 - Interrupt Register Low INTRL1 INTR1 R
000809HCAN1 - Interrupt Register High INTRH1 - R
00080AHCAN1 - Test Register Low TESTRL1 TESTR1 R/W
00080BHCAN1 - Test Register High (reserved) TESTRH1 - R
00080CHCAN1 - BRP Extension register Low BRPERL1 BRPER1 R/W
00080DHCAN1 - BRP Extension register High (reserved) BRPERH1 - R
00080EH-
00080FHReserved - - -
000810HCAN1 - IF1 Command request register Low IF1CREQL1 IF1CREQ1 R/W
I/O map MB96(F)38x (28 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
54 FME-MB96380 rev 10
000811HCAN1 - IF1 Command request register High IF1CREQH1 - R/W
000812HCAN1 - IF1 Command Mask register Low IF1CMSKL1 IF1CMSK1 R/W
000813HCAN1 - IF1 Command Mask register High
(reserved) IF1CMSKH1 - R
000814HCAN1 - IF1 Mask 1 Register Low IF1MSK1L1 IF1MSK11 R/W
000815HCAN1 - IF1 Mask 1 Register High IF1MSK1H1 - R/W
000816HCAN1 - IF1 Mask 2 Register Low IF1MSK2L1 IF1MSK21 R/W
000817HCAN1 - IF1 Mask 2 Register High IF1MSK2H1 - R/W
000818HCAN1 - IF1 Arbitration 1 Register Low IF1ARB1L1 IF1ARB11 R/W
000819HCAN1 - IF1 Arbitration 1 Register High IF1ARB1H1 - R/W
00081AHCAN1 - IF1 Arbitration 2 Register Low IF1ARB2L1 IF1ARB21 R/W
00081BHCAN1 - IF1 Arbitration 2 Register High IF1ARB2H1 - R/W
00081CHCAN1 - IF1 Message Control Register Low IF1MCTRL1 IF1MCTR1 R/W
00081DHCAN1 - IF1 Message Control Register High IF1MCTRH1 - R/W
00081EHCAN1 - IF1 Data A1 Low IF1DTA1L1 IF1DTA11 R/W
00081FHCAN1 - IF1 Data A1 High IF1DTA1H1 - R/W
000820HCAN1 - IF1 Data A2 Low IF1DTA2L1 IF1DTA21 R/W
000821HCAN1 - IF1 Data A2 High IF1DTA2H1 - R/W
000822HCAN1 - IF1 Data B1 Low IF1DTB1L1 IF1DTB11 R/W
000823HCAN1 - IF1 Data B1 High IF1DTB1H1 - R/W
000824HCAN1 - IF1 Data B2 Low IF1DTB2L1 IF1DTB21 R/W
000825HCAN1 - IF1 Data B2 High IF1DTB2H1 - R/W
000826H-
00083FHReserved - - -
000840HCAN1 - IF2 Command request register Low IF2CREQL1 IF2CREQ1 R/W
000841HCAN1 - IF2 Command request register High IF2CREQH1 - R/W
000842HCAN1 - IF2 Command Mask register Low IF2CMSKL1 IF2CMSK1 R/W
000843HCAN1 - IF2 Command Mask register High
(reserved) IF2CMSKH1 - R
000844HCAN1 - IF2 Mask 1 Register Low IF2MSK1L1 IF2MSK11 R/W
000845HCAN1 - IF2 Mask 1 Register High IF2MSK1H1 - R/W
I/O map MB96(F)38x (29 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 55
000846HCAN1 - IF2 Mask 2 Register Low IF2MSK2L1 IF2MSK21 R/W
000847HCAN1 - IF2 Mask 2 Register High IF2MSK2H1 - R/W
000848HCAN1 - IF2 Arbitration 1 Register Low IF2ARB1L1 IF2ARB11 R/W
000849HCAN1 - IF2 Arbitration 1 Register High IF2ARB1H1 - R/W
00084AHCAN1 - IF2 Arbitration 2 Register Low IF2ARB2L1 IF2ARB21 R/W
00084BHCAN1 - IF2 Arbitration 2 Register High IF2ARB2H1 - R/W
00084CHCAN1 - IF2 Message Control Register Low IF2MCTRL1 IF2MCTR1 R/W
00084DHCAN1 - IF2 Message Control Register High IF2MCTRH1 - R/W
00084EHCAN1 - IF2 Data A1 Low IF2DTA1L1 IF2DTA11 R/W
00084FHCAN1 - IF2 Data A1 High IF2DTA1H1 - R/W
000850HCAN1 - IF2 Data A2 Low IF2DTA2L1 IF2DTA21 R/W
000851HCAN1 - IF2 Data A2 High IF2DTA2H1 - R/W
000852HCAN1 - IF2 Data B1 Low IF2DTB1L1 IF2DTB11 R/W
000853HCAN1 - IF2 Data B1 High IF2DTB1H1 - R/W
000854HCAN1 - IF2 Data B2 Low IF2DTB2L1 IF2DTB21 R/W
000855HCAN1 - IF2 Data B2 High IF2DTB2H1 - R/W
000856H-
00087FHReserved - - -
000880HCAN1 - Transmission Request 1 Register Low TREQR1L1 TREQR11 R
000881HCAN1 - Transmission Request 1 Register High TREQR1H1 - R
000882HCAN1 - Transmission Request 2 Register Low TREQR2L1 TREQR21 R
000883HCAN1 - Transmission Request 2 Register High TREQR2H1 - R
000884H-
00088FHReserved - - -
000890HCAN1 - New Data 1 Register Low NEWDT1L1 NEWDT11 R
000891HCAN1 - New Data 1 Register High NEWDT1H1 - R
000892HCAN1 - New Data 2 Register Low NEWDT2L1 NEWDT21 R
000893HCAN1 - New Data 2 Register High NEWDT2H1 - R
000894H-
00089FHReserved - - -
0008A0HCAN1 - Interrupt Pending 1 Register Low INTPND1L1 INTPND11 R
I/O map MB96(F)38x (30 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
56 FME-MB96380 rev 10
Note: Anywriteaccesstoreservedaddresses intheI/Omapshouldnotbeperformed.A readaccesstoareserved
address results in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
0008A1HCAN1 - Interrupt Pending 1 Register High INTPND1H1 - R
0008A2HCAN1 - Interrupt Pending 2 Register Low INTPND2L1 INTPND21 R
0008A3HCAN1 - Interrupt Pending 2 Register High INTPND2H1 - R
0008A4H-
0008AFHReserved - - -
0008B0HCAN1 - Message Valid 1 Register Low MSGVAL1L1 MSGVAL11 R
0008B1HCAN1 - Message Valid 1 Register High MSGVAL1H1 - R
0008B2HCAN1 - Message Valid 2 Register Low MSGVAL2L1 MSGVAL21 R
0008B3HCAN1 - Message Valid 2 Register High MSGVAL2H1 - R
0008B4H-
0008CDHReserved - - -
0008CEHCAN1 - Output enable register COER1 - R/W
0008CFH-
000BFFHReserved - - -
I/O map MB96(F)38x (31 of 31)
Address Register Abbreviation
8-bit access Abbreviation
16-bit access Access
MB96380 Series
FME-MB96380 rev 10 57
■INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)38x (1 of 3)
Vector
number
Offset in
vector ta-
ble Vector name Clearedby
DMA
Index in
ICR to pro-
gram Description
0 3FCHCALLV0 No -
1 3F8HCALLV1 No -
2 3F4HCALLV2 No -
3 3F0HCALLV3 No -
4 3ECHCALLV4 No -
5 3E8HCALLV5 No -
6 3E4HCALLV6 No -
7 3E0HCALLV7 No -
8 3DCHRESET No -
9 3D8HINT9 No -
10 3D4HEXCEPTION No -
11 3D0HNMI No - Non-Maskable Interrupt
12 3CCHDLY No 12 Delayed Interrupt
13 3C8HRC_TIMER No 13 RC Timer
14 3C4HMC_TIMER No 14 Main Clock Timer
15 3C0HSC_TIMER No 15 Sub Clock Timer
16 3BCHRESERVED No 16 Reserved
17 3B8HEXTINT0 Yes 17 External Interrupt 0
18 3B4HEXTINT1 Yes 18 External Interrupt 1
19 3B0HEXTINT2 Yes 19 External Interrupt 2
20 3ACHEXTINT3 Yes 20 External Interrupt 3
21 3A8HEXTINT4 Yes 21 External Interrupt 4
22 3A4HEXTINT5 Yes 22 External Interrupt 5
23 3A0HEXTINT6 Yes 23 External Interrupt 6
24 39CHEXTINT7 Yes 24 External Interrupt 7
25 398HCAN0 No 25 CAN Controller 0
26 394HCAN1* No 26 CAN Controller 1
27 390HPPG0 Yes 27 Programmable Pulse Generator 0
28 38CHPPG1 Yes 28 Programmable Pulse Generator 1
29 388HPPG2 Yes 29 Programmable Pulse Generator 2
30 384HPPG3 Yes 30 Programmable Pulse Generator 3
31 380HPPG4 Yes 31 Programmable Pulse Generator 4
32 37CHPPG5 Yes 32 Programmable Pulse Generator 5
MB96380 Series
58 FME-MB96380 rev 10
33 378HPPG6 Yes 33 Programmable Pulse Generator 6
34 374HPPG7 Yes 34 Programmable Pulse Generator 7
35 370HRLT0 Yes 35 Reload Timer 0
36 36CHRLT1 Yes 36 Reload Timer 1
37 368HRLT2 Yes 37 Reload Timer 2
38 364HRLT3 Yes 38 Reload Timer 3
39 360HPPGRLT Yes 39 Reload Timer 6 - dedicated for PPG
40 35CHICU0 Yes 40 Input Capture Unit 0
41 358HICU1 Yes 41 Input Capture Unit 1
42 354HICU2 Yes 42 Input Capture Unit 2
43 350HICU3 Yes 43 Input Capture Unit 3
44 34CHICU4 Yes 44 Input Capture Unit 4
45 348HICU5 Yes 45 Input Capture Unit 5
46 344HICU6 Yes 46 Input Capture Unit 6
47 340HICU7 Yes 47 Input Capture Unit 7
48 33CHOCU0 Yes 48 Output Compare Unit 0
49 338HOCU1 Yes 49 Output Compare Unit 1
50 334HOCU2 Yes 50 Output Compare Unit 2
51 330HOCU3 Yes 51 Output Compare Unit 3
52 32CHFRT0 Yes 52 Free Running Timer 0
53 328HFRT1 Yes 53 Free Running Timer 1
54 324HRTC0 No 54 Real Timer Clock
55 320HCAL0 No 55 Clock Calibration Unit
56 31CHSG0 No 56 Sound Generator 0
57 318HSG1 No 57 Sound Generator 1
58 314HIIC0 Yes 58 I2C interface
59 310HADC0 Yes 59 A/D Converter
60 30CHALARM0 No 60 Alarm Comparator 0
61 308HALARM1* No 61 Alarm Comparator 1
62 304HLINR0 Yes 62 LIN USART 0 RX
63 300HLINT0 Yes 63 LIN USART 0 TX
64 2FCHLINR1 Yes 64 LIN USART 1 RX
65 2F8HLINT1 Yes 65 LIN USART 1 TX
66 2F4HLINR2 Yes 66 LIN USART 2 RX
67 2F0HLINT2 Yes 67 LIN USART 2 TX
Interrupt vector table MB96(F)38x (2 of 3)
Vector
number
Offset in
vector ta-
ble Vector name Clearedby
DMA
Index in
ICR to pro-
gram Description
MB96380 Series
FME-MB96380 rev 10 59
68 2ECHLINR4 Yes 68 LIN USART 4 RX
69 2E8HLINT4 Yes 69 LIN USART 4 TX
70 2E4HLINR5 Yes 70 LIN USART 5 RX
71 2E0HLINT5 Yes 71 LIN USART 5 TX
72 2DCHFLASH_A No 72 Flash memory A (only Flash devices)
73 2D8HFLASH_B No 73 Flash memory B (only MB96F388/F389)
*: ALARM1 and CAN1 are not included on MB96384 and MB96(F)385 devices
Interrupt vector table MB96(F)38x (3 of 3)
Vector
number
Offset in
vector ta-
ble Vector name Clearedby
DMA
Index in
ICR to pro-
gram Description
MB96380 Series
60 FME-MB96380 rev 10
■HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Unused sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on energization
• Stabilization of power supply voltage
• SMC power supply pins
• Serial communication
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC
Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
MB96380 Series
FME-MB96380 rev 10 61
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6. Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
thanoneVCC orVSS level,thedevicemayoperateincorrectlyorbedamagedevenwithintheguaranteedoperating
range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
NoiseatX0,X1pinsorX0A,X1Apinsmightcauseabnormaloperation.Itisrequiredtoprovidebypasscapacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
X0
X1
MB96380 Series
62 FME-MB96380 rev 10
11. Stabilization of power supply voltage
Ifthepowersupply voltagevariesacutelyevenwithin theoperationsafetyrangeofthe Vccpower supplyvoltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. SMC power supply pins
All DVSS pins must be set to the same level as the VSS pins.
The DVCC power supply level can be set independently of the VCC power supply level. However note that the
SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to
always power VCC before DVCC.
13. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
MB96380 Series
FME-MB96380 rev 10 63
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage VCC VSS - 0.3 VSS + 6.0 V
AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1
AD Converter voltage references AVRH,
AVRL VSS - 0.3 VSS + 6.0 V AVCC ≥AVRH, AVCC ≥AVRL,
AVRH > AVRL, AVRL ≥ AVSS
SMC Power supply DVCC VSS - 0.3 VSS + 6.0 V See *7
LCD power supply voltage V0 to V3 VSS - 0.3 VSS + 6.0 V V0 to V3 must not exceed VCC
Input voltage VIVSS - 0.3 VSS + 6.0 V VI≤(D)VCC + 0.3V *2
Output voltage VOVSS - 0.3 VSS + 6.0 V VO ≤ (D)VCC + 0.3V *2
Maximum Clamp Current ICLAMP -4.0 +4.0 mA Applicable to general purpose
I/O pins *3
Total Maximum Clamp Current Σ|ICLAMP| - 40 mA Applicable to general purpose
I/O pins *3
“L” level maximum output current IOL1 - 15 mA Normal outputs with driving
strength set to 5mA
IOLSMC - 40 mA High current outputs with driv-
ing strength set to 30mA
“L” level average output current IOLAV1 - 5 mA Normal outputs with driving
strength set to 5mA
IOLAVSMC - 30 mA High current outputs with driv-
ing strength set to 30mA
“L” level maximum overall output current ΣIOL1 - 100 mA Normal outputs
ΣIOLSMC - 330 mA High current outputs
“L” level average overall output current ΣIOLAV1 - 50 mA Normal outputs
ΣIOLAVSMC - 250 mA High current outputs
”H” level maximum output current IOH1 - -15 mA Normal outputs with driving
strength set to 5mA
IOHSMC - -40 mA High current outputs with driv-
ing strength set to 30mA
”H” level average output current IOHAV1 - -5 mA Normal outputs with driving
strength set to 5mA
IOHAVSMC - -30 mA High current outputs with driv-
ing strength set to 30mA
”H” level maximum overall output current ΣIOH1 - -100 mA Normal outputs
ΣIOHSMC - -330 mA High current outputs
”H” level average overall output current ΣIOHAV1 - -50 mA Normal outputs
ΣIOHASMC - -250 mA High current outputs
MB96380 Series
64 FME-MB96380 rev 10
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating super-
sedestheVIrating.Input/outputvoltagesofhighcurrentportsdependonDVCC.Input/outputvoltagesofstandard
ports depend on VCC.
*3: • Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality.
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
Permitted Power dissipation
(MB96F385) *4 PD
-295*5 mW TA=105oC
-595*5 mW TA=85oC
-820*5 mW TA=70oC
-370*5 mW TA=125oC, no Flash program/
erase *6
-670*5 mW TA=105oC, no Flash program/
erase *6
Permitted Power dissipation
(MB96F386/F387/F388/F389) *4 PD
-370*5 mW TA=105oC
-740*5 mW TA=85oC
-1000*5 mW TA=70oC
-460*5 mW TA=125oC, no Flash program/
erase *6
-800*5 mW TA=105oC, no Flash program/
erase *6
Permitted Power dissipation (MB96384/
385) *4 PD
-310*5 mW TA=105oC
-625*5 mW TA=85oC
-800*5 mW TA=70oC
-390*5 mW TA=125oC*6
-700*5 mW TA=105oC*6
Operating ambient temperature TA
0 +70
oC
MB96V300B
-40 +105
-40 +125 *6
Storage temperature TSTG -55 +150 oC
Parameter Symbol Rating Unit Remarks
Min Max
MB96380 Series
FME-MB96380 rev 10 65
supply is provided from the pins, so that incomplete operation may result.
•Notethatifthe+Binputisappliedduringpower-on,thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
• No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins).
• Sample recommended circuits:
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑(VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
*7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always
power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
Protective Diode
Limiting
resistance
+B input (0V to 16V)
MB96380 Series
66 FME-MB96380 rev 10
2. Recommended Operating Conditions
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC, DVCC 3.0 - 5.5 V
Smoothing capacitor at C
pin CS3.5 4.7 15 µFUseaX7Rceramiccapacitoror
a capacitor that has similar fre-
quency characteristics
MB96380 Series
FME-MB96380 rev 10 67
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Input H voltage
VIH Port inputs
Pnn_m
CMOSHysteresis
0.8/0.2 input se-
lected 0.8
VCC -(D)VCC
+ 0.3 V
CMOSHysteresis
0.7/0.3 input se-
lected
0.7
VCC -(D)VCC
+ 0.3 V (D)VCC ≥4.5V
0.74
VCC -(D)VCC
+ 0.3 V (D)VCC < 4.5V
AUTOMOTIVE
Hysteresis input
selected 0.8
VCC -(D)VCC
+ 0.3 V
TTL input select-
ed 2.0 - (D)VCC
+ 0.3 V
VIHX0F X0 External clock in
“Fast Clock Input
mode” 0.8
VCC -VCC +
0.3 VNot available in
MB96F386xxA/
F387xxA
VIHX0S X0,X1,
X0A,X1A External clock in
“oscillation mode” 2.5 - VCC +
0.3 V
VIHR RSTX - 0.8
VCC -VCC +
0.3 VCMOS Hysteresis in-
put
VIHM MD2-MD0 - VCC -
0.3 -VCC +
0.3 V
Input L voltage
VIL Port inputs
Pnn_m
CMOSHysteresis
0.8/0.2 input se-
lected VSS -
0.3 -0.2
(D)VCC V
CMOSHysteresis
0.7/0.3 input se-
lected VSS -
0.3 -0.3
(D)VCC V
AUTOMOTIVE
Hysteresis input
selected
VSS -
0.3 -0.5
(D)VCC V (D)VCC ≥4.5V
VSS -
0.3 -0.46
(D)VCC (D)VCC < 4.5V
TTL input select-
ed VSS -
0.3 - 0.8 V
VILX0F X0 External clock in
“Fast Clock Input
mode” VSS -
0.3 - 0.2 VCC VNot available in
MB96F386xxA/
F387xxA
VILX0S X0,X1,
X0A,X1A External clock in
“oscillation mode” VSS -
0.3 - 0.4 V
VILR RSTX - VSS -
0.3 - 0.2 VCC VCMOS Hysteresis in-
put
VILM MD2-MD0 - VSS -
0.3 -VSS +
0.3 V
MB96380 Series
68 FME-MB96380 rev 10
Output H voltage
VOH2
Normal
and High
Current
outputs
4.5V ≤(D)VCC ≤
5.5V
IOH = -2mA (D)VCC
- 0.5 --
VDriving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
3.0V ≤(D)VCC <
4.5V
IOH = -1.6mA
VOH5
Normal
and High
Current
outputs
4.5V ≤(D)VCC ≤
5.5V
IOH = -5mA (D)VCC
- 0.5 --
VDriving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
3.0V ≤(D)VCC <
4.5V
IOH = -3mA
VOH30 High cur-
rent out-
puts
4.5V ≤DVCC ≤ 5.5V
IOH = -30mA DVCC -
0.5 --
VDriving strength set
to 30mA
(PHDR:HD=1)
3.0V ≤DVCC < 4.5V
IOH = -20mA
VOH3 3mA out-
puts
4.5V ≤VCC ≤ 5.5V
IOH = -3mA VCC -
0.5 --
V I/O circuit type “N”
3.0V ≤VCC < 4.5V
IOH = -2mA
Output L voltage
VOL2
Normal
and High
Current
outputs
4.5V ≤(D)VCC ≤
5.5V
IOL = +2mA - - 0.4 VDriving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
3.0V ≤(D)VCC <
4.5V
IOL = +1.6mA
VOL5
Normal
and High
Current
outputs
4.5V ≤(D)VCC ≤
5.5V
IOL = +5mA - - 0.4 VDriving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
3.0V ≤(D)VCC <
4.5V
IOL = +3mA
VOL30 High cur-
rent out-
puts
4.5V ≤DVCC ≤ 5.5V
IOL = +30mA - - 0.5 VDriving strength set
to 30mA
(PHDR:HD=1)
3.0V ≤DVCC < 4.5V
IOL = +20mA
VOL3 3mA out-
puts 3.0V ≤VCC ≤ 5.5V
IOL = +3mA - - 0.4 V I/O circuit type “N”
Input leak current IIL Pnn_m VSS < VI < VCC
AVSS,AVRL<VI<
AVCC, AVRH -1 - +1 µA Single port pin
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
MB96380 Series
FME-MB96380 rev 10 69
Total LCD leak
current Σ|IILCD|all SEG/
COM pins VCC = 5.0V - 0.5 10 µAMaximum leakage
current of all LCD
pins
Internal LCD di-
vide resistance RLCD Between
V3 and VSS VCC = 5.0V 25 40 65 kΩ
Pull-up resistance RUP Pnn_m,
RSTX VCC = 3.3V ± 10%40 100 160 kΩ
VCC = 5.0V ± 10%25 50 100 kΩ
Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
MB96380 Series
70 FME-MB96380 rev 10
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
Power supply cur-
rent in Run
modes* ICCPLL
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
1 Flash/ROM wait state
(CLKRC and CLKSC
stopped)
+25˚C 8 11 mA MB96384/385
+125˚C 8.5 13
+25˚C 15 20 mA MB96F385
+125˚C 16 22.5
+25˚C 16 21 mA MB96F386/F387
+125˚C 17.5 24.5
+25˚C 17.5 23 mA MB96F388/F389
+125˚C 19 26
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
2 Flash/ROM wait states
(CLKRC and CLKSC
stopped)
+25˚C 14 18 mA MB96384/385
+125˚C 14.5 20
+25˚C 23 29 mA MB96F385
+125˚C 24.5 31.5
+25˚C 25 31 mA MB96F386/F387
+125˚C 27 35
+25˚C 28 34 mA MB96F388/F389
+125˚C 30 37.5
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
0 Flash/ROM wait states
(CLKRC and CLKSC
stopped)
+25˚C 13 17 mA MB96384/385
+125˚C 13.5 19
+25˚C 28 40 mA MB96F385
+125˚C 29.5 42.5
+25˚C 30 42 mA MB96F386/F387
+125˚C 32 46
+25˚C 32 44 mA MB96F388/F389
+125˚C 34 47.5
MB96380 Series
FME-MB96380 rev 10 71
Power supply cur-
rent in Run
modes*
ICCPLL
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
2 Flash/ROM wait states
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 23 28 mA MB96384/385
+125˚C 23.5 30
+25˚C 44 55
mA MB96F386/F387
+125˚C 46 59
PLL Run mode with
CLKS1/2 = 72MHz,
CLKB= CLKP1 = 36MHz,
CLKP2 = 18MHz
1 Flash wait state
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 37 50
mA MB96F386/F387
+125˚C 39 54
PLL Run mode with
CLKS1/2 = 80MHz,
CLKB= CLKP1 = 40MHz,
CLKP2 = 20MHz
1 Flash wait state
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 38 51 mA MB96F385
+125˚C 39.5 53.5
+25˚C 44 58
mA MB96F388/F389
+125˚C 46 61.5
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
1 ROM wait state
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 23 27.5
mA MB96384/385
+125˚C 23.5 29.5
ICCMAIN
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
1 Flash/ROM wait state
(CLKPLL, CLKSC and
CLKRC stopped)
+25˚C 2.3 3.5 mA MB96384/385
+125˚C 2.8 5
+25˚C 4.2 5.2 mA MB96F385
+125˚C 4.7 7
+25˚C 4.5 5.5 mA MB96F386/F387
+125˚C 5.2 8.5
+25˚C 4.8 5.8 mA MB96F388/F389
+125˚C 5.5 8.2
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
72 FME-MB96380 rev 10
Power supply cur-
rent in Run
modes*
ICCRCH
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped)
+25˚C 1.5 2.5 mA MB96384/385
+125˚C 2 4.1
+25˚C 2.7 3.7 mA MB96F385
+125˚C 3.2 5.4
+25˚C 2.9 4 mA MB96F386/F387
+125˚C 3.6 7
+25˚C 3 4.1 mA MB96F388/F389
+125˚C 3.7 6.5
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C 0.35 0.55 mA MB96384/385
+125˚C 0.75 1.95
+25˚C 0.4 0.6 mA MB96F385
+125˚C 0.9 2.1
+25˚C 0.4 0.6 mA MB96F386/F387
+125˚C 0.95 3.4
+25˚C 0.4 0.6 mA MB96F388/F389
+125˚C 0.95 2.8
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode, no Flash program-
ming/erasing allowed)
+25˚C 0.08 0.17 mA MB96384/385
+125˚C 0.47 1.6
+25˚C 0.15 0.25 mA MB96F385
+125˚C 0.55 1.75
+25˚C 0.15 0.25 mA MB96F386/F387
+125˚C 0.7 3.05
+25˚C 0.15 0.25 mA MB96F388/F389
+125˚C 0.7 2.45
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
FME-MB96380 rev 10 73
Power supply cur-
rent in Run
modes* ICCSUB
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKRCstopped,noFlash
programming/erasing al-
lowed)
+25˚C 0.04 0.12 mA MB96384/385
+125˚C 0.43 1.55
+25˚C 0.1 0.2 mA MB96F385
+125˚C 0.5 1.7
+25˚C 0.1 0.2 mA MB96F386/F387
+125˚C 0.65 3
+25˚C 0.1 0.2 mA MB96F388/F389
+125˚C 0.65 2.4
Power supply cur-
rent in Sleep
modes* ICCSPLL
PLL Sleep mode with
CLKS1/2 = CLKP1 =
16MHz,
CLKP2 = 8MHz
(CLKRC and CLKSC
stopped)
+25˚C 4 6 mA MB96384/385
+125˚C 4.5 8
+25˚C 4 6 mA MB96F385
+125˚C 4.6 8
+25˚C 4 6 mA MB96F386/F387
+125˚C 4.7 9
+25˚C 5 7 mA MB96F388/F389
+125˚C 5.7 9.5
PLL Sleep mode with
CLKS1/2 = CLKP1 =
32MHz,
CLKP2 = 16MHz
(CLKRC and CLKSC
stopped)
+25˚C 6.5 9 mA MB96384/385
+125˚C 7 11
+25˚C 7 9.5 mA MB96F385
+125˚C 7.6 11.5
+25˚C 7 9.5 mA MB96F386/F387
+125˚C 8 12.5
+25˚C 9 11.5 mA MB96F388/F389
+125˚C 10 14
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
74 FME-MB96380 rev 10
Power supply cur-
rent in Sleep
modes* ICCSPLL
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
(CLKRC and CLKSC
stopped)
+25˚C 6.5 8.5 mA MB96384/385
+125˚C 7 10.5
+25˚C 7 9 mA MB96F385
+125˚C 7.6 11
+25˚C 7 9 mA MB96F386/F387
+125˚C 8 12
+25˚C 9 11 mA MB96F388/F389
+125˚C 10 13.5
PLL Sleep mode with
CLKS1/2 = CLKP1=
56MHz, CLKP2 = 28MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 11 13.5 mA MB96384/385
+125˚C 11.5 15.5
+25˚C 11.5 14 mA MB96F386/F387
+125˚C 12.5 17
PLL Sleep mode with
CLKS1/2 = 72MHz,
CLKP1 = 36MHz,
CLKP2 = 18MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 9.5 11.5
mA MB96F386/F387
+125˚C 10.5 14.5
PLL Sleep mode with
CLKS1/2 = 80MHz,
CLKP1 = 40MHz,
CLKP2 = 20MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 11 13 mA MB96F385
+125˚C 11.6 15
+25˚C 13 15.5 mA MB96F388/F389
+125˚C 14 18
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
CLKP2 = 24MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 12 14
mA MB96384/385
+125˚C 12.5 16
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
FME-MB96380 rev 10 75
Power supply cur-
rent in Sleep
modes*
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
(CLKPLL, CLKSC and
CLKRC stopped)
+25˚C 1.3 1.8 mA MB96384/385
+125˚C 1.8 3.3
+25˚C 1.3 1.8 mA MB96F385
+125˚C 1.8 3.3
+25˚C 1.3 1.8 mA MB96F386/F387
+125˚C 1.9 4.6
+25˚C 1.5 2 mA MB96F388/F389
+125˚C 2.1 4.2
ICCSRCH
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
(CLKMC, CLKPLL and
CLKSC stopped)
+25˚C 0.8 1.4 mA MB96384/385
+125˚C 1.3 2.9
+25˚C 0.8 1.4 mA MB96F385
+125˚C 1.3 2.9
+25˚C 0.8 1.4 mA MB96F386/F387
+125˚C 1.4 4.2
+25˚C 0.9 1.5 mA MB96F388/F389
+125˚C 1.5 3.7
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
76 FME-MB96380 rev 10
Power supply cur-
rent in Sleep
modes*
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C 0.3 0.5 mA MB96384/385
+125˚C 0.7 1.9
+25˚C 0.3 0.5 mA MB96F385
+125˚C 0.7 2
+25˚C 0.3 0.5 mA MB96F386/F387
+125˚C 0.8 3.3
+25˚C 0.3 0.5 mA MB96F388/F389
+125˚C 0.8 2.7
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+25˚C 0.04 0.13 mA MB96384/385
+125˚C 0.43 1.55
+25˚C 0.05 0.15 mA MB96F385
+125˚C 0.44 1.6
+25˚C 0.05 0.15 mA MB96F386/F387
+125˚C 0.56 2.9
+25˚C 0.05 0.15 mA MB96F388/F389
+125˚C 0.56 2.3
ICCSSUB
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
+25˚C 0.035 0.11 mA MB96384/385
+125˚C 0.42 1.55
+25˚C 0.04 0.12 mA MB96F385
+125˚C 0.43 1.55
+25˚C 0.04 0.12 mA MB96F386/F387
+125˚C 0.54 2.9
+25˚C 0.04 0.12 mA MB96F388/F389
+125˚C 0.54 2.3
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
FME-MB96380 rev 10 77
Power supply cur-
rent in Timer
modes*
ICCTPLL
PLL Timer mode with
CLKMC=4MHz,CLKPLL
= 48MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C 1.4 1.9 mA MB96384/385
+125˚C 1.9 3.5
+25˚C 1.5 2 mA MB96F385
+125˚C 2 3.6
+25˚C 1.5 2 mA MB96F386/F387
+125˚C 2.1 5
+25˚C 1.5 2 mA MB96F388/F389
+125˚C 2.1 4.4
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C 0.35 0.5 mA MB96384/385
+125˚C 0.75 2
+25˚C 0.35 0.55 mA MB96F385
+125˚C 0.75 2
+25˚C 0.35 0.5 mA MB96F386/F387
+125˚C 0.85 3.3
+25˚C 0.35 0.5 mA MB96F388/F389
+125˚C 0.85 2.7
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
+25˚C 0.08 0.15 mA MB96384/385
+125˚C 0.47 1.6
+25˚C 0.1 0.18 mA MB96F385
+125˚C 0.5 1.6
+25˚C 0.08 0.15 mA MB96F386/F387
+125˚C 0.6 2.9
+25˚C 0.08 0.15 mA MB96F388/F389
+125˚C 0.6 2.3
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
78 FME-MB96380 rev 10
Power supply cur-
rent in Timer
modes* ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C 0.35 0.5 mA MB96384/385
+125˚C 0.75 2
+25˚C 0.35 0.5 mA MB96F385
+125˚C 0.75 2
+25˚C 0.35 0.5 mA MB96F386/F387
+125˚C 0.85 3.3
+25˚C 0.35 0.5 mA MB96F388/F389
+125˚C 0.85 2.7
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+25˚C 0.07 0.15 mA MB96384/385
+125˚C 0.46 1.6
+25˚C 0.07 0.15 mA MB96F385
+125˚C 0.46 1.6
+25˚C 0.07 0.15 mA MB96F386/F387
+125˚C 0.6 2.9
+25˚C 0.07 0.15 mA MB96F388/F389
+125˚C 0.6 2.3
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
FME-MB96380 rev 10 79
Power supply cur-
rent in Timer
modes*
ICCTRCL
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C 0.3 0.45 mA MB96384/385
+125˚C 0.65 1.9
+25˚C 0.3 0.45 mA MB96F385
+125˚C 0.65 1.9
+25˚C 0.3 0.45 mA MB96F386/F387
+125˚C 0.8 3.2
+25˚C 0.3 0.45 mA MB96F388/F389
+125˚C 0.8 2.6
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+25˚C 0.03 0.1 mA MB96384/385
+125˚C 0.41 1.55
+25˚C 0.03 0.1 mA MB96F385
+125˚C 0.41 1.55
+25˚C 0.03 0.1 mA MB96F386/F387
+125˚C 0.53 2.85
+25˚C 0.03 0.1 mA MB96F388/F389
+125˚C 0.53 2.25
ICCTSUB
Sub Timer mode with
CLKSC = 32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
+25˚C 0.03 0.1 mA MB96384/385
+125˚C 0.41 1.55
+25˚C 0.035 0.1 mA MB96F385
+125˚C 0.42 1.55
+25˚C 0.035 0.1 mA MB96F386/F387
+125˚C 0.53 2.85
+25˚C 0.035 0.1 mA MB96F388/F389
+125˚C 0.53 2.25
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
80 FME-MB96380 rev 10
Power supply cur-
rent in Stop Mode ICCH
VRCR:LPMB[2:0] = 110B
(Core voltage at 1.8V)
+25˚C 0.02 0.08 mA MB96384/385
+125˚C 0.4 1.5
+25˚C 0.02 0.08 mA MB96F385
+125˚C 0.4 1.5
+25˚C 0.02 0.08 mA MB96F386/F387
+125˚C 0.52 2.8
+25˚C 0.02 0.08 mA MB96F388/F389
+125˚C 0.52 2.2
VRCR:LPMB[2:0] = 000B
(Core voltage at 1.2V)
+25˚C 0.015 0.06 mA MB96384/385
+125˚C 0.3 1.2
+25˚C 0.015 0.06 mA MB96F385
+125˚C 0.3 1.2
+25˚C 0.015 0.06 mA MB96F386/F387
+125˚C 0.4 2.3
+25˚C 0.015 0.06 mA MB96F388/F389
+125˚C 0.4 1.65
Power supply cur-
rentforactiveLow
Voltage detector ICCLVD Low voltage detector en-
abled (RCR:LVDE = 1) +25˚C 90 140 µAThis current must be
added to all Power
supplycurrentsabove
+125˚C 100 150
Power supply cur-
rent for active
Clock modulator ICCCLOMO Clock modulator enabled
(CMCR:PDX = 1) - 3 4.5 mA Must be added to all
current above
FlashWrite/Erase
current ICCFLASH Current for one Flash
module -1540mA
Must be added to all
current above
Input capacitance CIN - 15 30 pF High current outputs
Input capacitance CIN --515pF
Other than C, AVCC,
AVSS, AVRH, AVRL,
VCC, VSS, DVCC, DVSS,
High current outputs
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of
the Hardware Manual for further details about voltage regulator control.
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Condition (at TA)Value Remarks
Typ Max Unit
MB96380 Series
FME-MB96380 rev 10 81
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Clock frequency fCX0, X1
3 - 16 MHz When using a crystal oscillator, PLL off
0 - 16 MHz Whenusinganoppositephaseexternal
clock, PLL off
3.5 - 16 MHz When using a crystal oscillator or oppo-
site phase external clock, PLL on
Clock frequency fFCI X0
0 - 56 MHz When using a single phase external
clock in “Fast Clock Input mode” (not
available in MB96F386xxA and
MB96F387xxA), PLL off
3.5 - 56 MHz When using a single phase external
clock in “Fast Clock Input mode” (not
available in MB96F386xxA and
MB96F387xxA), PLL on
Clock frequency fCL
X0A,X1A 32 32.768 100 kHz When using an oscillation circuit
0 - 100 kHz Whenusinganoppositephaseexternal
clock
X0A 0 - 50 kHz When using a single phase external
clock
Clock frequency fCR -50 100 200 kHz When usingslowfrequency of RC oscil-
lator
1 2 4 MHz When using fast frequency of RC oscil-
lator
RC clock stabili-
zation time tRCSTAB - 64 RC clock cycles Applied after any reset and when acti-
vating the RC oscillator.
PLL Clock fre-
quency fCLKVCO - 64 - 200 MHz PermittedVCOoutputfrequencyofPLL
(CLKVCO)
PLLPhaseJitter TPSKEW ---± 5ns
For CLKMC (PLL input clock) ≥4MHz,
jitter coming from external oscillator,
crystal or resonator is not covered
Inputclockpulse
width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70%
Inputclockpulse
width PWHL, PWLL X0A,X1A 5 - - µs
MB96380 Series
82 FME-MB96380 rev 10
X0
tCYL
PWH PWL
VIL
VIH
X0A
tCYLL
PWHL PWLL
VIL
VIH
MB96380 Series
FME-MB96380 rev 10 83
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol
Core Voltage Settings
Unit Remarks1.8V 1.9V
Min Max Min Max
Internal System clock fre-
quency (CLKS1 and
CLKS2) fCLKS1, fCLKS2 0 92 0 96 MHz Others than below
0 72 0 80 MHz MB96F385/F388/F389
0 68 0 74 MHz MB96F386/F387
Internal CPU clock fre-
quency (CLKB), internal
peripheralclockfrequency
(CLKP1) fCLKB, fCLKP1 0 52 0 56 MHz Others than below
0 36 0 40 MHz MB96F385/F388/F389
Internal peripheral clock
frequency (CLKP2) fCLKP2 0 28 0 32 MHz Others than below
0 26 0 28 MHz MB96F386/F387
MB96380 Series
84 FME-MB96380 rev 10
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Reset input time tRSTL RSTX 500 - - ns
0.2 VCC
RSTX
tRSTL
0.2 VCC
MB96380 Series
FME-MB96380 rev 10 85
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Power on rise time tRVcc 0.05 - 30 ms
Power off time tOFF Vcc 1 - - ms
0.2 V
tR
2.7V
tOFF
0.2 V 0.2 V
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
3 V
VCC
VCC
Rising edge of 50 mV/ms
maximum is allowed
MB96380 Series
86 FME-MB96380 rev 10
External Input timing
Note : Relocated Resource Inputs have same characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Condition Value Unit Used Pin input func-
tion
Min Max
Input pulse
width tINH
tINL
INTn(_R)
⎯
200 ⎯ns External Interrupt
NMI(_R) NMI
Pnn_m
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)⎯ns
General Purpose IO
TINn(_R) Reload Timer
TTGn(_R) PPG Trigger input
ADTG(_R) AD Converter Trigger
FRCKn(_R) Free Running Timer
external clock
INn(_R) Input Capture
VIL
VIH
tINH
VIL
VIH
tINL
External Pin input
MB96380 Series
FME-MB96380 rev 10 87
Slew Rate High Current Outputs
Note : Relocated Resource Inputs have same characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Output
rise/fall
time
tR30
tF30 I/O circuit type M
Output
driving
strength
set to
“30mA”
15 ⎯ns
VL
VH
VL
VH
tR30 tF30
• Slew rate output timing VH=VOL30 + 0.9 ×(VOH30 -VOL30)
VL=VOL30 + 0.1 ×(VOH30 -VOL30)
MB96380 Series
88 FME-MB96380 rev 10
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must then be increased by 10ns.
Basic Timing (TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
ECLK
tCYC
ECLK ⎯
25 ⎯
nstCHCL tCYC/2-5 tCYC/2+5
tCLCH tCYC/2-5 tCYC/2+5
ECLK →
UBX/ LBX / CSn time
tCHCBH
CSn, UBX,
LBX, ECLK ⎯
-20 20
ns
tCHCBL -20 20
tCLCBH -20 20
tCLCBL -20 20
ECLK → ALE time
tCHLH
ALE, ECLK ⎯
-10 10
ns
tCHLL -10 10
tCLLH -10 10
tCLLL -10 10
ECLK →address valid time
(non-multiplexed) tCHAV A[23:0], ECLK EBM:NMS=1 -15 15 ns
tCLAV -15 15
ECLK →address valid time
(multiplexed)
tCHAV A[23:16],
ECLK EBM:NMS=0 -15 15 ns
tCLAV -15 15
tCLADV AD[15:0],
ECLK EBM:NMS=0 -15 15 ns
tCHADV -15 15
ECLK → RDX /WRX time
tCHRWH RDX, WRX,
WRLX,WRHX,
ECLK ⎯
-10 10
ns
tCHRWL -10 10
tCLRWH -10 10
tCLRWL -10 10
MB96380 Series
FME-MB96380 rev 10 89
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
ECLK
tCYC
ECLK ⎯
30 ⎯
nstCHCL tCYC/2-8 tCYC/2+8
tCLCH tCYC/2-8 tCYC/2+8
ECLK →
UBX/ LBX / CSn time
tCHCBH
CSn, UBX,
LBX, ECLK ⎯
-25 25
ns
tCHCBL -25 25
tCLCBH -25 25
tCLCBL -25 25
ECLK → ALE time
tCHLH
ALE, ECLK ⎯
-15 15
ns
tCHLL -15 15
tCLLH -15 15
tCLLL -15 15
ECLK →address valid time
(non-multiplexed) tCHAV A[23:0], ECLK EBM:NMS=1 -20 20 ns
tCLAV -20 20
ECLK →address valid time
(multiplexed)
tCHAV A[23:16],
ECLK EBM:NMS=0 -20 20 ns
tCLAV -20 20
tCLADV AD[15:0],
ECLK EBM:NMS=0 -20 20 ns
tCHADV -20 20
ECLK → RDX /WRX time
tCHRWH RDX, WRX,
WRLX, WRHX,
ECLK ⎯
-15 15
ns
tCHRWL -15 15
tCLRWH -15 15
tCLRWL -15 15
MB96380 Series
90 FME-MB96380 rev 10
ECLK
tCYC
CSn
ALE
A[23:0]
0.2*Vcc
tCHCL
tCHAV
tCHCBL tCHCBH
LBX UBX
tCLLH tCHLL tCHLH tCLLL
tCLADV
AD[15:0] Address
tCLAV
tCHADV
tCLCBH tCLCBL
tCHRWH
tCLRWH tCLRWL
tCHRWL
RDX
WRX (WRLX, WRHX)
0.8*Vcc
tCLCH
Refer to the Hardware Manual for detailed Timing Charts
MB96380 Series
FME-MB96380 rev 10 91
Bus Timing (Read) (TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Sym-
bol Pin Conditions Value Unit Remarks
Min Max
ALE pulse width
(multiplexed) tLHLL ALE
EACL:STS=0 and
EACL:ACE=0 tCYC/2 −5⎯
ns
EBM:NMS=
0
EACL:STS=1 tCYC −5⎯
EACL:STS=0 and
EACL:ACE=1 3tCYC/2 −5⎯
Valid address
⇒ ALE ↓ time
(multiplexed)
tAVLL ALE, A[23:16],
EACL:STS=0 and
EACL:ACE=0 tCYC −15 ⎯
ns
EACL:STS=1 and
EACL:ACE=0 3tCYC/2 −15 ⎯
EACL:STS=0 and
EACL:ACE=1 2tCYC −15 ⎯
EACL:STS=1 and
EACL:ACE=1 5tCYC/2 −15 ⎯
tADVLL ALE,AD[15:0]
EACL:STS=0 and
EACL:ACE=0 tCYC/2 −15 ⎯
ns
EACL:STS=1 and
EACL:ACE=0 tCYC −15 ⎯
EACL:STS=0 and
EACL:ACE=1 3tCYC/2 −15 ⎯
EACL:STS=1 and
EACL:ACE=1 2tCYC −15 ⎯
ALE ↓
⇒ Address valid time
(multiplexed) tLLAX ALE, AD[15:0] EACL:STS=0 tCYC/2 −15 ⎯ns
EACL:STS=1 -15 ⎯
Valid address
⇒ RDX ↓ time
(non-multiplexed) tAVRL RDX, A[23:0] EBM:NMS= 1 tCYC/2 −15 ⎯ns
Valid address
⇒ RDX ↓ time
(multiplexed)
tAVRL RDX, A[23:16]
EACL:ACE=0
EBM:NMS=0 3tCYC/2 −15 ⎯ns
EACL:ACE=1
EBM:NMS=0 5tCYC/2 −15 ⎯
tADVRL RDX, AD[15:0]
EACL:ACE=0
EBM:NMS=0 tCYC −15 ⎯ns
EACL:ACE=1
EBM:NMS=0 2tCYC −15 ⎯
Valid address
⇒ Valid data input
(non-multiplexed) tAVDV A[23:0],
AD[15:0] EBM:NMS= 1 ⎯2tCYC −55 ns w/o cycle
extension
MB96380 Series
92 FME-MB96380 rev 10
Valid address
⇒ Valid data input
(multiplexed)
tAVDV A[23:16],
AD[15:0]
EACL:ACE=0
EBM:NMS=0 ⎯3tCYC −55 ns w/o cycle
extension
EACL:ACE=1
EBM:NMS=0 ⎯4tCYC −55
tADVDV AD[15:0]
EACL:ACE=0
EBM:NMS=0 ⎯5tCYC/2 −55 ns w/o cycle
extension
EACL:ACE=1
EBM:NMS=0 ⎯7tCYC/2 −55
RDX pulse width tRLRH RDX ⎯3 tCYC/2 − 5 ⎯ns w/o cycle
extension
RDX ↓⇒ Valid data input tRLDV RDX, AD[15:0] ⎯⎯3tCYC/2 −50 ns w/o cycle
extension
RDX ↑⇒ Data hold time tRHDX RDX, AD[15:0] ⎯0⎯ns
Address valid ⇒Data hold
time tAXDX A[23:0],
AD[15:0] ⎯0⎯ns
RDX ↑⇒ ALE ↑ time tRHLH RDX, ALE
EACL:STS=1 and
EACL:ACE=1 3tCYC/2 −10 ⎯ns
other ECL:STS,
EACL:ACE setting tCYC/2 −10 ⎯
Valid address
⇒ ECLK ↑ time tAVCH A[23:0], ECLK ⎯tCYC −15 ⎯ns
tADVCH AD[15:0], ECLK tCYC/2 −15 ⎯
RDX ↓⇒ ECLK ↑ time tRLCH RDX, ECLK ⎯tCYC/2 −10 ⎯ns
ALE ↓⇒ RDX ↓ time tLLRL ALE, RDX EACL:STS=0 tCYC/2 −10 ⎯ns
EACL:STS=1 −10 ⎯
ECLK↑⇒ Valid data input tCHDV AD[15:0], ECLK ⎯⎯tCYC −50 ns
(TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Sym-
bol Pin Conditions Value Unit Remarks
Min Max
MB96380 Series
FME-MB96380 rev 10 93
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive = 5mA, CL= 50pF)
Parameter Sym-
bol Pin Conditions Value Unit Remarks
Min Max
ALE pulse width
(multiplexed) tLHLL ALE
EACL:STS=0 and
EACL:ACE=0 tCYC/2 − 8 ⎯
ns
EBM:NMS
= 0
EACL:STS=1 tCYC − 8 ⎯
EACL:STS=0 and
EACL:ACE=1 3tCYC/2 − 8 ⎯
Valid address
⇒ ALE ↓ time
(multiplexed)
tAVLL ALE, A[23:16],
EACL:STS=0 and
EACL:ACE=0 tCYC −20 ⎯
ns
EACL:STS=1 and
EACL:ACE=0 3tCYC/2 −20 ⎯
EACL:STS=0 and
EACL:ACE=1 2tCYC −20 ⎯
EACL:STS=1 and
EACL:ACE=1 5tCYC/2 −20 ⎯
tADVLL ALE, AD[15:0]
EACL:STS=0 and
EACL:ACE=0 tCYC/2 −20 ⎯
ns
EACL:STS=1 and
EACL:ACE=0 tCYC −20 ⎯
EACL:STS=0 and
EACL:ACE=1 3tCYC/2 −20 ⎯
EACL:STS=1 and
EACL:ACE=1 2tCYC −20 ⎯
ALE ↓
⇒ Address valid time
(multiplexed) tLLAX ALE, AD[15:0] EACL:STS=0 tCYC/2 −20 ⎯ns
EACL:STS=1 -20 ⎯
Valid address
⇒ RDX ↓ time
(non-multiplexed) tAVRL RDX, A[23:0] EBM:NMS= 1 tCYC/2 −20 ⎯ns
Valid address
⇒ RDX ↓ time
(multiplexed)
tAVRL RDX, A[23:16]
EACL:ACE=0
EBM:NMS=0 3tCYC/2 −20 ⎯ns
EACL:ACE=1
EBM:NMS=0 5tCYC/2 −20 ⎯
tADVRL RDX, AD[15:0]
EACL:ACE=0
EBM:NMS=0 tCYC −20 ⎯ns
EACL:ACE=1
EBM:NMS=0 2tCYC −20 ⎯
Valid address
⇒ Valid data input
(non-multiplexed) tAVDV A[23:0],
AD[15:0] EBM:NMS= 1 ⎯2tCYC −60 ns w/o cycle
extension
MB96380 Series
94 FME-MB96380 rev 10
Valid address
⇒ Valid data input
(multiplexed)
tAVDV A[23:16],
AD[15:0]
EACL:ACE=0
EBM:NMS=0 ⎯3tCYC −60 ns w/o cycle
extension
EACL:ACE=1
EBM:NMS=0 ⎯4tCYC −60
tADVDV AD[15:0]
EACL:ACE=0
EBM:NMS=0 ⎯5tCYC/2 −60 ns w/o cycle
extension
EACL:ACE=1
EBM:NMS=0 ⎯7tCYC/2 −60
RDX pulse width tRLRH RDX ⎯3tCYC/2 − 8 ⎯ns w/o cycle
extension
RDX ↓⇒ Valid data input tRLDV RDX, AD[15:0] ⎯⎯3tCYC/2 −55 ns w/o cycle
extension
RDX ↑⇒ Data hold time tRHDX RDX, AD[15:0] ⎯0⎯ns
Address valid ⇒Data hold
time tAXDX A[23:0] ⎯0⎯ns
RDX ↑⇒ ALE ↑ time tRHLH RDX, ALE
EACL:STS=1 and
EACL:ACE=1 3tCYC/2 −15 ⎯ns
other ECL:STS,
EACL:ACE setting tCYC/2 −15 ⎯
Valid address
⇒ ECLK ↑ time tAVCH A[23:0], ECLK ⎯tCYC −20 ⎯ns
tADVCH AD[15:0], ECLK tCYC/2 −20 ⎯
RDX ↓⇒ ECLK ↑ time tRLCH RDX, ECLK ⎯tCYC/2 −15 ⎯ns
ALE ↓⇒ RDX ↓ time tLLRL ALE, RDX EACL:STS=0 tCYC/2 −15 ⎯ns
EACL:STS=1 −15 ⎯
ECLK↑⇒ Valid data input tCHDV AD[15:0], ECLK ⎯⎯tCYC −55 ns
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive = 5mA, CL= 50pF)
Parameter Sym-
bol Pin Conditions Value Unit Remarks
Min Max
MB96380 Series
FME-MB96380 rev 10 95
.
Bus Timing (Write) (TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Valid address
⇒ WRX ↓ time
(non-multiplexed) tAVWL WRX, WRLX,
WRHX,
A[23:0]
EACL:STS=0
EBM:NMS=1 tCYC/2 −15 ⎯ns
EACL:STS=1
EBM:NMS=1 tCYC −15 ⎯
Valid address
⇒ WRX ↓ time
(multiplexed)
tAVWL WRX, WRLX,
WRHX,
A[23:16]
EACL:ACE=0
EBM:NMS=0 3tCYC/2 −
15 ⎯ns
EACL:ACE=1
EBM:NMS=0 5tCYC/2 −
15 ⎯
tADVWL WRX, WRLX,
WRHX,
AD[15:0]
EACL:ACE=0
EBM:NMS=0 tCYC −15 ⎯ns
EACL:ACE=1
EBM:NMS=0 2tCYC −15 ⎯
WRX pulse width tWLWH WRX, WRXL,
WRHX ⎯tCYC − 5 ⎯ns w/o cycle
extension
A[23:0]
AD[15:0] Address VIL
VIH VIH
VIL Read data
tRHDX
tRLDV
tADVDV
ECLK
tADVCH
0.8*Vcc
tRLCH
ALE tLHLL
tRHLH
0.2*VCC
tLLAX
tADVLL
RDX
tLLRL
tRLRHtADVRL
tAVCH
tAVLL
tAVDV
tAVRL
tCHDV
tAXDX
Refer to the Hardware Manual for detailed Timing Charts
MB96380 Series
96 FME-MB96380 rev 10
Valid data output
⇒ WRX ↑ time tDVWH WRX, WRLX,
WRHX,
AD[15:0] ⎯tCYC − 20 ⎯ns w/o cycle
extension
WRX ↑
⇒ Data hold time tWHDX WRX, WRLX,
WRHX,
AD[15:0] ⎯tCYC/2 −15 ⎯ns
WRX ↑
⇒ Address valid time
(non-multiplexed) tWHAX WRX, WRLX,
WRHX, A[23:0]
EACL:STS=1
EBM:NMS=1 − 15 ⎯ns
EACL:STS=0
EBM:NMS=1 tCYC/2 − 15 ⎯ns
WRX ↑
⇒ Address valid time
(multiplexed) tWHAX WRX, WRLX,
WRHX,
A[23:16] EBM:NMS=0 tCYC/2 − 15 ⎯ns
WRX ↑⇒ALE ↑time
(multiplexed) tWHLH WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1 2tCYC − 10 ⎯
ns EBM:NMS=0
other EBM:ACE
and
EACL:STS setting tCYC − 10 ⎯
WRX ↓⇒ ECLK ↑
time tWLCH WRX, WRLX,
WRHX, ECLK ⎯tCYC/2 − 10 ⎯ns
CSn ⇒ WRX time
(non-multiplexed) tCSLWL WRX, WRLX,
WRHX, CSn
EACL:STS=0
EBM:NMS=1 ⎯tCYC/2 −15 ns
EACL:STS=1
EBM:NMS=1 ⎯tCYC −15
CSn ⇒ WRX time
(multiplexed) tCSLWL WRX, WRLX,
WRHX, CSn
EACL:ACE=0
EBM:NMS=0 ⎯3tCYC/2 −
15 ns
EACL:ACE=1
EBM:NMS=0 ⎯5tCYC/2 −
15
WRX ⇒ CSn time
(non-multiplexed) tWHCSH WRX, WRLX,
WRHX, CSn
EACL:STS=1
EBM:NMS=1 − 15 ⎯ns
EACL:STS=0
EBM:NMS=1 tCYC/2 − 15 ⎯ns
WRX ⇒ CSn time
(multiplexed) tWHCSH WRX, WRLX,
WRHX, CSn EBM:NMS=0 tCYC/2 − 15 ⎯ns
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Valid address
⇒ WRX ↓ time
(non-multiplexed) tAVWL WRX, WRLX,
WRHX,
A[23:0]
EACL:STS=0
EBM:NMS=1 tCYC/2 −20 ⎯ns
EACL:STS=1
EBM:NMS=1 tCYC −20 ⎯
(TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
MB96380 Series
FME-MB96380 rev 10 97
Valid address
⇒ WRX ↓ time
(multiplexed)
tAVWL WRX, WRLX,
WRHX,
A[23:16]
EACL:ACE=0
EBM:NMS=0 3tCYC/2 −
20 ⎯ns
EACL:ACE=1
EBM:NMS=0 5tCYC/2 −
20 ⎯
tADVWL WRX, WRLX,
WRHX,
AD[15:0]
EACL:ACE=0
EBM:NMS=0 tCYC −20 ⎯ns
EACL:ACE=1
EBM:NMS=0 2tCYC −20 ⎯
WRX pulse width tWLWH WRX, WRXL,
WRHX ⎯tCYC − 8 ⎯ns w/o cycle
extension
Valid data output
⇒ WRX ↑ time tDVWH WRX, WRLX,
WRHX,
AD[15:0] ⎯tCYC − 25 ⎯ns w/o cycle
extension
WRX ↑
⇒ Data hold time tWHDX WRX, WRLX,
WRHX,
AD[15:0] ⎯tCYC/2 −20 ⎯ns
WRX ↑
⇒ Address valid time
(non-multiplexed) tWHAX WRX, WRLX,
WRHX, A[23:0]
EACL:STS=1
EBM:NMS=1 − 20 ⎯ns
EACL:STS=0
EBM:NMS=1 tCYC/2 − 20 ⎯ns
WRX ↑
⇒ Address valid time
(multiplexed) tWHAX WRX, WRLX,
WRHX,
A[23:16] EBM:NMS=0 tCYC/2 − 20 ⎯ns
WRX ↑⇒ALE ↑time
(multiplexed) tWHLH WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1 2tCYC − 15 ⎯
ns EBM:NMS=0
other EBM:ACE
and
EACL:STS setting tCYC − 15 ⎯
WRX ↓⇒ ECLK ↑
time tWLCH WRX, WRLX,
WRHX, ECLK ⎯tCYC/2 − 15 ⎯ns
CSn ⇒ WRX time
(non-multiplexed) tCSLWL WRX, WRLX,
WRHX, CSn
EACL:STS=0
EBM:NMS=1 ⎯tCYC/2 −20 ns
EACL:STS=1
EBM:NMS=1 ⎯tCYC −20
CSn ⇒ WRX time
(multiplexed) tCSLWL WRX, WRLX,
WRHX, CSn
EACL:ACE=0
EBM:NMS=0 ⎯3tCYC/2 −
20 ns
EACL:ACE=1
EBM:NMS=0 ⎯5tCYC/2 −
20
WRX ⇒ CSn time
(non-multiplexed) tWHCSH WRX, WRLX,
WRHX, CSn
EACL:STS=1
EBM:NMS=1 − 20 ⎯ns
EACL:STS=0
EBM:NMS=1 tCYC/2 − 20 ⎯ns
WRX ⇒ CSn time
(multiplexed) tWHCSH WRX, WRLX,
WRHX, CSn EBM:NMS=0 tCYC/2 − 20 ⎯ns
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
MB96380 Series
98 FME-MB96380 rev 10
.
Ready Input Timing
Note : If the RDY setup time is insufficient, use the auto-ready function.
(TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Test
Condition Rated Value Units Remarks
Min Max
RDY setup time tRYHS RDY ⎯35 ⎯ns
RDY hold time tRYHH RDY 0 ⎯ns
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Test
Condition Rated Value Units Remarks
Min Max
RDY setup time tRYHS RDY ⎯45 ⎯ns
RDY hold time tRYHH RDY 0 ⎯ns
ECLK
tWLCH
0.8*VCC
ALE
tWHLH
WRX (WRLX, WRHX)
tWLWH
tADVWL
A[23:0]
tWHAX
AD[15:0] Address Write data
tDVWH tWHDX
CSn
tWHCSH
tAVWL
tCSLWL
0.2*VCC
Refer to the Hardware Manual for detailed Timing Charts
MB96380 Series
FME-MB96380 rev 10 99
Hold Timing (TA=−40 °Cto+125 °C, VCC =5.0 V ±10%,VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Units Remarks
Min Max
Pin floating ⇒ HAKX ↓ time tXHAL HAKX ⎯tCYC −20 tCYC + 20 ns
HAKX ↑ time ⇒ Pin valid time tHAHV HAKX tCYC −20 tCYC +20 ns
(TA=−40 °Cto+125 °C, VCC =3.0 to 4.5V, VSS =0.0 V, IOdrive =5mA,CL= 50pF)
Parameter Symbol Pin Condition Value Units Remarks
Min Max
Pin floating ⇒ HAKX ↓ time tXHAL HAKX ⎯tCYC −25 tCYC +25 ns
HAKX ↑ time ⇒ Pin valid time tHAHV HAKX tCYC −25 tCYC +25 ns
ECLK
RDY
When WAIT is not used.
VIH VIH
tRYHH
RDY
When WAIT is used.
tRYHS
VIL
0.8*VCC
Refer to the Hardware Manual for detailed Timing Charts
HAKX
Each pin High-Z
tHAHV
tXHAL
0.8*VCC
0.2*VCC
0.8*VCC
0.2*VCC
Refer to the Hardware Manual for detailed Timing Charts
MB96380 Series
100 FME-MB96380 rev 10
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must then be increased by 10ns.
Notes: •AC characteristic in CLK synchronized mode.
•CL is the load capacity value of pins when testing.
•Dependingonthe usedmachine clockfrequency, themaximumpossiblebaudratecan belimited bysome
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
•tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL= 50pF)
Parameter Symbol Pin Condition VCC =AVCC=4.5V
to 5.5V VCC =AVCC= 3.0V
to 4.5V Unit
Min Max Min Max
Serial clock cycle time tSCYCI SCKn
Internal Shift
Clock Mode
4 tCLKP1 ⎯4 tCLKP1 ⎯ns
SCK ↓→ SOT delay
time tSLOVI SCKn,
SOTn -20 +20 -30 +30 ns
SOT → SCK ↑ delay
time tOVSHI SCKn,
SOTn N*tCLKP1
- 20 *1 ⎯N*tCLKP1 -
30 *1 ⎯ns
Valid SIN → SCK ↑tIVSHI SCKn,
SINn tCLKP1 +
45 ⎯tCLKP1 +
55 ⎯ns
SCK ↑→ Valid SIN
hold time tSHIXI SCKn,
SINn 0⎯0⎯ns
Serial clock “L” pulse
width tSLSHE SCKn
ExternalShift
Clock Mode
tCLKP1 +
10 ⎯tCLKP1 +
10 ⎯ns
Serial clock “H” pulse
width tSHSLE SCKn tCLKP1 +
10 ⎯tCLKP1 +
10 ⎯ns
SCK ↓→ SOT delay
time tSLOVE SCKn,
SOTn ⎯2 tCLKP1
+ 45 ⎯2 tCLKP1
+ 55 ns
Valid SIN → SCK ↑tIVSHE SCKn,
SINn tCLKP1/2
+ 10 ⎯tCLKP1/2+
10 ⎯ns
SCK ↑→ Valid SIN
hold time tSHIXE SCKn,
SINn tCLKP1 +
10 ⎯tCLKP1 +
10 ⎯ns
SCK fall time tFE SCKn ⎯20 ⎯20 ns
SCK rise time tRE SCKn ⎯20 ⎯20 ns
tSCYCI N
4*tCLKP1 2
5*tCLKP1, 6*tCLKP1 3
7*tCLKP1, 8*tCLKP1 4
... ...
MB96380 Series
FME-MB96380 rev 10 101
Internal Shift Clock Mode
SOT
tSLOVI
SIN VIL
VIH
tIVSHI
VIL
VIH
tSHIXI
tOVSHI
SCK for
ESCR:SCES = 0 0.8*VCC
tSCYCI
SCK for
ESCR:SCES = 1 0.8*VCC 0.8*VCC
0.2*VCC
0.2*VCC
0.2*VCC
0.8*VCC
0.2*VCC
External Shift Clock Mode
tFE
VIL
VILVIL
VIL
SOT
tSLOVE
SIN VIL
VIH
tIVSHE
VIL
VIH
tSHIXE
VIH
tRE
VIH
tSLSHE
VIL
VIH
tSHSLE
VIH
VIH
SCK for
ESCR:SCES = 0
SCK for
ESCR:SCES = 1
0.8*VCC
0.2*VCC
MB96380 Series
102 FME-MB96380 rev 10
I2C Timing
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
•VOH = 0.7 * VCC
•VOL = 0.3 * VCC
• CMOS Hysteresis 0.7/0.3 input selected
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter Symbol Standard-mode Fast-mode*1Unit
Min Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition
SDA↓→SCL↓tHDSTA 4.0 ⎯0.6 ⎯µs
“L” width of the SCL clock tLOW 4.7 ⎯1.3 ⎯µs
“H” width of the SCL clock tHIGH 4.0 ⎯0.6 ⎯µs
Set-up time for a repeated START condition
SCL↑→SDA↓tSUSTA 4.7 ⎯0.6 ⎯µs
Data hold time
SCL↓→SDA↓↑ tHDDAT 0 3.45 0 0.9 µs
Data set-up time
SDA↓↑→SCL↑tSUDAT 250 ⎯100 ⎯ns
Set-up time for STOP condition
SCL↑→SDA↑tSUSTO 4.0 ⎯0.6 ⎯µs
Bus free time between a STOP and START
condition tBUS 4.7 ⎯1.3 ⎯µs
Outputfalltimefrom 0.7*Vccto0.3*Vccwith
a bus capacitance from 10 pF to 400 pF tof 20 + 0.1*Cb *2250 20 + 0.1*Cb *2250 ns
Capacitive load for each bus line Cb⎯400 ⎯400 pF
Pulse width of spikes which will be sup-
pressed by input noise filter tSP n/a n/a 0 1*tCLKP1*3ns
SDA
SCL
t
LOW
t
SUDAT
t
HDSTA
t
BUS
t
HDSTA
t
HDDAT
t
HIGH
t
SUSTA
t
SUSTO
MB96380 Series
FME-MB96380 rev 10 103
5. Analog Digital Converter
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Resolution - - - - 10 bit
Total error - - - - ±3 LSB
Nonlinearity error - - - - ±2.5 LSB
Differentialnonlinearity
error --
--± 1.9 LSB
Zero transition voltage VOT ANn AVRL -
1.5 LSB AVRL+
0.5 LSB AVRL +
2.5 LSB V
Full scale transition
voltage VFST ANn AVRH -
3.5 LSB AVRH -
1.5 LSB AVRH+
0.5 LSB V
Compare time - - 1.0 - 16,500 µs 4.5V ≤ ΑVCC ≤ 5.5V
2.0 - - µs 3.0V ≤ ΑVCC < 4.5V
Sampling time - - 0.5 - - µs 4.5V ≤ ΑVCC ≤ 5.5V
1.2 - - µs 3.0V ≤ ΑVCC < 4.5V
Analog input leakage
current (during conver-
sion) IAIN ANn
-1 - +1 µATA≤ 105 ˚C,
AVSS, AVRL < VI <
AVCC, AVRH
-1.2 - +1.2 µA105 ˚C <TA≤125 ˚C,
AVSS, AVRL < VI <
AVCC, AVRH
Analog input voltage
range VAIN ANn AVRL - AVRH V
Reference voltage
range
AVRH AVRH/
AVRH2 0.75
AVcc - AVcc V
AVRL AVRL AVSS -0.25
AVCC V
Power supply current IAAVcc - 2.5 5 mA A/D Converter active
IAH AVcc - - 5 µAA/DConverternotop-
erated
Reference voltage cur-
rent
IRAVRH/
AVRL - 0.7 1 mA A/D Converter active
IRH AVRH/
AVRL --5µAA/DConverternotop-
erated
Offset between input
channels - ANn - - 4 LSB
MB96380 Series
104 FME-MB96380 rev 10
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
3FF
3FE
3FD
004
003
002
001
AVRL AVRH
VNT
1.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Actual conversion
characteristics
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Analog input
Total error of digital output “N” =VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB = (Ideal value) AVRH − AVRL
1024 [V]
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
Total error
N: A/D converter digital output value
MB96380 Series
FME-MB96380 rev 10 105
3FF
3FE
3FD
004
003
002
001
AVRL AVRH AVRL AVRH
N + 1
N
N − 1
N − 2
VOT (actual measurement value)
{1 LSB × (N − 1)
+ VOT }
Actual conversion
characteristics
VFST (actual
measurement
value)
VNT (actual
measurement value)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog inputAnalog input
VNT
(actual measurement value)
V (N + 1) T
(actual measurement
value)
Nonlinearity error Differential nonlinearity error
Differential nonlinearity error of digital output N =
1 LSB =
Nonlinearity error of digital output N =VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
V (N+1)T− VNT
1 LSB −1 LSB [LSB]
VFST − VOT
1022 [V]
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
MB96380 Series
106 FME-MB96380 rev 10
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal
sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and
the AVcc voltage level. The following replacement model can be used for the calculation:
The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement
model above can be used:
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC)× CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5µs for 4.5V ≤AVcc ≤5.5V; 1.2 µs for 3.0V ≤AVcc <4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this
case the internal sampling capacitance CADC will be charged out of this external capacitance.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input
leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total
leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL
cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Comparator
Sampling switch
RADC
CADC
Analog
Rext
Cext
input
MCU
Source
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤AVcc ≤5.5V
12kΩ (max) for 3.0V ≤AVcc <4.5V
CADC: sampling capacitance within MCU: 10pF (max)
CIN
CIN: capacitance of MCU input pin: 15pF (max)
MB96380 Series
FME-MB96380 rev 10 107
6. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Power supply current
IA5ALMF
AVCC
-2545µAAlarm comparator
enabled in fast
mode(onechannel)
IA5ALMS -713µAAlarm comparator
enabled in slow
mode(onechannel)
IA5ALMH --5µAAlarm comparator
disabled
ALARM pin input cur-
rent IALIN
ALARM0,
ALARM1
-1 - +1 µATA = 25 ˚C
-3 - +3 µATA = 125 ˚C
ALARM pin input volt-
age range VALIN 0-AVCC V
External low threshold
high->low transition VEVTL(H->L) 0.36* AVCC
-0.25 0.36*AVCC
-0.1 -V
INTREF = 0
External low threshold
low->high transition VEVTL(L->H) -0.36*AVCC
+0.1 0.36 * AVCC
+0.25 V
Externalhighthreshold
high->low transition VEVTH(H->L) 0.78 * AVCC
-0.25 0.78*AVCC
-0.1 -V
Externalhighthreshold
low->high transition VEVTH(L->H) 0.78*AVCC
+0.1 0.78 * AVCC
+0.25 V
Internal low threshold
high->low transition VIVTL(H->L) 0.9 1.1 - V
INTREF = 1
Internal low threshold
low->high transition VIVTL(L->H) - 1.3 1.55 V
Internal high threshold
high->low transition VIVTH(H->L) 2.2 2.4 - V
Internal high threshold
low->high transition VIVTH(L->H) - 2.6 2.85 V
Switching hysteresis VHYS 50 - 300 mV
Comparison time tCOMPF - 0.1 1 µs CMD = 1 (fast)
tCOMPS -110µs CMD = 0 (slow)
Power-up stabilization
time after enabling
alarm comparator tPD - 1 10 ms Threshold levels
specifiedaboveare
not guaranteed
within this time
Slow/Fast mode transi-
tion time tCMD - 100 500 µs
MB96380 Series
108 FME-MB96380 rev 10
Comparator
Output
VxVTx(L->H)
VHYS VALIN
H
LVxVTx(H->L)
MB96380 Series
FME-MB96380 rev 10 109
7. Low Voltage Detector characteristics
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
For correct detection, the slope of the voltage level must satisfy .
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
“Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to
3.0V).
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Parameter Symbol Value Unit Remarks
Min Max
Stabilizationtime TLVDSTAB -75µsAfter power-up or change
of detection level
Level 0 VDL0 2.7 2.9 V CILCR:LVL[3:0]=”0000”
Level 1 VDL1 2.9 3.1 V CILCR:LVL[3:0]=”0001”
Level 2 VDL2 3.1 3.3 V CILCR:LVL[3:0]=”0010”
Level 3 VDL3 3.5 3.75 V CILCR:LVL[3:0]=”0011”
Level 4 VDL4 3.6 3.85 V CILCR:LVL[3:0]=”0100”
Level 5 VDL5 3.7 3.95 V CILCR:LVL[3:0]=”0101”
Level 6 VDL6 3.8 4.05 V CILCR:LVL[3:0]=”0110”
Level 7 VDL7 3.9 4.15 V CILCR:LVL[3:0]=”0111”
Level 8 VDL8 4.0 4.25 V CILCR:LVL[3:0]=”1000”
Level 9 VDL9 4.1 4.35 V CILCR:LVL[3:0]=”1001”
Level 10 VDL10 not used
Level 11 VDL11 not used
Level 12 VDL12 not used
Level 13 VDL13 not used
Level 14 VDL14 not used
Level 15 VDL15 not used
td
dV0.004 V
µs
-----
≤
MB96380 Series
110 FME-MB96380 rev 10
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
Time [s]
VCC
VDLx, Min
VDLx, Max
dV
dt
Low Voltage Reset Assertion
Normal Operation Power Reset Extension Time
MB96380 Series
FME-MB96380 rev 10 111
8. FLASH memory program/erase characteristics
*1:This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Value Unit Remarks
Min Typ Max
Sector erase time - 0.9 3.6 s Without erasure pre-program-
ming time
Chip erase time - n*0.9 n*3.6 s Without erasure pre-program-
ming time (n is the number of
Flash sector of the device)
Word (16-bit width) programming time - 23 370 us Without overhead time for sub-
mitting write command
Program/Erase cycle 10 000 - - cycle
Flash data retention time 20 - - year *1
MB96380 Series
112 FME-MB96380 rev 10
■EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in differ-
ent operation modes.
Common condition for all operation modes:
•V
CC = AVCC = 5.0V
• Main clock = 4MHz external clock
• Sub clock = 32kHz external clock
Operation mode details:
Mode name Details
PLL Run 56 PLL Run mode current ICCPLL with the following settings:
•f
CLKS1 = fCLKS2 = fCLKB = fCLKP1 = 56MHz
•f
CLKP2 = 28MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 2 Flash/ROM wait states (MTCRA=233AH)
• RC oscillator and Sub oscillator stopped
PLL Run 48 PLL Run mode current ICCPLL with the following settings:
•f
CLKS1 = fCLKS2 = 96MHz
•f
CLKB = fCLKP1 = 48MHz
•f
CLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 1 Flash/ROM wait states (MTCRA=6B09H)
• RC oscillator and Sub oscillator stopped
PLL Run 40 PLL Run mode current ICCPLL with the following settings:
•f
CLKS1 = fCLKS2 = 80MHz
•f
CLKB = fCLKP1 = 40MHz
•f
CLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 1 Flash/ROM wait states (MTCRA=6B09H)
• RC oscillator and Sub oscillator stopped
PLL Run 36 PLL Run mode current ICCPLL with the following settings:
•f
CLKS1 = fCLKS2 = 72MHz
•f
CLKB = fCLKP1 = 36MHz
•f
CLKP2 = 18MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 1 Flash/ROM wait states (MTCRA=6B09H)
• RC oscillator and Sub oscillator stopped
MB96380 Series
FME-MB96380 rev 10 113
PLL Run 24 PLL Run mode current ICCPLL with the following settings:
•f
CLKS1 = fCLKS2 = 48MHz
•f
CLKB = fCLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 0 Flash/ROM wait states (MTCRA=2208H)
• RC oscillator and Sub oscillator stopped
Main Run Main Run mode current ICCMAIN with the following settings:
•f
CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Sub oscillator stopped
RC Run 2M RC Run mode current ICCRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•f
CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
RC Run 100k RC Run mode current ICCRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•f
CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
Sub Run Sub Run mode current ICCSUB with the following settings:
•f
CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Main oscillator stopped
PLL Sleep 56 PLL Sleep mode current ICCSPLL with the following settings:
•f
CLKS1 = fCLKS2 = fCLKP1 = 56MHz
•f
CLKP2 = 28MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
Mode name Details
MB96380 Series
114 FME-MB96380 rev 10
PLL Sleep 48 PLL Sleep mode current ICCSPLL with the following settings:
•f
CLKS1 = fCLKS2 = 96MHz
•f
CLKP1 = 48MHz
•f
CLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
PLL Sleep 40 PLL Sleep mode current ICCSPLL with the following settings:
•f
CLKS1 = fCLKS2 = 80MHz
•f
CLKP1 = 40MHz
•f
CLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
PLL Sleep 36 PLL Sleep mode current ICCSPLL with the following settings:
•f
CLKS1 = fCLKS2 = 72MHz
•f
CLKP1 = 36MHz
•f
CLKP2 = 18MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
PLL Sleep 24 PLL Sleep mode current ICCSPLL with the following settings:
•f
CLKS1 = fCLKS2 = 48MHz
•f
CLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
Main Sleep Main Sleep mode current ICCSMAIN with the following settings:
•f
CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, RC oscillator and Sub oscillator stopped
RC Sleep 2M RC Sleep mode current ICCSRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•f
CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, Main oscillator and Sub oscillator stopped
RC Sleep 100k RC Sleep mode current ICCSRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•f
CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
Mode name Details
MB96380 Series
FME-MB96380 rev 10 115
Sub Sleep Sub Sleep mode current ICCSSUB with the following settings:
•f
CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
PLL Timer 48 PLL Timer mode current ICCTPLL with the following settings:
•f
CLKS1 = fCLKS2 = 48MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
Main Timer Main Timer mode current ICCTMAIN with the following settings:
•f
CLKS1 = fCLKS2 = 4MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Sub oscillator stopped
RC Timer 2M RC Timer mode current ICCTRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•f
CLKS1 = fCLKS2 = 2MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k RC Timer mode current ICCTRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•f
CLKS1 = fCLKS2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
Sub Timer Sub Timer mode current ICCTSUB with the following settings:
•f
CLKS1 = fCLKS2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
Stop 1.8V Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B)
Stop 1.2V Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B)
Mode name Details
MB96380 Series
116 FME-MB96380 rev 10
MB96384/385 PLL Run and Sleep mode currents
MB96384/385 operation modes with medium currents
0
5
10
15
20
25
-60 -40 -20 0 20 40 60 80 100 120
Ta
[˚C]
Icc[mA]
PLL Sleep 24
PLL Sleep 56
PLL Sleep 48
PLL Run 24
PLL Run 56
PLL Run 48
0
0.5
1
1.5
2
2.5
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
RC Sleep 2M
Main Sleep
PLL Timer 48
RC Run 2M
Main Run
MB96380 Series
FME-MB96380 rev 10 117
MB96384/385 Low power mode currents
MB96F385 PLL Run and Sleep mode currents
0.01
0.1
1
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
Stop 1.2V
Stop 1.8V
RC Timer 100k
Sub Timer
Sub Sleep
Sub Run
RC Sleep 100k
RC Timer 2M
RC Run 100k
Main Timer
0
10
20
30
40
-60 -40 -20 0 20 40 60 80 100 120
Ta
[˚C]
Icc[mA]
PLL Sleep 24
PLL Sleep 40
PLL Run 24
PLL Run 40
MB96380 Series
118 FME-MB96380 rev 10
MB96F385 operation modes with medium currents
MB96F385 Low power mode currents
0
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
RC Sleep 2M
Main Sleep
PLL Timer 48
RC Run 2M
Main Run
0.001
0.01
0.1
1
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
Stop 1.2V
Stop 1.8V
RC Timer 100k
Sub Timer
Sub Sleep
Sub
RC Sleep 100k
RC Timer 2M
RC Run 100k
Main Timer
MB96380 Series
FME-MB96380 rev 10 119
MB96F386/F387 PLL Run and Sleep mode currents
MB96F386/F387 operation modes with medium currents
0
10
20
30
40
50
-60 -40 -20 0 20 40 60 80 100 120
Ta
[˚C]
Icc[mA]
PLL Sleep 24
PLL Sleep 56
PLL Sleep 36
PLL Run 24
PLL Run 56
PLL Run 36
0
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
RC Sleep 2M
Main Sleep
PLL Timer 48
RC Run 2M
Main Run
MB96380 Series
120 FME-MB96380 rev 10
MB96F386/F387 Low power mode currents
MB96F388/F389 PLL Run and Sleep mode currents
0.001
0.01
0.1
1
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
Stop 1.2V
Stop 1.8V
RC Timer 100k
Sub Timer
Sub Sleep
Sub Run
RC Sleep 100k
RC Timer 2M
RC Run 100k
Main Timer
0
10
20
30
40
-60 -40 -20 0 20 40 60 80 100 120
Ta
[˚C]
Icc[mA]
PLL Sleep 24
PLL Sleep 40
PLL Run 24
PLL Run 40
MB96380 Series
FME-MB96380 rev 10 121
MB96F388/F389 operation modes with medium currents
MB96F388/F389 Low power mode currents
0
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
RC Sleep 2M
Main Sleep
PLL Timer 48
RC Run 2M
Main Run
0.001
0.01
0.1
1
-60 -40 -20 0 20 40 60 80 100 120
Ta [˚C]
Icc[mA]
Stop 1.2V
Stop 1.8V
RC Timer 100k
Sub Timer
Sub Sleep
Sub Run
RC Sleep 100k
RC Timer 2M
RC Run 100k
Main Timer
MB96380 Series
122 FME-MB96380 rev 10
2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL
Run mode at different frequencies and Flash timing settings.
Measurement conditions:
•V
CC = AVCC = 5.0V
• Ta = 25˚C
•f
CLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram
•f
CLKS2 = fCLKS1
•f
CLKP1 = fCLKB
•f
CLKP2 = fCLKB/2
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram
• Main clock = 4MHz external clock
• Flash memory timing settings:
• MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB)
• MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB)
• MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB)
• MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB)
• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash wait states: 0.5
• 1 Flash wait states: 0.33
• 2 Flash wait states: 0.25
MB96F385 PLL Run mode currents
0
5
10
15
20
25
30
35
40
0 4 8 1216202428323640
CLKB/CLKP1 (MHz)
ICCPLL (mA)
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.9V)
: Specified in "DC characteristics"
MB96380 Series
FME-MB96380 rev 10 123
MB96F386/F387 PLL Run mode currents
MB96F388/F389 PLL Run mode currents
0
5
10
15
20
25
30
35
40
45
0 4 8 121620242832364044485256
CLKB/CLKP1 (MHz)
ICCPLL (mA)
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.9V)
: Specified in "DC characteristics"
0
5
10
15
20
25
30
35
40
45
0 4 8 1216202428323640
CLKB/CLKP1 (MHz)
ICCPLL (mA)
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.9V)
: Specified in "DC characteristics"
MB96380 Series
124 FME-MB96380 rev 10
■PACKAGE DIMENSION MB96(F)38x LQFP 120P
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
120-pin plastic LQFP Le ad pitch 0.50 mm
Package width ×
package length 16.0 × 16.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.88 g
Code
(Reference) P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
(FPT-120P-M21)
C
2002 FUJITSU LIMITED F120033S-c-4-4
130
60
31
90 61
120
91
SQ
18.00±0.20(.709±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002) M
0.08(.003)
INDEX
.006
–.001
+.002
–0.03
+0.05
0.145
"A"
0.08(.003)
LEAD No.
.059
–.004
+.008
–0.10
+0.20
1.50
Details of "A" part
(Mounting height)
0.60±0.15
(.024±.006) 0.25(.010)
(.004±.002)
0.10±0.05
(Stand off)
0~8˚
*
.630
–.004
+.016
–0.10
+0.40
16.00
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB96380 Series
FME-MB96380 rev 10 125
■ORDERING INFORMATION
Part number Flash/ROM Subclock Persistent
Low Volt-
age Reset Package
MB96384YSC PMC-GSE2 *1
ROM (128KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96384RSC PMC-GSE2 *1 No
MB96384YWC PMC-GSE2 *1 Yes Yes
MB96384RWC PMC-GSE2 *1 No
MB96385YSC PMC-GSE2 *1
ROM (160KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96385RSC PMC-GSE2 *1 No
MB96385YWC PMC-GSE2 *1 Yes Yes
MB96385RWC PMC-GSE2 *1 No
MB96F385YSB PMC-GSE2 *1
Flash A (160KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96F385RSB PMC-GSE2 *1 No
MB96F385YWB PMC-GSE2 *1 Yes Yes
MB96F385RWB PMC-GSE2 *1 No
MB96F386YSB PMC-GSE2
Flash A (288KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96F386RSB PMC-GSE2 No
MB96F386YWB PMC-GSE2 Yes Yes
MB96F386RWB PMC-GSE2 No
MB96F387YSB PMC-GSE2
Flash A (416KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96F387RSB PMC-GSE2 No
MB96F387YWB PMC-GSE2 Yes Yes
MB96F387RWB PMC-GSE2 No
MB96F386YSC PMC-GSE2 *1
Flash A (288KB)
No Yes
20 pin Plastic LQFP
(FPT-120P-M21)
MB96F386RSC PMC-GSE2 *1 No
MB96F386YWC PMC-GSE2 *1 Yes Yes
MB96F386RWC PMC-GSE2 *1 No
MB96F387YSC PMC-GSE2 *1
Flash A (416KB)
No Yes 120 pin Plastic LQFP
(FPT-120P-M21)
MB96F387RSC PMC-GSE2 *1 No
MB96F387YWC PMC-GSE2 *1 Yes Yes
MB96F387RWC PMC-GSE2 *1 No
MB96F388TSB PMC-GSE2 *1
Flash A (544KB)
Flash B (32KB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96F388HSB PMC-GSE2 *1 No
MB96F388TWB PMC-GSE2 *1 Yes Yes
MB96F388HWB PMC-GSE2 *1 No
MB96380 Series
126 FME-MB96380 rev 10
*1:Thesedevices are under developmentandspecificationispreliminary. These products under development may
change its specification without notice.
This datasheet is also valid for the following outdated devices:
MB96384YSB, MB96384RSB, MB96384YWB, MB96384RWB,
MB96385YSB, MB96385RSB, MB96385YWB, MB96385RWB,
MB96F385YSA, MB96F385RSA, MB96F385YWA, MB96F385RWA,
MB96F386YSA, MB96F386RSA, MB96F386YWA, MB96F386RWA,
MB96F387YSA, MB96F387RSA, MB96F387YWA, MB96F387RWA,
MB96F388TSA, MB96F388HSA, MB96F388TWA, MB96F388HWA,
MB96F389YSA, MB96F389RSA, MB96F389YWA, MB96F389RWA.
MB96F389YSB PMC-GSE2 *1
Flash A (544KB)
Flash B (288kB)
No Yes
120 pin Plastic LQFP
(FPT-120P-M21)
MB96F389RSB PMC-GSE2 *1 No
MB96F389YWB PMC-GSE2 *1 Yes Yes
MB96F389RWB PMC-GSE2 *1 No
MB96V300BRB-ES
(for evaluation) Emulated by ext. RAM Yes No 416 pin Plastic BGA
(BGA-416P-M02)
Part number Flash/ROM Subclock Persistent
Low Volt-
age Reset Package
MB96380 Series
FME-MB96380 rev 10 127
■REVISION HISTORY
Revision Date Modification
Prelim 1 2007-05-2 Creation
Prelim 2 2007-05-24 Electrical characteristics and memory description updates
Prelim 3 2007-08-09 Typo errors corrections, Flash memory programming interface update
Prelim 4 2007-08-31 Update of DC characteristics. new MB96F388 and MB96F389 added. LVD
chapter added as well as an example characteristics chapter
Prelim 5 2007-09-06 Updates of the DC characteristics, interrupt vector table update, update of the
LVD characteristics
Prelim 6 2007-11-14 Memory map for external bus modified. Modifications of the drawing of the pin
circuits. Electrical characteristics updates. Rephrasing and typos corrections.
Add Slew rate high current outputs chapter.
Modification of the block diagram.
Memory map modified for Flash. RAM memory map added.
Pin circuit type corrected. Type L IO is now included.
Prelim 7 2007-12-12 Memory IO map modified
New Flash/ROM configuration presentation
Ordering information: MB96300B used as reference.
Block diagram modified to included relocated pins.
Main Flash becomes Flash memory A and Satellite flash becomes Flash
memory B
MB96380 Series FME-MB96380 rev 10
Prelim 8 2008-02-04 • Devices under development added: MB96384/385/F385/F388/F389
• Block diagram corrected (existing resource pins)
• Pin assignment: TTG8 -> TTG7
• Pin function table corrected
• I/O circuit type diagrams corrected
• Memory map cleaned up
• "Flash sector configuration" replaced by corrected "User ROM Memory map for
Flash devices", “ROM configuration” replaced by “User ROM Memory map for
Mask ROM devices”
• IO map table regenerated:
- Port register: Naming style corrected
- Memory control registers renamed (Main/Sat -> A/B)
- addresses after 000BFFh removed
• Absolute maximum ratings: Pd and Ta specified more precisely
• Run and Sleep mode currents: more conditions added (1WS settings)
• Run mode current spec in 48/24MHz mode corrected
• Maximum CLKP2 frequency for MB96F386/F387 corrected
• High current port input capacitance added
• External bus timings: missing conditions added and readability improved
• Alarm comparator spec updated (transition voltages defined)
• MB96V300A removed
• Ordering information updated
• Typos and formatting corrected
Revision Date Modification
MB96380 Series
FME-MB96380 rev 10 129
9 2009-01-09 • Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly
style changes and official notes and disclaimer added)
• Numbering of Electrical Characteristics subchapters automated
• Note about devices under development modified
• I/O map: Note added about reserved addresses
• Serial programming interface: Note about handshaking pins improved
• ICCPLL for CLKS1/2=80MHz, CLKB=40MHz (F388/F389) increased by 5mA
• ICCSPLLforCLKS1/2=80MHz,CLKB=40MHz(F388/F389)increasedby0.8mA
(typ) and 1.3mA (max)
• Updated ordering information: MB96384/385**A -> MB96384/385**B
• Package code of MB96V300 corrected in ordering information
• Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max
50kOhm -> 65kOhm
• Run and Sleep mode currents of ROM devices (MB96384/385) reduced
• Added voltage condition to pull-up resistance and LCD divide resistance spec
• Lineup: Term “Data Flash” replaced by “independent 32KB Flash”
• Ordering information: column “Independent 32KB Data Flash” replaced by new
column “Flash/ROM”, column “Remarks” removed
• Official package dimension drawing with additional notes added
• Empty pages removed
• MB96384/385 and MB96F385/F388/F389 separated in DC spec and currents of
these devices adjusted according to first evaluation results
• Alarmcomparator:Powersupplycurrentmaxvaluesincreased,comparisontime
reduced, mode transition time and power-up stabilization time newly added
• Handling devices: Notes added about Serial communication and about using
ceramic resonators.
• Feature list and ACCharacteristics: 16MHzmaximumfrequency is validforcrys-
tal oscillators. For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
• “Preliminary” watermark removed
Revision Date Modification
MB96380 Series FME-MB96380 rev 10
10 2010-06-25 • AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg
• Note added that PLL phase jitter spec does not include jitter coming from Main
clock
• Alarm comparator: Maximum power-up stabilization time increased to 10ms
• Note added in DC characteristics how to select driving strength of ports
• I2CACspecupdated:tof,CbandtSPspecadded,wrongfootnotesandCondition
removed
• I/O Circuit type: Note added for type “N” (slew rate control according to I2C spec)
• Example characteristics updated, new figures added showing dependency of
PLL Run mode current on frequency
• Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new spec
items in PLL Run/Sleep mode, small adjustment of most other values)
• Package dimension: Added the following sentence under the figure: “Please
confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/”
• AD converter: Impact of input pin capacitance and external capacitance added
to formula for calculation of the sampling time
• Added specification of RC clock stabilization time
• Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’
• Feature description PPG: ‘Reload timer overflow as clock input’ corrected to
‘Reload timer underflow as clock input’
• Company name updated on the cover page: Fujitsu Microelectronics Limited ->
Fujitsu Semiconductor Limited
• Ordering information: MB96384/385**B -> MB96384/385**C, MB96F385/F388/
F389**A -> MB96F385/F388/F389**B, added devices under development
MB96F386**C and MB96F387**C
Revision Date Modification
MB96380 Series
FME-MB96380 rev 10 131
MB96380 Series
132 FME-MB96380 rev 10
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation,ordinaryindustrial use, general office use, personal use,andhousehold use, but are not designed, developedand manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
