AM28F256A-90FCB - Advanced Micro Devices

FINAL

Publicati on# 18879 Rev: CAmendment/+2

Issue Date: May 1998

Am28F256A

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

DISTINCTIVE CHARACTERISTICS

■High performan c e

— Access times as fast as 70 ns

■CMOS low power consumption

— 30 mA maximum activ e current

— 100 µA maximum standb y current

— No data retention power consumption

■Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

— 32-pin TSOP

■100,000 write/erase cycles minimum

■Write and erase voltage 12.0 V ±5%

■Latch-up protected to 100 mA from –1 V to

VCC +1 V

■Embedded Erase Electrical Bulk Chip-Erase

— 1.5 seconds typical chip-erase including

pre-programming

■Embedded Program

— 14 µs typical byte-program including time-out

— 0.5 second typical chip program

■Command register architecture fo r

micr oprocessor/microcontroller compati b le

write interface

■On-chip address and data latches

■Adv anced CMOS flash memory technology

— Low cost single transist or memory cell

■Embedded algorithms for completely

self-timed write/erase operations

GENERAL DESCRIPTION

The Am28F256A is a 256 K Flash memor y organized

as 32 Kbytes of 8 bits each. AMD’s Flash memories

offer the most cost-effective and reliable read/write

non- v olatile random acces s memory. The Am28 F256A

is packaged in 32-pin PDIP, PLCC, and TSOP versions.

It is designed to be reprogrammed and erased in-sys-

tem or in standard EPROM programmers. The

Am28F256A is erased when shipped from the factory.

The standard Am28F256A offers access times as fast

as 70 ns, allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the Am28F256A has separate chip enable (CE#)

and output enable (OE#) controls.

AMD’s Flash memories augment EPROM functionality

with in-circuit electrical erasure and prog ramming. The

Am28F256A uses a command register to manage this

functionality, while maintaining a standard JEDEC

Flash Standard 32-pin pinout. The command register

allows for 100% TTL level control inputs and fixed

pow er supply levels during erase and programming.

AMD’s Flash technology reliably stores memory con-

tents even after 100,000 erase and program cycles.

The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina-

tion of adv anced tunnel o xide processing and l ow inter-

nal electric fields for erase and programming

operations produces reliable cycling. The Am28F256A

uses a 12.0 V ±5% VPP high voltage input to perform

the erase and programming functions.

The highest degree of latch-up protection is achieved

with AMD’s proprietary non-epi process. Latch-up pro-

tection is provided for stresses up to 100 milliamps on

address and data pins from –1 V to VCC +1 V.

Embedded Program

The Am28F256A is byte programmable using the

Embedded Programming algorithm. The Embedded

Progr amming algorithm does not r equire t he system to

time-out or verify the data programmed. The typical

room temperature programming time of the

Am28F256A is one half second.

Embedded Erase

The entire chip is bulk erased using the Embedded

Erase algorithm. The Embedded Erase algorithm

automatically programs the entire arra y prior to electrical

erase. The timing and verification of electrical erase are

2 Am28F256A

controlled internal to the dev ice. Typical erasure at room

temperature is accomplished in 1.5 seconds, including

preprogramming.

AMD’s Am28F256A is entirely pin and software com-

patible with AMD’s Am28F020A, Am28F256A and

Am28F512A Flash memories.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine which

controls the erase and programming circuitry. During

write cycles, the command register internally latches

address and data needed for the programming and

erase operations. For system design simplification, the

Am28F256A is designed to support either WE# or CE#

controlled writes. During a system write cycle,

addresses are latched on the falling edge of WE# or

CE# whichev er occurs last. Data is latched on the rising

edge of WE# or CE# whichever occurs first. To simplify

the following discussion, the WE# pin is used as the

write cycle control pin throughout the rest of this text. All

setup and hold times are with respect to the WE# signal.

AMD’s Flash technology combines years of EPROM

and EEPROM e xperience to produce the highest le v els

of quality, reliability, and cost effectiveness. The

Am28F256A electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are

programmed one byte at a time using the EPROM

programming mechanism of hot electron injectio n.

Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms

Am28F256A with

Embedded Alg orit hm s Am28F256 using AMD Flashrite

and Flashe ras e Algo rith ms

Embedded

Programming

Algorithm vs.

Flashrite

Programming

Algorithm

AMD’s Embedded Programming algorithm

requires the user to only write a program

set-up command and a program command

(program data and address). The device

automatically times the programming

pulse width, verifies the programming, and

counts the number of sequences. A status

bit, Data# Polling, provides the user with

the programming operation status.

The Flashrite Programming algorithm requires the

user to write a program set-up command, a program

command, (program data and address), and a

program verify command, followed by a read and

compare operation. The user is required to time the

programming pulse width in order to issue the

program verify command. An integrated stop timer

prevents any possibility of overprogramming.

Upon completion of this sequence, the data is read

back from the device and compared by the user with

the data intended to be written; if there is not a

match, the sequence is repeated until there is a

match or the sequence has been repeated 25 times.

Embedded Era se

Algorithm vs.

Flashera se Era se

Algorithm

AMD’s Embedded Erase algorithm

requires the user to only write an erase set-

up command and erase command. The

device automatically pre-programs and

verifies the entire array. The device then

automatically times the erase pulse width,

verifies the erase operation, and counts

the number of sequences. A status bit,

Data# Polling, provides the user with the

erase operation status.

The Flasherase Erase algorithm requires the device

to be completely programmed prior to executing an

erase command.

To invoke the erase operation, the user writes an

erase set-up command, an erase command, and an

erase verify command. The user is required to time

the erase pulse width in order to issue the erase

verify command. An integrated stop timer prevents

any possibility of overerasure.

Upon completion of this sequence, the data is read

back from the device and compared by the user with

erased data. If there is not a match, the sequence is

repeated until there is a match or the sequence has

been repeated 1,000 times.

Am28F256A 3

BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Erase

Voltage

Switch

State

Control

Command

Voltage

Switch Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

18879C-1

A0–A14

OE#

CE#

WE#

VSS

VCC

To Array

DQ0–DQ7

Input/Output

Buffers

VPP

Address

Latch

Low VCC

Detector Program/Erase

Pulse Timer

Embedded

Algorithms

Data

Latch

Y-Gating

262,144

Bit

Cell Matr ix

Family Part Number Am28F256A

Speed Options (VCC = 5.0 V ±10%) -70 -90 -120 -150 -200

Max Access Time (ns) 70 90 120 150 200

CE# (E#) Access (ns) 70 90 120 150 200

OE# (G#) Access (ns) 35 35 50 55 55

4 Am28F256A

CONNECTION DIAGRAMS

Note: Pin 1 is marked for orientation.

VPP VCC

DQ0

A12 A14

16 18

DQ1

DQ2

VSS

WE# (W#)

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

DQ6

DQ5

DQ4

DQ3

18879C-2

PDIP

NC 131 30

13 17 18 19 2016

DQ0

A14

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

A12

VPP

VCC

WE# (W#)

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

PLCC

18879B-3

Am28F256A 5

CONNECTION DIAGRAMS (continued)

32-Pin — Standard Pinout

32-Pin — Reverse Pinout

LOGIC SYMBOL

A11

A13

A14

VCC

VPP

A12

OE#

A10

CE#

VSS

A11

A13

A14

WE#

VCC

VPP

A12

OE#

A10

CE#

VSS

15 18879C-4

A0–A14

CE# (E#)

OE# (G#)

WE# (W#)

18879C-5

DQ0–DQ7

6 Am28F256A

ORDERING INFORMATION

Standard Pr oducts

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm av ailability of specific valid combinations and

to check on newly released combinations.

DEVICE NUM BE R/ DES CR IPT IO N

Am28F25 6A

256 Kilobit (32 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms

AM28F256A -70 J C

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F256A-70

AM28F256A-90

AM28F256A-120

AM28F256A-150

AM28F256A-200

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Am28F256A 7

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches

hold addresses dur ing write cycles.

CE# (E#)

Chip Enab le activ e low input activ ates the chip’ s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0-DQ7

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Connect-corresponding pin is not connected

internally to the die.

OE# (G#)

Output Enab le acti ve low input gates the outp uts of the

device through the data buffers during memory read

cycles. Output Enable is high during command

sequencing and program/erase operations.

VCC

P ow er supply f or de vice operat ion. (5.0 V ± 5% or 10%)

VPP

Program voltage input. VPP must be at high voltage in

order to write to the command register. The command

ory array contents . Memory contents cannot be altered

when VPP ≤ VCC +2 V.

VSS

Ground.

WE# (W)

Write Enable active low input controls the write function

of the command register to the memory arra y . The t arget

address is latched on the falling ed ge of the Write En-

able pulse and the appropriate data is latched on the ris-

ing edge o f the pulse. Write Enable high inhibits wr iting

to the device.

8 Am28F256A

BASIC PRINCIPLES

This section contains descriptions about the device

read, erase, and program operations, and write opera-

tion status of the Am29FxxxA, 12.0 volt family of Flash

devices. References to some tables or figures may be

given in generic form, such as “Command Definitions

tabl e”, rather t han “Table 1”. Ref er to the corresponding

data sheet for the actual table or figure .

The Am28FxxxA family uses 100% TTL-level control

inputs to manage the command register. Erase and

reprogramming operations use a fixed 12.0 V ± 5%

high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a

read only memory and operates like a standard

EPROM. The control inputs still manage traditional

read, standb y, output disable, and Aut o select modes.

Command Register

The command register is enabled only when high volt-

age is applied to the VPP pin. The erase and repro-

gramming operations are only accessed via the

for erase and reprogramming operations. The tradi-

tional read, standby, output disable, and Auto select

modes are available via the register.

The de vice’ s command register is written using standard

microprocessor write timings. The register controls an

inter nal state machine that manages all device opera-

tions. F or system design simplification, the de vice is de-

signed to suppor t either WE# or CE# controll ed writes.

During a system write cycle, addresses are latched on

the falling edge of WE# or CE# whichever o ccurs last.

Data is latched on the rising edge of WE# or CE# which-

ever occur first. To simplify the following discussion, the

WE# pin is used as the write cycle control pin throughout

the rest of this text. All setup and hold times are with re-

spect to the WE# signal.

OVERVIEW OF ERASE/PROGRAM

OPERATIONS

Embedded Erase Algorithm

AMD now makes erasure extremely simple and reli-

abl e. The Embedded Eras e algorithm requires the user

to only write an erase setup command and erase com-

mand. The device will automatically pre-program and

verify the entire array. The device automatically times

the erase pulse width, provides the erase verify and

counts the number of sequences. A status bit, Data#

Polling, provides feedback to the user as to the status

of the erase operation.

Embedded Programming Algorithm

AMD now makes programming extremely simple and

reliable. The Embedded Programming algorithm re-

quires the user to only write a program setup command

and a program command. The device automatically

times the programming pulse width, provides the pro-

gram verify and counts the number of sequences. A

status bi t, Data# Polling, provides feedback to the user

as to the status of the programming operation.

DATA PROTECTION

The de vice is designed to of fer protect ion against ac ci-

dental erasure or programming caused by spurious

system lev el signals that ma y e xist during power t ransi-

tions. The de vice pow ers up in its read only state. Also ,

with its control register architecture, alteration of the

memory contents only occurs aft er succes sful comple-

tion of specific command sequences.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting from VCC

power-up and power -down tr ansition s or system noise.

Low VCC Write Inhibit

To av oid init iat ion of a write cycle during VCC power-up

and power-down, the device locks out write cycles for

VCC < VLKO (see DC characteristics section for volt-

ages). When VCC < VLKO, t he command regi ster is dis-

abled, all internal program/erase circuits are disabled,

and the dev ice resets to the read mode. The de v ic e ig-

nores all writes until VCC > VLKO. The user m ust ensure

that the control pins are in the correct logic state when

VCC > VLKO to prevent unintentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#

or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = VIL,

CE#=VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and

OE# = VIH will not accept commands on the rising

edge of WE# . The internal state machine is automati-

cally reset to the read mode on power-up.

Am28F256A 9

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1. Am28F256A Device Bus Operations (Notes 7 and 8)

Legend:

X = Don’t care, where Don’t Care is either VIL or VIH levels. V PPL = VPP

VCC + 2 V. See DC Characteristics for voltage levels

of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:

1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for

the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < VID < 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

4. Read operation with VPP = VPPH may access array data or the Auto select codes.

5. With VPP at high voltage, the standby current is ICC + IPP (standby).

6. Refer to Table 3 for valid DIN during a write operation.

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all

addresses except A9 and A0 must be held at VIL.

8. If VCC

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP

rise time and fall time specification of 500 ns minimum.

Operation CE#

(E#)OE#

(G#)WE#

(W#)VPP

(Note 1) A0 A9 I/O

Read-Only

Read VIL VIL XV

PPL A0 A9 DOUT

Standby VIH XXV

PPL X X HIGH Z

Output Disable VIL VIH VIH VPPL X X HIGH Z

Auto-select Manufacturer

Code (Note 2) VIL VIL VIH VPPL VIL VID

(Note 3) CODE

(01h)

Auto-select Device

Code (Note 2) VIL VIL VIH VPPL VIH VID

(Note 3) CODE

(2Fh)

Read/Write

Read VIL VIL VIH VPPH A0 A9 DOUT

(Note 4)

Standby (Note 5) VIH XXV

PPH X X HIGH Z

Output Disable VIL VIH VIH VPPH X X HIGH Z

Write VIL VIH VIL VPPH A0 A9 DIN

(Note 6)

10 Am28F256A

READ-ONLY MODE

When VPP is less than VCC + 2 V, the command register

is inactive. The device can either read array or autose-

lect data, or be standby mode.

Read

The de vice f unctions as a r ead only memory when VPP

< VCC + 2 V. The de vice has two control func tions. Both

must be satisfied in order to output data. CE# controls

power to the device. This pin should be used for spe-

cific device selection. OE# controls the device outputs

and should be used to gate data to the output pins if a

device is selected.

Address access time tACC is equal to the delay from

stable addresses to valid output data. The chip enable

access time tCE is the dela y from s table addresses and

stable CE# to valid data at the output pins. The output

enable access time is the dela y from the f alling edge of

OE# to valid data at the output pins (assuming the ad-

dresses have been stable at least tACC - tOE).

Standby Mode

The device has two standby modes. The CMOS

standby mode (CE# input held at VCC ± 0.5 V), con-

sumes less than 100 µA of current. TTL standby mode

(CE# is held at VIH) reduces the current requirements

to less than 1 mA. When in the standby mode the out-

puts are in a high impedance state, independent of the

OE# input.

If the device is deselected during erasure, program-

ming, or program/erase verification, the device will

dra w activ e current until the operation is terminated.

Output Disable

Output from the device is disabled when OE# is at a

logic high level. When disabled, output pins are in a

high impedance state.

Auto Select

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon recei pt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

The Auto select mode allows the reading out of a binary

code from the device that will identify its manufacturer and

type. This mode is intended for the pur pos e of autom ati-

cally matching the de vice to be programmed with its cor-

responding programming algorithm. This mode is

functional ov er the entire temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment

must force VID (11.5 V to 13.0 V) on address A9. Two

identifier b ytes may then be sequenced from the de vice

outputs by toggling address A0 from VIL to VIH. All other

address lines must be held at VIL, and VPP must be

less than or equal to VCC + 2.0 V while using this Auto

select mode. By te 0 (A0 = VIL) represents the manuf ac-

turer code and byte 1 (A0 = VIH) the device identifier

code. For the de vice the t wo bytes are given in t he table

2 of the device data sheet. All identifiers for manufac-

turer and device codes will exhibit odd parity with the

MSB (DQ7) defined as the parity bit.

Table 2. Am28F256A Auto Select Code

Type A0 Code

(HEX)

Manufacturer Code VIL 01

Device Code VIH 2F

Am28F256A 11
ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High volt age must be applied t o the VPP pin in order to
activate the  command register. Data written to the reg-
ister serves as input to t he internal state machine. The
output of the s tate machine determines the oper ational
function of the device.
The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE# and CE# to VIL, while OE#
is at VIH. Addresses are latched on the falling edge of
WE#, while data is latched on the rising edge of the
WE# pulse. Sta ndard mic roprocessor write timings are
used.
The device requi res the OE# pin to be VIH for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not  in the correct state a write
command will not be executed.
Refer to AC Wr ite Characteristics and the Erase/Pro-
gramming Wavefor ms for specific timing parameters.
Command Definitions 
The contents of the command register default to 00h
(Read Mode)  in the a bsence of hi gh v oltage applie d to
the VPP pin. The device operates as a read only
memory. High voltage on the VPP pin enables the
command register. Device operations are selected by
writing specif ic data  codes int o the command  register.
Tabl e 3 in the dev ice data sheet def ines these regis ter
commands.
Read Command
Memory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00h into the c ommand regist er. Standard microproc es-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP power-up . The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents  does not oc cur during the V PP power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing paramet ers.
Table 3. Am28F256A Command Definitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE
#
 pulse.
X = Don’t care.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE
#
.
4. Please reference Reset Command section.
Command
First Bus Cycle Second Bus Cycle
Operation 
(Note 1) Address 
(Note 2) Data 
(Note 3) Operatio n 
(Note 1) Address 
(Note 2) Data 
(Note 3)
Read Memory (Note 4) Write X 00h/FFh Read RA RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/2Fh
Embedded Erase Set-up/
Embedded Erase Write X 30h Write X 30h
Embedded Program Set-up/
Embedded Program Write X 10h or 50h Write PA PD
Reset (Note 4) Write X 00h/FFh Write X 00h/FFh

12 Am28F256A

FLASH MEMORY PROGRAM/ERASE

OPERATIONS

Embedded Erase Algorithm

The automatic chip erase does not require the device

to be entirely pre-programmed prior to executing the

Embedded set-up erase command and Embedded

erase command. Upon e x ec uting the Embedded er ase

command the device automatically will program and

verify the entire memory for an all zero data pattern.

The system is

not

required to provide any controls or

timing during these operations.

When the device is automatically verified to contain an

all zero pattern, a self-timed chip erase and verify be-

gin. The er ase and verify oper at ion are complete when

the data on DQ7 is “1" (see Write Operation Status sec-

tion) at which time the device returns to Read mode.

The system is not required to provide any control or

timing during these operations.

When using the E mbedd ed Erase algorithm, the erase

automatically terminates when adequate erase margin

has been achi eved for the memory arra y ( no erase v er-

ify command is required). The margin voltages are in-

ternally generated in the same manner as when the

standard erase verify command is used.

The Embedded Erase Set-Up command is a command

only operation that stages the device for automatic

electrical erasure of all bytes in the array. Embedded

Erase Setup is performed by writing 30h to the com-

mand register.

To commence automatic chip erase, t he command 30h

must be written again t o the command register . The au-

tomatic erase begins on the rising edge of the WE and

terminates when the data on DQ7 is “1" (see Write Op-

eration Status section) at which time the device ret urns

to Read mode.

Figure 1 and Tab l e 4 illustr ate t he Embedded Er ase al-

gorithm, a typical command string and bus operation.

Table 4. Embedded Erase Algorithm

Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL ma y be ground, no connect with a resistor tied to ground, or less than VCC + 2 .0 V. Ref er

to Functional Description.

Bus Operations Command Comments

Standby Wait for VPP Ramp to VPPH (see Note)

Write Embedded Erase Setup Command Data = 30h

Embedded Erase Command Data = 30h

Read Data# Polling to Verify Erasure

Standby Compare Output to FFh

Read Available for Read Operations

START

Apply VPPH

Erasure Completed

Data# Poll from Device

Write Embedded Erase Command

Write Embedded Erase Setup Command

18879C-6

Figure 1. Embedded Erase Algorithm

Am28F256A 13

Embedded Programming Algorithm

The Embedded Progr am Se tup i s a command only op-

eration that stages the device for automatic program-

ming. Embedded Program Setup is performed by

writing 10h or 50h to the command register.

Once the Embed ded Setup Prog r am ope r ation is per-

for med, the next WE# pulse causes a transition to an

activ e pro gr amming oper ation. Address es are lat ched

on the falling edge of CE# or WE# pulse, whichever

happens later. Data is latched on the rising edge of

WE# or CE# , whiche ver happ ens first. The rising e dge

of WE# also begins the programming operation. The

system is not required to provide further controls or

timings. The device wi ll automatically provide an ade-

quate internally generated program pulse and verify

margin. The automatic programming operation is

completed when the d ata on DQ7 is equi valent to dat a

written to th is bit (s ee Write Oper at io n Stat us s ecti on)

at which time the device returns to Read mode.

Figure 2 and Table 5 illustrate the Embedded Program

algorithm, a typical command string, and bus operation.

Table 5. Embedded Programming Algorithm

Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL ma y be ground, no connect with a resistor tied to ground, or less than VCC + 2 .0 V. Ref er

to Functional Description. Device is either powered-down, erase inhibit or program inhibit.

Bus Operations Command Comments

Standby Wait for VPP Ramp to VPPH (see Note)

Write Embedded Program Setup Command Data = 10h or 50h

Write Embedded Program Command Valid Address/Data

Read Data# Polling to Verify Completion

Read Available for Read Operations

START

Apply VPPH

Write Embedded Setup Program Command

Write Embedded Program Command (A/D)

Programming Completed

Yes

Data# Poll Device

Increme nt Add res s No

18879C-7

Figure 2. Embedded Programming Algorithm

Last Address

14 Am28F256A

Write Operation Status

Da ta Pollin g— D Q 7

The device features Data# Polling as a method to indi-

cate to the host system that the Embedded algorithms

are either in progress or completed.

While the Embedded Programming algorithm is in oper-

ation, an a ttemp t to read the device at a valid address

will produce the comple ment of expected Valid data on

DQ7. Upon completion of the Embedded Program algo-

rithm an attempt to read the device at a valid address will

produce V alid data on DQ7. The Data# P olling feature is

valid after the rising edge of the second WE# pulse of

the two write pulse sequence.

While the Embedded Erase algorithm is in operation,

DQ7 will read “0"

until the erase operation is com-

pleted. Upon completion of the erase operation, the

data on DQ7 will read “1.” The Data# Polling feature is

valid after the rising edge of the second WE# pulse of

the two Write pulse sequence .

The Data# Polling feature is only a ctive during Embed-

ded Programming or erase algorithms.

See Figures 3 and 4 for the Data# Polling timing spec-

ifications and diagrams. Data# Polling is the standard

method to check the write operation status, however,

an alternative method is available using Toggle Bit.

START

Fail

DQ7 = Data

DQ5 = 1

Pass

Yes

Read Byte

(DQ0–DQ7)

Addr = VA

Read Byte

(DQ0–DQ7)

Addr = VA

Yes

VA = Byte address for programming

= XXXXh during chip erase

18879C-8

Note:

DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 or after DQ5.

Figure 3. Data# Polling Algor ithm

Am28F256A 15

tCH

tOEH

tOE

tCE

tWHWH 3 or 4

DQ7# DQ7 =

Valid Data High Z

CE#

OE#

WE#

DQ7

tOH

tDF

DQ0–DQ 6 = InvalidDQ0–DQ 6 DQ0–DQ7

Valid Data

18879C-9

*DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 4. AC Waveforms for Data# Polling during Embedded Algorithm Operations

16 Am28F256A

Toggle Bit—DQ6

The dev ice also f eatures a “To ggle Bit” as a method to

indicate to the host system that the Embedded algo-

rithms are either in progress or completed.

Successive attempts to read data from the device at a

valid address, while the Embedded Program algorithm

is in progress, or at any address while the Embedded

Erase algorithm is in progress, will result in DQ6 tog-

gling between one and z ero. Once the Embedded Pro-

gram or Erase algorithm is completed, DQ6 will stop

toggling to indicate the c ompletion of eit her Embedded

operation. Only on the ne xt read cycl e will valid data be

obtained. The toggle bit is v alid after the rising edge of

the first WE# pulse of the two write pulse sequence, un-

like Data# Polling which is valid after the rising edge of

the second WE# pulse. This feature allows the user to

determine if the de vice is partially through t he two write

pulse sequence.

See Figures 5 and 6 for the Toggle Bit timing specif ica-

tions and diagrams.

START

Fail

DQ6 = Toggle

DQ5 = 1

Pass

Yes

Read Byte

(DQ0–DQ7)

Addr = VA

Read Byte

(DQ0–DQ7)

Addr = VA

Yes

DQ6 = Toggle

VA = Byte address for programming

= XXXXh during chip erase

18879C-10

Note:

DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

Figure 5. Toggle Bit Algorith m

Am28F256A 17

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has

exceeded the specified limits. This is a failure condi-

tion and the device may not be used again (internal

pulse count exceeded). Under these conditions DQ5

will produce a “1.” The pro gram or er ase cycle was not

successfully completed. Data# Polling is the only op-

eratin g function of the de vice under th is condition. The

CE# circuit will partially power down the device under

these conditions (to approximately 2 mA). The OE#

and WE# pins will control the output disable functions

as described in the Command Definitions table in the

corresponding device data sheet.

Parallel Device Erasure

The Embedded Erase algorithm greatly simplifies par-

allel dev ice erasure. Since th e erase process is internal

to the dev ic e, a single eras e command can be given to

multiple de vices concurrently. By implementing a paral-

lel erase algorithm, total erase ti me may be minimized.

Note that the Flash memories may erase at different

rates. If this is the case, when a device is completely

erased, us e a mask ing code to prev ent further erasure

(ov er-erasure). The other de vices will continue t o erase

until verified. The masking code applied could be the

read command (00h).

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power

supply sequencing is not required. Note that if VCC ≤

1.0 Volt, the voltage difference between VPP and VCC

should not exceed 10.0 Volts. Also, the device has a

rise VPP rise time and fall time specification of 500 ns

minimum.

Reset Command

The Reset command initializes the Flash memory de-

vice to the Read mode . In addition, it als o provides the

user with a safe method to abort any device operation

(including program or erase).

The Reset must be written two consecutive times after

the Setup Program command (10h or 50h). This will

reset the de vice to the Read mode.

Following any other Flash command, write the Reset

command once to the device. This wi ll safely abort any

prev ious operation and init ialize the device to t he Read

mode.

The Setup Program command (10h or 50h) is the only

command that requires a two-sequence reset cycle. The

first Reset command is interpreted as program data.

However , FFh data is considered as null data during pro-

gramming operations (memory cells are only pro-

grammed from a logical “1" to “0"). The second Reset

command safely aborts the programming operation and

resets the device to the Read mode.

Memory contents are not altered in an y c ase.

CE#

tOEH

WE#

OE#

Data

DQ0–DQ7 DQ6 = DQ6 = DQ6

Stop Toggling DQ0–DQ7

Valid

tOE

18879C-11

Note:

*DQ6 stops toggling (The device has completed the Embedded operation.)

Figure 6. AC Waveforms for Toggle Bit during Embedded Algor ith m Operati ons

18 Am28F256A

This detailed information is for your reference. It may

prove easier to always issue the Reset command two

consecutive times. This eliminates the need to deter-

mine if you are in the Setup Program state or not.

In-System Programming Considerations

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon rece ipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the circuit board.

Auto Select Command

AMD’s Flash memories are designed for use in appli-

cations where the local CPU alters memory contents.

In order to correctly program any Flash memories

in-system, manufacturer and device codes must be

accessible while the device resides in the target

system. PROM programmers typically access the sig-

nature c odes by rais ing A9 to a high v oltage . Howe v er ,

multiplexing high voltage onto address lines is not a

generally desired system design practice.

The device contains an A uto Select operation to supple-

ment traditional PROM programming methodologies.

The operation is ini tiated by wr iting 80h or 90h into the

command register. Following this command, a read

cycle address 0000h retrie v es the manufacturer code of

01h (AMD). A read cycle from address 0001h returns

the device cod e (see the Auto Select C ode table of the

corresponding device data sheet). To ter minate the op-

eration, it is necessar y to w r ite another valid command,

such as Reset (00h or FFh), into the register.

Am28F256A 19

ABSOLUTE MAXIMUM RATINGS

Storage Temperature. . . . . . . . . . . . –65°C to +150°C

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Voltage with Respect To Ground

All pins except A9 and VPP

(Note 1) . . . . . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

VPP (Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 2 00 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, inputs may overshoot VSS to –2.0 V for

periods of up to 20 ns. Maximum DC voltage on input and

I/O pins is VCC + 0.5 V. During voltage transitions, input

and I/O pins ma y ov ershoot to VCC + 2.0 V for periods up

to 20ns.

2. Minimum DC input voltage on A9 and VPP pins is –0.5 V.

During voltage transitions, A9 and VPP may overshoot

VSS to –2.0 V for periods of up to 20 ns. Maximum DC

input voltage on A9 and VPP is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shor ted to ground at a time.

Duration of the short circuit should no t be greater than

one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions abov e those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the de vice to absolute maximum rating conditions for

extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C

Industrial (I) De vices

Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +125°C

VCC Sup pl y Vo lt ages

VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

VPP Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 Am28F256A

MAXIMUM OVERSHOOT

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

18879C-12

Maximum Negative Input Overshoot

20 ns

VCC + 0.5 V

2.0 V

20 ns 20 ns

VCC + 2.0 V

18879C-13

Maximum Positive Input Overshoot

18879C-14

Maximum VPP Overshoot

20 ns

13.5 V

VCC + 0.5 V

20 ns 20 ns

14.0 V

Am28F256A 21

DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1-4)

TTL/NMOS Compatible

Notes:

1. Caution: The Am28F256A must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC

1.0

volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256A has a VPP rise time

and fall time specification of 500 ns minimum.

2. ICC1 is tested with OE# = VIH to simulate open outputs.

3. Maximum active power usage is the sum of ICC and IPP

4. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Max, CE# = VIH 0.2 1.0 mA

ICC1 VCC Active Read Curren t VCC = VCC Max, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE# = VIL

Programming in Progress (Note 4) 20 30 mA

ICC3 VCC Erase Curren t CE# = VIL

Erasure in Progress (Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

VPP = VPPL ±1.0

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA

VPPL VPP during Read-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC +2.0 V

VPPH VPP during Read/Write

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

22 Am28F256A

DC CHARACTERISTICS

CMOS Compatible

Notes:

1. Caution: The Am28F256A must not be removed from (or inserted into) a soc ket when VCC or VPP is applied. If VCC ð 1.0 volt,

the voltage diff erence between VPP and VCC should not e xceed 10.0 volts. Also, the Am28F256A has a VPP rise time and fall

time specification of 500 ns minimum.

2. ICC1 is tested with OE

= V IH to simulate ope n outputs.

3. Maximum active power usage is the sum of ICC and IPP

4. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Max, CE# = VCC ±0.5 V 15 100 µA

ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE# = VIL

Programming in Progress (Note 4) 20 30 mA

ICC3 VCC Erase Curren t CE# = VIL

Erasure in Progress (Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC –0. 4

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA

VPPL VPPL during Read-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC + 2.0 V

VPPH VPP during Read/Write

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

Am28F256A 23

TEST CONDITIONS

Table 6. Test Specifications

18879C-15

Figure 7. Am28F256A—Average ICC Active vs. Frequency

VCC = 5.5 V, Addressing Pattern = Minmax

Data Patter n = Checkerboard

ICC Active in mA

0123456789101112

Frequency in MHz

55°C

0°C

25°C

70°C

125°C

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

18879C-16

Figure 8. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition -70 A ll others Uni t

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times ≤10 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8, 2.0 V

24 Am28F256A

SWITCHING TEST WAVEFORMS

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics—Read Only Operation

Notes:

1. Guaranteed by design not tested.

2. Not 100% tested.

Parameter Symbo ls

Parameter Description

Am28F256A Speed Options

UnitJEDEC Standard -70 -90 -120 -150 -200

tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns

tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns

tAVQV tACC Address Access Time Max 70 90 120 150 200 ns

tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns

tELQX tLZ Chip Enable to Output in Low Z

(Note 2) Min00000ns

EHQZ tDF Chip Disable to Output in High Z

(Note 1) Max2020303535ns

GLQX tOLZ Output Enable to Output in Low Z

(Note 2) Min00000ns

GHQZ tDF Output Disable to Output in High Z

(Note 2) Max2020303535ns

AXQX tOH Output Hold from first of Address,

CE#, or OE# Change (Note 2) Min00000ns

VCS VCC Setup Time to Valid Read

(Note 2) Min 50 50 50 50 50 µs

18879C-17

3 V

0 V Input Output

1.5 V 1.5 V

Test Points

AC Testing for -70 devices: Inputs are driven at 3.0 V for a

logic “1” and 0 V for a logic “0”. Input pulse rise and fall time

are

≤

10 ns.

2.4 V

0.45 V Input Output

Test Points

2.0 V 2.0 V

0.8 V

AC Testing (all speed options e xcept -70): Inputs are driven at

2.4 V for a logic “1” and 0.45 V f or a logic “0”. Input pulse rise

and fall times are

≤

10 ns.

Am28F256A 25

AC Characteristics—Write/Erase/Program Operations

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded erase operation of 5 sec consists of 4 sec arra y pre-programming time and 1 sec array erase time. This is a typical

time for one embedded erase operation.

4. Not 100% tested.

Parameter Symbo ls

Parameter Description

Am28F256A Speed Options

UnitJEDEC Standard -70 -90 -120 -150 -200

tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns

tAVWL tAS Address Setup Time Min00000ns

WLAX tAH Address Hold Time Min 45 45 50 60 75 ns

tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns

tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns

tOEH Output Enable Hold Time for

Embedded Algorithm only Min 10 10 10 10 10 ns

tGHWL Read Recovery Time before WriteMin00000µs

tELWLE tCSE Chip Enable Embedded Algorithm

Setup Time Min 20 20 20 20 20 ns

tWHEH tCH Chip Enable Hold Time Min00000ns

WLWH tWP Write Pulse Width Min 45 45 50 60 60 ns

tWHWL tWPH Write Pulse Width HIGH Min 20 20 20 20 20 ns

tWHWH3 Embedded Programming Operation

(Note 2) Min 14 14 14 14 14 µs

tWHWH4 Embedded Erase Operation (Note3)Typ55555sec

VPEL VPP Setup Time to Chip Enable LO W

(Note 4) Min 100 100 100 100 100 ns

tVCS VCC Setup Time to Chip Enable LOW

(Note 4) Min 50 50 50 50 50 µs

tVPPR VPP Rise Time 90% VPPH (Note 4) Min 500 500 500 500 500 ns

tVPPF VPP Fall Time 90% VPPL (Note 4) Min 500 500 500 500 500 ns

tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

26 Am28F256A

KEY TO SWITCHING WAVEFORMS

SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Addresses

CE#

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

Power-up, Standby Device and

Address Sel ecti on Outputs

Enabled Data

Valid Standby, Power-down

Addresses Stable

High Z High Z

tWHGL

tAVQV (tACC)

tEHQZ

(tDF)

tGHQZ

(tDF)

tELQX (tLZ)

tGLQX (tOLZ)

tELQV (tCE)

tGLQV (tOE)

tAXQX (tOH)

Output Valid

tAVAV (tRC)

tVCS

18879C-18

Figure 9. AC Waveforms for Read Operations

Am28F256A 27

SWITCHING WAVEFORMS

tWC

DQ7#30h

tRC

Data# Polling Read

tDF

tOH

tCE

tOE

tDS

tCSE tWPH tDH

tWP

tGHWL

tWHWH3 OR 4

Addresses

CE#

OE#

WE#

Data

VCC

VPP

Embedded

Erase Setup Embedded

Erase Erase Standby

30h

tAH

tAS

tVCS

tVPEL

DQ7#

18879C-19

Note:

DQ7# is the complement of the data written to the device.

Figure 10. AC Waveforms for Embedded Erase Operation

28 Am28F256A

SWITCHING WAVEFORMS

tWC

tDS

DQ7#DIN

tAS

tAH

tRC

Data# Polling Read

tDF

tOH

tCE

tOE

tWPH

tDH

tWP

tGHWL

Embedded

Program Setup Embedded

Program

tCSE

tWHWH3 OR 4

50h

tVCS

tVPEL

DQ7# DOUT

18879C-20

Notes:

DIN is data input to the device.

DQ7

is the complement of the data written to the device.

DOUT is the data written to the device.

Figure 11. AC Waveforms for Embedded Programmi ng Operation

Addresses

CE#

OE#

WE#

Data

VCC

VPP

Am28F256A 29

AC CHARACTERISTICS—WRITE/ERASE/PROGRAM OPERATIONS

Alternate CE# Controlled Writes

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a

typical time for one embedded erase operation.

4. Not 100% tested.

Parameter Symbols

Parameter Descr ipti on

Am28F256A Speed Options

UnitJEDEC Standard -70 -90 -120 -150 -200

tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns

tAVEL tAS Addre ss Set up Tim e M in 0 0 0 0 0 ns

tELAX tAH Address Hold Time Min 45 45 50 60 75 ns

tDVEH tDS Data Setup Time Min 45 45 50 50 50 ns

tEHDX tgData Hold Time Min 10 10 10 10 10 ns

tOEH Output Enable Hold Time for

Embedded Algorithm only Min1010101010ns

GHEL Read Recovery Time Before Write Min 0 0 0 0 0 µs

tWLEL tWS WE# Setup Time by CE#Min00000ns

EHWK tWH WE# Hold Time Min 0 0 0 0 0 ns

tELEH tCP Write Pul se Wid th Min 65 65 70 80 80 ns

tEHEL tCPH Write Pul s e Wid th HIG H Min 20 20 20 20 20 ns

tEHEH3 Embedded Programming Operation

(Note 2) Min1414141414µs

EHEH4 Embedded Erase Operation (Note 3) Typ 5 5 5 5 5 sec

tVPEL VPP Setup Time to Chip Enable LOW

(Note 4) Min 100 100 100 100 100 ns

tVCS VCC Setup Time to Chip Enable LOW

(Note 4) Min5050505050µs

VPPR VPP Rise Time 90% VPPH (Note 4) Min 500 500 500 500 500 ns

tVPPF VPP Fall Time 90% VPPL (Note 4) Min 500 500 500 500 500 ns

tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

30 Am28F256A

SWITCHING WAVEFORMS

tVPEL

tWC

Data# Polling

DQ7#DIN

50h

tAS

tAH

tGHEL

tDH

tCPH tEHEH3 OR 4

tWS

tDS

tCP

Embedded

Program Setup Embedded

Program

DOUT

DQ7#

18879C-21

Notes:

1. DIN is data input to the device.

2. DQ7# is complement of the data written to the device.

3. DOUT is the data written to the device.

Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes

Addresses

WE#

OE#

CE#

Data

VCC

VPP

Am28F256A 31

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. 25°C, 12 V VPP

2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which

allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is

significantly less than the actual device limit.

3. Typical worst case = 84 µs. DQ5 = “1” only after a byte takes longer than 96 ms to program.

LATCHUP CHARACTERISTICS

PIN CAPACITANCE

Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

CommentsMin Typ

(Note 1) Max

(Note 2) Unit

Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure

Chip Programming Time 0.5 12.5 sec Excludes system-level overhead

Write/E rase Cyc les 100,000 Cycles

Byte Programming Time 14 µs

(Note 3) ms

Parameter Min Max

Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V

Current –100 mA +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

Parameter

Symbol Parameter Descriptio n Test Conditio ns Typ Max Unit

CIN Input Capacitance VIN = 0 8 10 pF

COUT Output Capacitance VOUT = 0 8 12 pF

CIN2 VPP Input Capacitance VPP = 0 8 12 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Ret ent ion Time 150°C 10 Years

125°C 20 Years

32 Am28F256A

PH YS ICAL DIMENSIONS

PD032—32-Pin Plastic DIP (measured in inches)

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.670

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .016

.022

SEATING PLANE

.015

.060

16-038-S_AG

PD 032

EC75

5-28-97 lv

32 17

16 .630

.700

0°

10°

.600

.625

.009

.015

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530

Am28F256A 33

PH YS ICAL DIMENSIONS

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

Pin 1 I.D.

18.30

18.50

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TS 032

DA95

3-25-97 lv

19.80

20.20

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

34 Am28F256A

PH YS ICAL DIMENSIONS

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TSR032

DA95

3-25-97 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

Am28F256A 35

DATA SHEET REVISION SUMMARY FOR

AM28F256A

Deleted -75, -95, and -250 sp eed options. Matched f or-

matting to other current data sheets.

Revision C+1

Programming In A PROM Programmer:

Deleted the paragraph “(Refer to the AUTO SELECT

paragraph in the ERASE, PROGRAM, and READ

MODE section for progr ammi ng the Flash memory de-

vice in-system).”

Revision C+2

Product Selector Guide

Corrected maxim um access time for -200 to 200 ns.

Erase and Programming Performance

Chip Programming Time—Typical:

Changed value

from 2 to 0.5 sec.

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.