stems CORPORATION Hybrid Sy HS 3120 Double Buffered 12-Bit MDAC FEATURES Monolithic Construction 12 Bit Resolution 0.01% Non-Linearity UP Compatible 4-Quadrant Multiplication Latch-up Protected DESCRIPTION The HS 3120 is a precision monolithic 12-bit multiplying DAC with internal two-stage input storage registers for easy interfacing with microprocessor busses. It is packaged in a 28-pin DIP to give high I/O design flexibility. DOUBLE BUFFERED ~ The input registers are sectioned into 3 segments of 4 bits each, all individually addressable. The DAC-register, following the input registers, is a parallel 12-bit register for holding the DAC data while the input registers are updated. Only the data held in the DAC register determines the analog output value of the converter. MICRO PROCESSOR COMPATIBLE The HS 3120 has been designed for great flexibility in connecting to bus- oriented systems. The 12 data inputs are organized into 3 independent addressable 4-bit input registers such that the HS 3120 can be connected to either a 4, 8 or 16-bit data bus. The control logic of the HS 3120 includes chip enable and latch enable inputs for flexible memory mapping. All FUNCTIONAL DIAGRAM controls are level-triggered to allow static or dynamic operation. VERSATILE OUTPUTS A total of 5 output lines are pro- vided by the HS 3120 to allow unipolar and bipolar output connection with a minimum of external components. The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. MONOLITHIC CMOS CONSTRUCTION The HS 3120 is a one-chip CMOS circuit with a resistor ladder network de- signed for 0.01% linearity without laser trimming. Small chip size and high manufacturing yields result in greatly reduced cost. (MSB) (LSB) BIT1 2 3 4 5 6 7 8 9 10 11 BIT12 VReEF 9 9] 10) 11] 12 13| 14{ 15 rel 17 rel rol 20 4 cEO r INPUT REGISTER }] INPUT REGISTER |- INPUT REGISTER 25 HBE O- CONTROL 24 LoGic MBE O R 5 23 O FB, LBEO \ Loaco-2! _ ~ tor DAC REGISTER 12 BIT MDAC > 7 O Io2 ___o FR, R/2 R/2 3 _ FB3 |? Vpo1 & Vpp2 b? GND iy GND LDTR 117SPECIFICATIONS (Typical @ 25C, nominal power supply, V = +10V, unipolar unless otherwise noted). REF MODEL HS 3120-2 HS 3120-0 TYPE MULTIPLYING, DOUBLE BUFFERED INPUTS * DIGITAL INPUT Resolution 12-Bits * 2-Quad. Unipolar Coding Binary, Comp. Binary! * 4-Quad. Bipolar Coding Offset Binary * Logic Compatibility2 CMOS, TTL * Input Current +1 A (max) * Data Set-up Time3 250nS (min) * Strobe Width? 250nS (min) * Data Hold Time OnS (min) * REFERENCE INPUT Voltage Range +25V (max) * Input Impedance Bk2 +50% * ANALOG OUTPUT Scale Factor 125uA/V Re +50% * cale Factor Accuracy +1% F.S.R. * Output Leakage @ 25C <10nA (max) * @ 125C <200nA (max) * Output Capacitance Court 1, all inputs high 80pF * CouT 1, all inputs low 40pF * COUT 2, all inputs high 40pF * Cour 2, all inputs low 80eF * STATIC PERFORMANCE Integral Linearity Differential Linearity Monotonicity Monotonicity Temp. Range C-Models B-Models DYNAMIC PERFORMANCE 0.015% F.S.R. (max) +0.024% F.S.R. (max) Guaranteed to 12 bits 0C to +70C -55C to +125C +0.05 % F.S.R. (max) +0.097% F.S.R. (max) Guaranteed to 10 bits * * Digital Small Signal Settling 1.Ousec * Full Scale Transition Settling to 0.01% (strobed) 2.Ousec * Reference Feedthrough Error (VRef = 20Vpp) @ 1kHz <1mvVv * @ 10kHz 2mvV * Delay to output from Bits input 100ns6 * from LDAC 200ns6 * from CE 120ns6 * STABILITY (Over Specified Temp. Range) Scale Factor4 2 ppm F.S.R./C (max) * Integral Linearity 4 ppm F.S.R./C (max) * Differential Linearity 1 ppm F,S.R./C (max) * Monotonicity Temp. Range C-Option 0C to +70C * B-Option -55C to +125C * POWER SUPPLY (Vpp) Operating Voltage (specifications guaranteed) +15V +5% * Maximum Voltage Range +5V to 16V * Current 2.5mA (max) * Rejection Ratio 0.002%/% (max) * TEMPERATURE RANGE Operating C-Option 0C to +70C * ~55C to +125C * Operating B-Option Storage ~65C to +150C * MECHANICAL Case Style 28-pin double DIP * C-Option plastic * B-Option ceramic * NOTES: Same as HS 3120-2 "0" <O.8V, 2.4V <""1" <Vp every 10C temperature increase. MSO Na+ 118 The input coding is comptementary binary if IQ is used. Digital input voltage must not exceed supply voltage or go below -0.5V. All strobes are level triggered. See TIMING DIAGRAM. Using the internal feedback resistor and an external opamp. The output leakage current wilt create an offset voltage at the external opamps output. It doubles Delay times are twice the amount shown at Ta = +125CPIN ASSIGNMENTS APPLICATIONS INFORMATION PIN FUNCTION : . : . - - Connection Diagram, Unipolar Operation 1 FBy, Feedback Bipolar Operation VaEF HBV 2 LDTR, Ladder Termination | [Voos [voo1 3 FB3, Feedback Bipolar Operation 4 VREF. Reference Voltage Input o FBy Ros 5 FB, Feedback, Unipolar/Bipolar lo1 ay 6 1091. Current out into virtual ground 7 To2, Current out-complement of Ig4 INPUTS. HS 3120 [LoTR > Vout 8 Vss, Ground, Analog and DAC Register FB4 L 9 Bit 1, MSB 1 FB3 ~ 10 Bit 2 | 102 11 Bit 3 12 Bit 4 crOJ Veg 1Vsg1 13 Bit 5 HBE O- 14 Bit 6 MBE O- L > 15 Bit 7 LBEO-~ = 16 Bit 8 LDAC O 17 Bit 9 Connection Diagram, Bipolar Operation 18 Bit 10 VREF +15V 19 Bit 11 | Voo2 | vpp1 20 Bit 12 21 LDAC, Transfers data from input to DAC register oC FB, Rost 22 CE, Chip Enable, active low 1 ~ 23 LBE, Bit 12 to Bit 9 Enable oraraL > 0 24 MBE, Bit 8 to Bit 5 Enable inputs | HS 3120 Vout 25 HBE, Bit 4 to Bit 1 Enable I 26 Vpp2. Supply Analog and DAC Register 27 Vgs1, Ground input latches 4 28 Vpp1. Supply input latches NOTE: Pins 8 and 27 and pins 26 and 28 must be connected co! Vss externally. HBE O--" MECHANICAL MBEO___ 5 | = We Lee C = VouT 1 0.1 LbDAC O_ 2.54) | PIN1 Ay, Aa, LF411ACN Connection Diagram, Bipolar Operation (for applications where bipolar offset temperature drift (~ 10 ppm/C) is not critical) NOTE: To maintain specified linearity, external amplifiers must be zeroed. This is best done with Vp_F set to zero and, 135.56) Unipolar: toad the DAC register with all bits at zero and adjust Ros for VouT = OV Bipolar: load the DAC register with 10. . .0 {MSB =1) and set Rosa for VouT 1 = OV. Then set Rasy for (33. 0,05 TRANSFER FUNCTION (N=12) (1.27) TYP BINARY INPUT | UNIPOLAR OUTPUT] BIPOLAR OUTPUT 4 114...114 -Vper (1- 27N) -Vper (1-2-(N-1)) | _ f 100... 001 -Vrer (1/2+2-N) | -Vper (2 -(N- 1)) 9.17 0.05 0.610 (4.3) + 116-49) , 100... 000 VREF 0 i) 4 o11...111 ~VREF (1/2- 2-N) VREF (2-(N - 1)) DIMENSIONS A 0.006 000...000 0 VREF inch 0.85_ (0.152) (2.16) 0.01. (mm {9,257 YP CONNECTIONS Unipolar Operation: Connect Ig 1 and FB as shown in diagram. Tie Tog (Pin 7), FBg (Pin 3), FBg, (Pin 1) all to Ground (Pin 8) Bipolar Operation: Connect 194, Io2, FB1, FB3, FBq as shown in diagram. Tie LDTR to Ig Grounding: Connect all GRD to system analog ground and tie this to digital ground. NOTE: All unused input pins must be grounded. 119BIPOLAR OFFSET ADJUST (external) -15V +15V 20k | AAA VV 4m ADJUSTMENT RANGE 0.2% TO 101 NOTE: External opamps have to be zeroed before the bipolar offset adjust circuit is connected. CONTROL LOGIC cE HBE TO INPUT REGISTER BIT 1- BIT 4 MBE TO INPUT REGISTER BIT 5- BIT 8 LBE TO INPUT REGISTER BIT 9 - BIT 12 LDAC O___ _ TO DAC REGISTER NOTE: The transfer from input register to DAC register can be performed without Enabling Chip. STROBE LOGIC Strobe Function 0 data latched (held) 1 data changing (transfer) TIMING DIAGRAM INPUT DATA <tet LIT L LBE fi | mBe Tl te Ke HBE LDAC | >| ty I | OUTPUT ly alts TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. ty: Data Setup Time. Time data must be stable before strobe (byte enable/LDAC) goes to 0, ty (min) = 250 nsec. tg: Strobe Width. tz (min) = 250 nsec. (CE, LBE, MBE, HBE, LDAC). tg: Hold Time. Time data must be stable after strobe goes to 0", tg = O nsec. tg: Delay from LDAC to Output. tg = 200 nsec. NOTE: Minimum common active time for CE and any byte enable is 250 nsec. 120 HIGH RELIABILITY PROCESSING Hybrid Systems maintains a continuing product assurance program to provide the highest levels of reliability demanded by MIL-specifications. Whether for government, aerospace or critical industrial applications, Hybrid Systems continues to be in a position of leadership in the development and manufacture of hybrid microelectronics data conversion products. Facilities include the most advanced manufacturing, test and calibration equipment available, supported by Class 100 clean areas for maximum environmental control during critical assembly and inspection processes. Hybrid Systems, through its emphasis on product quality assurance and its reliability, is a proven, experienced source of converter and resistor products. SCREENING TESTS PERFORMED PER MIL-STD-883 Process MIL-STD-883 Test Requirement Test Method Condition Pre-cap Visual 2017 - 100% Stabilization Bake 1008 Cc 100% Temperature Cycling 1010 Cc 100% Constant Acceleration 2001 B 100% Seal, Fine 1014 A 100% Seal, Gross 1014 Cc 100% Burn-in 1015 B 100% Final Electrical Test = ------ - 100% PRODUCT SCREENING AND QUALIFICATION Hybrid Systems is equipped to perform qualification and quality conformance testing of its products to the Level B re- quirements of MIL-STD-883 Rev. C. Processing to applicable Level S requirements is available where the higher confi- dence level is required. ORDERING INFORMATION MODEL DESCRIPTION HS 3120C-0 Double Buffered 12-Bit MDAC, Commercial HS 3120C-2 Double Buffered 12-Bit MDAC, Commercial HS 3120B-0 Double Buffered 12-Bit MDAC, MIL-STD-883 HS 3120B-2 Double Buffered 12-Bit MDAC, MIL-STD-883 CAUTION: ESD (Electro-Static Discharge) sensitive de- vice. Permanent damage may occur when unconnected devices are subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Protective foam should be discharged to the destin- ation socket before devices are removed. Devices should be handled at static safe workstations only. Unused dig- ital inputs must be grounded or tied to the logic supply voltage. Unless otherwise noted, the supply voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below -0.5 volts. If this condition cannot be maintained, limit input current on digital in- puts by using series resistors or contact Hybrid Systems for technical assistance. Specifications subject to change without notice.