1
Data sheet acquired from Harris Semiconductor
SCHS155C
Features
• Buffered Inputs
• Asynchronous Master Reset
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC164 and ’HCT164 are 8-bit serial-in parallel-out shift
registers with asynchronous reset. Data is shifted on the
positive edge of Clock (CP). A LOW on the Master Reset
(MR) pin resets the shift register and all outputs go to the
LOW state regardless of the input conditions. Two Serial
Data inputs (DS1 and DS2) are provided, either one can be
used as a Data Enable control.
Pinout
CD54HC164, CD54HCT164
(CERDIP)
CD74HC164, CD74HCT164
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC164F3A -55 to 125 14 Ld CERDIP
CD54HCT164F3A -55 to 125 14 Ld CERDIP
CD74HC164E -55 to 125 14 Ld PDIP
CD74HC164M -55 to 125 14 Ld SOIC
CD74HC164MT -55 to 125 14 Ld SOIC
CD74HC164M96 -55 to 125 14 Ld SOIC
CD74HCT164E -55 to 125 14 Ld PDIP
CD74HCT164M -55 to 125 14 Ld SOIC
CD74HCT164MT -55 to 125 14 Ld SOIC
CD74HCT164M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
DS1
DS2
Q0
Q1
Q2
Q3
GND
VCC
Q7
Q6
Q5
Q4
MR
CP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
October 1997 - Revised August 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC164, CD74HC164,
CD54HCT164, CD74HCT164
High-Speed CMOS Logic
8-Bit Serial-In/Parallel-Out Shift Register
[
/Title
(
CD74
H
C164
,
C
D74
H
CT16
4
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
8
-Bit
S
erial-
I
n/Par-
a
llel-
2
Functional Diagram
TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
MR CP DS1 DS2 Q0Q1 - Q7
RESET (CLEAR) L X X X L L - L
Shift H ↑llL q
0 - q6
H↑lhL q
0 - q6
H↑hlL q
0 - q6
H↑hhH q
0 - q6
H= High Voltage Level.
h= High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition.
l= Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition.
L= Low Voltage Level.
X= Don’t Care.
↑= Transition from Low to High Level.
qn= Lower Case Letters Indicate The State Of the Ref erence Input Cloc k Transition.
3
4
5
6
11
13
12
10
1
DS1 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
MR 98
2
DS2
GND = 7
VCC = 14
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
4
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
Date Shift-In (1, 2) 0.3
MR 0.9
Clock 0.7
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Function
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
HC TYPES
Maximum Clock Frequency fMAX 26-5-4-MHz
4.5 30 - 24 - 20 - MHz
6 35 - 28 - 24 - MHz
MR Pulse Width tw260-75-90-ns
4.5 12 - 15 - 18 - ns
610-13-15-ns
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
5
CP Pulse Width tW2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
Set-up Time tSU 260-75-90-ns
4.5 12 - 15 - 18 - ns
610-13-15-ns
Hold Time tH24-4-4-ns
4.54-4-4-ns
64-4-4-ns
MR to Clock,
Removal Time tREM 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
HCT TYPES
Maximum Clock Frequency fMAX 4.5 27 - 22 - 18 - MHz
MR Pulse Width tw618-23-27-ns
CP Pulse Width tw4.5 18 - 23 - 27 - ns
Set-up Time tSU 612-15-18-ns
Hold Time tH4.54-4-4-ns
MR to Clock,
Removal Time tREM 616-20-24-ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
HC TYPES
Propagation Delay,
CP to QntPLH, tPHL CL= 50pF 2 - 170 212 255 ns
4.5 - 34 43 51 ns
CL= 15pF 5 14 - - - ns
CL= 50pF 6 - 29 36 43 ns
MR to QntPLH, tPHL CL= 50pF 2 - 140 175 210 ns
4.5 - 28 35 42 ns
CL= 15pF 5 11 - - - ns
CL= 50pF 6 - 24 30 36 ns
Output Transition Times tTLH, tTHL CL= 50pF 2 - 75 - 110 ns
4.5 - 15 - 22 ns
6 - 13 - 19 ns
Maximum Clock Frequency fMAX CL= 15pF 5 60 - - - MHz
Input Capacitance CIN ---1010 10pF
Prerequisite For Switching Function (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
6
Power Dissipation
Capacitance
(Notes 3, 4)
CPD - 5 47 - - - pF
HCT TYPES
Propagation Delay,
CP to QntPLH, tPHL CL= 50pF 4.5 - 36 45 54 ns
CL= 15pF 5 15 - - - ns
MR to QntPLH, tPHL CL= 50pF 4.5 - 38 46 57 ns
CL= 15pF 5 16 - - - ns
Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns
Input Capacitance CIN ---- - -pF
Maximum Clock Frequency fMAX CL= 15pF - 54 - - - MHz
Power Dissipation
Capacitance
(Notes 3, 4)
CPD - 5 49 10 10 10 pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per device.
4. PD=V
CC2fi+∑(CLVCC2+f
O) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
Test Circuits and Waveforms
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54HC164, CD74HC164, CD54HCT164, CD74HCT164
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8970401CA ACTIVE CDIP J 14 1 TBD Call TI Call TI
CD54HC164F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD54HC164F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD54HCT164F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD74HC164E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC164EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC164M ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164M96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164M96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164M96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164ME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164MG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164MT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164MTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC164MTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT164EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT164M ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164M96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164M96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HCT164M96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164ME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164MG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164MT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164MTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT164MTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF CD54HC164, CD54HCT164, CD74HC164, CD74HCT164 :
•Catalog: CD74HC164, CD74HCT164
•Military: CD54HC164, CD54HCT164
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC164M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC164MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT164M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT164MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC164M96 SOIC D 14 2500 346.0 346.0 33.0
CD74HC164MT SOIC D 14 250 346.0 346.0 33.0
CD74HCT164M96 SOIC D 14 2500 346.0 346.0 33.0
CD74HCT164MT SOIC D 14 250 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2010
Pack Materials-Page 2
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