DT28F160S3-110 - Intel - Product.Network

E PRELIMINARY

December 1998 Order Number: 290608-005

Two 32-Byte Write Buffers



2.7 µs per Byte Effective

Programming Time

Low Voltage Operation



2.7 V or 3.3 V VCC



2.7 V, 3.3 V or 5 V VPP

100 ns Read Access Time (16 Mbit)

110 ns Read Access Time (32 Mbit)

High-Density Symmetrically-Blocked

Architecture



32 64-Kbyte Erase Blocks (16 Mbit)



64 64-Kbyte Erase Blocks (32 Mbit)

System Performance Enhancements



STS Status Output

Industry-Standard Packaging



SSOP, and TSOP (16 Mbit)

Cross-Compatible Command Support



Intel Standard Command Set



Common Flash Interface (CFI)



Scaleable Command Set (SCS)

Block Erase Cycles



100,000 at 0 °C to +70 °C

(Commercial)



10,000 at –40 °C to +85 °C

(Extended)

Enhanced Data Protection Features



Absolute Protection with VPP = GND



Flexible Block Locking



Block Erase/Program Lockout

during Power Transitions

Configurable x8 or x16 I/O

Automation Suspend Options



Program Suspend to Read



Block Erase Suspend to Program



Block Erase Suspend to Read

ETOX™ V Nonvolatile Flash

Technology

The Intel® 3 Volt FlashFile™ memory provides high-density, low-cost, nonvolatile, read/write storage

soluti ons for a wide range of applications . The 3 Volt FlashFile m emories are av ailable at v arious densi ties in

the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended cycling

provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced

suspend capabilities provide an ideal solution for code or dat a storage applications . For secure code s torage

applicat ions, such as networki ng, where code is eit her direc tl y ex ecut ed out of flas h or downloaded t o DRAM,

the 3 Volt FlashFile m emory offers three lev els of protection: absolute protect ion with VPP at GND, selective

block l ock ing, and program /eras e loc kout during power trans it ions. These al ternat iv es giv e desi gners ul tim ate

control of their code security needs.

This family of products is manufactured on Intel® 0.4 µm ETOX™ V process technology. It comes in the

industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the

industry-standard 56-lead TSOP package.

NOTE: This document formerly known as

Word-Wide FlashFile™ Memory Family 28F160S3, 28F320S3

3 VOLT FlashFile™ MEMORY

28F160S3 and 28F320S3 (x8/x16)

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property ri ghts is granted by thi s document. E xcept as provided i n Intel’s Terms and Condi tions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F160S3 and 28F320S3 may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-4725

or call 1-800-548-4725

or visit Intel’s website at http:\\www.intel.com

*Third-party brands and names are the property of their respective owners.

E28F160S3/28F320S3

PRELIMINARY

CONTENTS

PAGE PAGE

1.0 INTRODUCTION ............................................... 5

1.1 New Features................................................. 5

1.2 Product Overview........................................... 5

1.3 Pinout and Pin Description............................. 6

2.0 PRINCIPLES OF OPERATION ......................... 9

2.1 Data Protection .............................................10

3.0 BUS OPERATION............................................10

3.1 Read.............................................................11

3.2 Output Disable..............................................11

3.3 Standby.........................................................11

3.4 Deep Power-Down........................................11

3.5 Read Query Operation..................................11

3.6 Read Identifier Codes Operation...................11

3.7 Write .............................................................12

4.0 COMMAND DEFINITIONS...............................12

4.1 Read Array Command...................................16

4.2 Read Query Mode Command........................16

4.2.1 Query Structure Output ..........................16

4.2.2 Query Structure Overview ......................18

4.2.3 Block Status Register.............................19

4.2.4 CFI Query Identification String................20

4.2.5 System Interface Information..................21

4.2.6 Device Geometry Definition....................22

4.2.7 Intel-Specific Extended Query Table ......23

4.3 Read Identifier Codes Command..................24

4.4 Read Status Register Command...................24

4.5 Clear Status Register Command...................25

4.6 Block Erase Command .................................25

4.7 Full Chip Erase Command............................25

4.8 Write to Buffer Command .............................26

4.9 Byte/Word Program Commands...................26

4.10 STS Configuration Command.....................27

4.11 Block Erase Suspend Command................27

4.12 Program Suspend Command......................27

4.13 Set Block Lock-Bit Command.....................28

4.14 Clear Block Lock-Bits Command ................28

5.0 DESIGN CONSIDERATIONS ..........................38

5.1 Three-Line Output Control............................38

5.2 STS and WSM Polling..................................38

5.3 Power Supply Decoupling.............................38

5.4 VPP Trace on Printed Circuit Boards............38

5.5 VCC, VPP, RP# Transitions............................38

5.6 Power-Up/Down Protection...........................38

6.0 ELECTRICAL SPECIFICATIONS....................39

6.1 Absolute Maximum Ratings..........................39

6.2 Operating Conditions....................................39

6.3 Capacitance .................................................40

6.4 DC Characteristics........................................40

6.5 AC Characteristics—Read-Only Operations.45

6.6 AC Characteristics—Write Operations..........47

6.7 Erase, Write, and Lock-Bit Configuration

Performance................................................50

6.8 Erase, Write, and Lock-Bit Configuration

Performance................................................51

7.0 ORDERING INFORMATION...........................52

8.0 ADDITIONAL INFORMATION ........................53

28F160S3/28F320S3 E

4PRELIMINARY

REVISION HISTORY

Date of

Revision Version Description

06/09/97 -001 Original version

11/10/97 -002 Added commercial temperature specifications throughout the document.

Updated Figure 4 by adding pinout letter and number designators,

updating ball locations (F7), and making descriptive information more

clear.

Updated address in Figure 6.

Updated addresses and added descriptive information in Table 9 and

Table 10.

Updated first paragraph of Section 4.8,

Write to Buffer Command

Corrected documentation errors in Table 15 and Table 16.

Updated Figure 7. Modified decision diamond for checking counter.

Corrected documentation errors in Figure 12 and Figure 13.

Updated Table 19 to include commercial and extended temperature range

specifications and added VPPH3.

Updated notes to Table 19. Changed note 4 to be a reference to Figure

13. Added note 5 (explanation of VPP1/2/3). Updated subsequent note

numbers.

Added Figure 17,

Block Erase, Program and Lock-Bit Configurations

under V

Voltage Combinations

and updated subsequent figure

numbers.

Added Table 20,

Valid V

Voltage Combinations for 28F160/320S3

and updated subsequent table numbers.

Updated Table 21 to show 16-Mb/32-Mb specifications more clearly.

Corrected documentation error in Figure 19 and Table 24.

Added µBGA* package mechanical specifications.

Updated package designators and order codes in Appendix A.

12/02/97 -003 Removed µBGA* package option.

01/29/98 -004 Corrected error in datasheet designation

12/10/98 -005 Added Max values for Erase, Write, and Lock-Bit performance, Section

6.8.

Corrected Figure 11, Comments section from “Data = D0H” to “Data =

01H.”

Revised Section 6.5 AC Characteristics to reflect –75 Line Item.

Name of document changed from

Word-Wide FlashFile™ Memory Family

28F160S3, 28F320S3.

E28F160S3/28F320S3

PRELIMINARY

1.0 INTRODUCTION

This datasheet contains 16- and 32-Mbit 3 Volt

FlashFileTM memory (28F160S3 and 28F320S3)

specif ications . Section 1.0 provides a fl ash memory

overview. Sections 2.0 through 5.0 describe the

memory organization and functionality. Section 6.0

covers electrical specifications for extended

temperature product offerings. Finally, Section 7.0

provides ordering and reference information.

1.1 New Features

The 3 Volt FlashFile memory family maintains basic

compatibility wit h Intel’s 28F016SA and 28F016SV.

Key enhancements include:

•Common Flash Interface (CFI) Support

• Scaleable Command Set (SCS) Support

• Low Voltage Technology

•Enhanced Suspend Capabilities

They share a compatible status register, basic

software commands, and pinout. These similarities

enable a clean migration from the 28F016SA or

28F016SV. When upgrading, it is important to note

the following differences:

•Because of new feature and density options,

the devices have different manufacturer and

device identi fier codes. This allows for software

optimization.

•New software commands.

•To take advantage of low voltage on the

28F160S3 and 28F320S3, allow VPP

connection to VCC. The 28F160S3 and

28F320S3 do not support a 12 V VPP option.

1.2 Product Overview

The 3 Volt FlashFile memory family provides

density upgrades with pinout compatibility for the

16- and 32-Mbit densities. They are high-

performance memories arranged as 1 Mword and

2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of

8 bits. This data is grouped in thirty-two and sixty-

four 64-Kbyte blocks that can be erased, locked

and unlocked in-system. Figure 1 shows the block

diagram, and Figure 4 illustrates the memory

organization.

This fam i l y of product s are optim i zed for fas t fac tory

programming and low power designs. Specifically

designed for 3 V systems, the 28F160S3 and

28F320S3 support read operations at 2.7 V–3.6 V

VCC with block erase and program operations at

2.7 V–3.6 V and 5 V VPP. High programming

performance is achieved through highly-optimized

write buffers. A 5 V V PP opt ion is available f or even

faster f actory programming. For a simple low power

design, VCC and VPP can be tied to 2. 7 V .

Additionally, the dedicated VPP pin gives complete

data protection when VPP ≤ VPPLK.

Internal VPP detection circuitry automatically

configures the device for optimized write

operations.

A Common Flash Interface (CFI) permits OEM-

specified software algorithms to be used for entire

families of dev ic es. This allows dev ice-independent,

JEDEC ID-independent, and forward- and

backward-compatible software support for the

specified flash device families. Flash vendors can

standardize their existing interfaces for long-term

compatibility.

Scaleable Command Set (SCS) allows a single,

simple software driver in all host systems to work

with all SCS-compliant flash memory devices,

independent of system-level packaging (e.g.,

memory card, SIMM, or direct -to-board placement).

Additionally, SCS provides the highest

system/device data transfer rates and minimizes

device and system-level implementation costs.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal device operation. A valid command

sequence written to the CUI initiates device

automati on. An internal Write Stat e Machi ne (WSM)

automatically executes the algorithms and timings

necessary for block erase, program, and lock-bit

configuration operations.

A block erase operation erases one of the device’s

64-Kbyte blocks typically within tWHQV2/EHQV2

independent of other blocks. Each block can be

independently erased 100,000 times in the

commerc ial temperat ure range (0 °C t o +70 °C) and

10,000 times in the extended temperature range

(–40 °C to +85 °C). Block erase suspend mode

allows system software to suspend block erase to

read or write data from any other block.

Data is programmed in byte, word or page

increments. Program suspend mode enables the

28F160S3/28F320S3 E

6PRELIMINARY

system to read data or execute c ode from any ot her

flash memory array location.

The device incorporates two Write Buffers of 32

bytes (16 words) to allow optimum-performance

data programming. This feature can improve

system program performance by up to four times

over non-buffer programming.

Indivi dual bloc k loc k ing uses a c ombinat ion of bloc k

lock-bits to lock and unlock blocks. Block lock-bits

gate block eras e, full chi p erase, program and write

to buffer operations. Lock-bit configuration

operations (Set Block Lock-Bit and Clear Block

Lock-Bits commands) set and clear lock-bits.

The status register and the STS pin in RY/BY#

mode indicate whether or not the device is busy

executing an operation or ready for a new

command. Polling the status register, system

software retrieves WSM feedback. STS in RY/BY#

mode gives an additional indicator of WSM activity

by providing a hardware status signal. Like the

status regist er, RY/B Y#-low indic ates t hat the WSM

is performing a block erase, program, or lock-bit

operation. RY/BY#-high indicates that the WSM is

ready for a new command, block erase is

suspended (and program is inactive), program is

suspended, or the device is in deep power-down

mode.

The Automatic Power Savings (APS) feature

substantially reduces active current when the

device is in static mode (addresses not switching).

The BYTE# pin allows either x8 or x16 read/writes

to the device. BYTE# at logic low selects 8-bit

mode with address A0 selecting between the low

byte and high byte. BYTE# at logic high enables

16-bit operation with address A1 becoming the

lowest order addres s. Addres s A0 i s not used i n 16-

bit mode.

When one of the CEX# pins (CE0#, CE1#) and RP#

pins are at VCC, the component enters a CMOS

standby mode. Dri vi ng RP# to GND enabl es a deep

power-down mode which significantly reduces

power consumption, provides write protection,

resets the device, and clears the status register. A

reset time (tPHQV) is required from RP# switching

high until outputs are valid. Likewise, the device

has a wake time (tPHEL) from RP#-high until writes

to the CUI are recognized.

1.3 Pinout and Pin Description

The 16-Mbit device is available in the 56-lead

TSOP and 56-lead SSOP packages. The 32-Mb

device is available in the 56-lead SSOP package.

The pinouts are shown in Figures 2 and 3.

16-Mbit: Thirty-two

32-Mbit: Sixty-four

64-Kbyte Blocks

Input Buffer

Output

Multiplexer

Y-Gating

Program/Erase

Voltage Switch

Data

Comparator

Status

Identifier

Data

I/O Logic

Address

Latch

Address

Counter

X-Decoder

Y-Decoder

Input Buffer

Output Buffer

GND

CE#

WE#

OE#

RP#

WP#

BYTE#

Command

User

Interface

16-Mbit: A

- A

32-Mbit: A

0 -

- DQ

Write Buffer

Write State

Machine

Multiplexer

Query

STS

0608_01

Figure 1. Block Diagram

E28F160S3/28F320S3

PRELIMINARY

Table 1. Pin Descriptions

Sym Type Name and Function

A0–A21 INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally

latched during a write cycle. A0 selects high or low byte when operating in x8 mode.

In x16 mode, A0 is not used; input buffer is off.

16-Mbit → A0–A20 32-Mbit → A0–A21

DQ0–

DQ15 INPUT/

OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles;

outputs data during memory array, status register, query and identifier code read

cycles. Data pins float to high-impedance when the chip is deselected or outputs

are disabled. Data is internally latched during a write cycle.

CE0#,

CE1#INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and

sense amplifiers. With CE0# or CE1# high, the device is deselected and power

consumption reduces to standby levels. Both CE0# and CE1# must be low to select

the device. Device selection occurs with the latter falling edge of CE0# or CE1#. The

first rising edge of CE0# or CE1# disables the device.

RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations

which provides data protection during system power transitions, puts the device in

deep power-down mode, and resets internal automation. RP#-high enables normal

operation. Exit from deep power-down sets the device to read array mode.

OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data

are latched on the rising edge of the WE# pulse.

STS OPEN

DRAIN

OUTPUT

STATUS: Indicates the status of the internal state machine. When configured in

level mode (default), it acts as a RY/BY# pin. For this and alternate configurations

of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up

resistor.

WP# INPUT WRITE PROTECT: Master control for block locking. When VIL, locked blocks

cannot be erased or programmed, and block lock-bits cannot be set or cleared.

BYTE# INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).

VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:

Necessary voltage to perform block erase, program, and lock-bit configuration

operations. Do not float any power pins.

VCC SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block

erase, program, or block-lock configuration with invalid VCC values.

GND SUPPLY GROUND: Do not float any ground pins.

NC NO CONNECT: Lead is not internally connected; it may be driven or floated.

28F160S3/28F320S3 E

8PRELIMINARY

1 56

2 55

3 54

4 53

5 52

6 51

7 50

8 49

9 48

10 47

11 46

12 45

13 44

14 43

15 42

16 41

17 40

18 39

19 38

20 37

21 36

22 35

23 34

24 33

25 32

26 31

27 30

28 29

56-LEAD TSOP

STANDARD PINOUT

14 mm x 20 mm

TOP VIEW

Highlights pinout changes.

WP#

WE#

OE#

RY/BY#

GND

BYTE#

28F016SA

28F016SV

RY/BY#

3/5#

RP#

GND

28F016SA

28F016SV

3/5# NC

RP#

GND

28F160S3

28F160S5

WP#

WE#

OE#

STS

GND

BYTE#

28F160S3

28F160S5

0608_02

Figure 2. TSOP 56-Lead Pinout

E28F160S3/28F320S3

PRELIMINARY

56-LEAD SSOP

STANDARD PINOUT

16 mm x 23.7 mm

TOP VIEW

28F016SA

WE#

WP#

OE#

GND

A12

CE #

A13

A14

A15

CE #

A20

A19

A18

A17

A16

VCC

DQ13

DQ5

DQ12

DQ4

DQ6

DQ14

DQ7

DQ15

STS

GND

BYTE#

GND

DQ2

DQ10

DQ3

DQ11

DQ0

DQ8

DQ1

DQ9

VCC

A10

A11

VPP

28F016SV

WE#

WP#

OE#

GND

A12

CE #

A13

A14

A15

CE #

A20

A19

A18

A17

A16

VCC

DQ13

DQ5

DQ12

DQ4

DQ6

DQ14

DQ7

DQ15

WE#

WP#

OE#

GND

A12

CE #

A13

A14

A15

CE #

A20

A19

A18

A17

A16

VCC

DQ13

DQ5

DQ12

DQ4

DQ6

DQ14

DQ7

DQ15

28F016SA

GND

BYTE#

GND

DQ2

DQ10

DQ3

DQ11

DQ0

DQ8

DQ1

DQ9

VCC

A10

A11

VPP

28F016SV

GND

BYTE#

GND

DQ2

DQ10

DQ3

DQ11

DQ0

DQ8

DQ1

DQ9

VCC

A10

A11

VPP

STS

R/P#

RY/BY#

3/5#

A21

Highlights pinout changes.

28F320S5

28F320S3 28F160S5

28F160S3 28F320S5

28F320S3

28F160S5

28F160S3

0608_03

Figure 3. SSOP 56-Lead Pinout

2.0 PRINCIPLES OF OPERATION

The 3 Volt memories include an on-chip Write

State Machine (WSM) to manage block erase,

program, and lock-bit configuration functions. It

allows for: 100% TTL-level control inputs, fixed

power supplies during block erasure,

programming, lock-bit configuration, and minimal

processor overhead with RAM-like interface

timings.

After initial device power-up or return from deep

power-down mode (see

Bus Operations

), the

device def aults to read array mode. Manipulati on

of external memory control pi ns allow array read,

standby, and output disable operations.

Read array, status register, query, and identifier

codes can be accessed through the CUI

independent of the VPP voltage. Proper

programming voltage on VPP enables successful

block erasure, program, and lock-bit

configuration. All functions associated with

altering memory contents —block eras e, program,

lock-bit configuration—are accessed via the CUI

and verified through the status register.

Commands are written using standard micro-

processor write timings. The CUI contents serve

as input to the WSM that controls the block

erase, programming, and lock-bit configuration.

The internal algorithms are regulated by the

WSM, including pulse repetition, internal

verification, and margining of data. Addresses

and data are internally latched during write

cycles. Writing the appropriate command outputs

array data, identifier codes, or status register

data.

28F160S3/28F320S3 E

10 PRELIMINARY

Interface software that initiates and polls

progress of block erase, programming, and lock-

bit configuration can be stored in any block. This

code is copied to and executed from system

RAM during flash memory updates. After

successful completion, reads are again possible

via the Read Array command. Block erase

suspend allows system software to suspend a

block erase to read or write data from any other

block. Program suspend allows system software

to suspend a program to read data from any

other flash memory array location.

2.1 Data Protection

Depending on the application, the system

designer may choose to make the VPP power

supply switchable or hardwired to VPPH1/2/3. The

device supports either design practice, and

encourages optimization of the processor-

memory interface.

When VPP ≤ VPPLK, memory contents cannot be

altered. When high voltage is applied to VPP, the

two-step block erase, program, or lock-bit

configuration command sequences provide

protection from unwanted operations. All write

functi ons are disabled when V CC voltage is below

the write lockout voltage VLKO or when RP# is at

VIL. The device’s block locking capability

provides additional protection from inadvertent

code or data alteration.

3.0 BUS OPERATION

The local CP U reads and writes flash memory in-

system. All bus cycles to or from the flash

memory conf orm to standard mi croprocessor bus

cycles.

64-Kbyte Block

3FFFFF

3F0000

64-Kbyte Block

1FFFFF

1F0000

64-Kbyte Block

01FFFF

010000

64-Kbyte Block

00FFFF

000000

32-Kword Block

1FFFFF

1F0000

32-Kword Block

0FFFFF

0F8000

32-Kword Block

00FFFF

008000

32-Kword Block

007FFF

000000

32-Mbit: A[

21-1

]

16-Mbit: A[

20-1

]

32-Mbit: A[

21-0

]

16-Mbit: A[

20-0

]

Byte-Wide (x8) Mode Word-Wide (x16) Mode

16 Mbit

32 Mbit

0608_05

Figure 4. Memory Map

E28F160S3/28F320S3

PRELIMINARY

3.1 Read

Block information, query information, identifier

codes and status registers can be read

independent of the VPP voltage.

The first task is to place the device into the

desired read mode by writing the appropriate

read-mode command (Read Array, Query, Read

Identifier Codes, or Read Status Register) to the

CUI. Upon initial device power-up or after exit

from deep power-down mode, the device

automatically resets to read array mode. Control

pins dictate the data flow in and out of the

component. CE0#, CE1# and OE # must be driven

active to obtain data at the outputs. CE0# and

CE1# are the device selection controls, and,

when both are active, enable the selected

memory device. OE# is the data output (DQ0–

DQ15) control: When active it drives the selected

memory data onto the I/O bus. WE# must be at

VIH and RP# must be at VIH. Figure 17 illustrates

a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins DQ0–DQ15 are

placed in a high-impedance state.

3.3 Standby

CE0# or CE1# at a logic-high level (VIH) places

the device in standby mode, substantially

reducing device power consumption. DQ0–DQ15

(or DQ0– DQ7 in x8 mode) outputs are placed in

a high-impedance state independent of OE#. If

deselected during block erase, programming, or

lock-bit configuration, the device continues

functioning and consuming active power until the

operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read mode, RP#-low deselects the memory,

places output drivers in a high-impedance state,

and turns off all internal circuits. RP# must be

held low for time tPLPH. Time tPHQV is required

after return from power-down until initial memory

access outputs are valid. After this wake-up

interval, normal operation is restored. The CUI

resets to read array mode, and the s tat us regi st er

is set to 80H.

During block erase, programming, or lock-bit

configuration modes, RP#-low will abort the

operation. STS in RY/BY# mode remains low

until the reset operation is complete. Memory

contents being altered are no longer valid; the

data may be partially corrupted after

programming or parti ally altered af ter an erase or

lock-bit conf igurati on. Tim e tPHWL i s required af ter

RP# goes to logic-high (VIH) before another

command can be written.

It is important in any automated system to assert

RP# during system reset. When the system

comes out of reset, it expects to read from the

flash memory. Automated flash memories

provide st atus information when acc essed during

block erase, programming, or lock-bit

configuration modes. If a CPU reset occurs with

no flash memory reset, proper CPU initialization

may not oc cur bec aus e the fl ash m emory may be

providing s tat us inf ormat ion ins tead of array dat a.

Intel’s Flash memories allow proper CPU

initialization following a system reset through the

use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that

resets the system CPU.

3.5 Read Query Operation

The read query operation outputs block status,

Common Flash Interface (CFI) ID string, system

interface, device geometry, and Intel-specific

extended query information.

3.6 Read Identifier Codes

Operation

The read-identifier codes operation outputs the

manufacturer code, device code, and block lock

configuration codes for each block configuration

(see Figure 5). Using the manufacturer and

device codes, the system software can

automatically match the device with its proper

algorithms. The block-lock configuration codes

identify each block’s lock-bit setting.

28F160S3/28F320S3 E

12 PRELIMINARY

Reserved for Future

Implementation

(Subsequent Blocks)

Reserved for Future

Implementation

Block 1 Lock Configuration

Reserved for Future

Implementation

Device Code

Manufacturer Code

Block 0

Block 1

Word

Address

0FFFF

08004

08003

08002

08000

07FFF

00004

00003

00002

00001

00000

20-1

]: 16-Mbit

21-1

]: 32-Mbit

Block 0 Lock Configuration

0608_06

Figure 5. Device Identifier Code Memory Map

3.7 Write

Writing commands t o the CUI enables reading of

device data, query, identifier codes, inspection

and clearing of the status register. Additionally,

when VPP = VPPH1/2/3, block erasure, program-

ming, and lock-bit configuration can also be

performed.

The Block Erase command requires appropriate

command data and an address within the block

to be erased. The Byte/Word Write command

requires the command and address of the

location to be written. Set Block Lock-Bit

commands require the command and address

within the block to be locked. The Clear Block

Lock-Bits command requires the command and

an address within the device.

The CUI does not occupy an addressable

memory location. It is written when WE#, CE0#,

and CE1# are acti ve and OE # = V IH. The address

and data needed to execute a command are

latched on the rising edge of WE# or CEX#

(CE0#, CE1#), whichever goes high first.

Standard microprocessor write timings are used.

Figure 18 illustrates a write operation.

4.0 COMMAND DEFINITIONS

VPP voltage ≤ V

PPLK enables read operations

from the status register, identifier codes, or

memory blocks. Placing VPPH1/2/3 on VPP enables

successful block erase, programming, and lock-

bit configuration operations.

Device operat ions are sel ect ed by writi ng s pec ifi c

commands into the CUI. and Table 3 define

these commands.

E28F160S3/28F320S3

PRELIMINARY

Table 2. Bus Operations

Mode Notes RP# CE0#CE

1# OE#(11) WE#(11) Address VPP DQ(8) STS(3)

Read 1,2 VIH VIL VIL VIL VIH XXD

OUT X

Output Disable VIH VIL VIL VIH VIH X X High Z X

Standby VIH VIL

VIH

VIL

VIH

X X X X High Z X

Reset/Power-

Down Mode 10 VIL X X X X X X High Z High Z(9)

Read Identifier

Codes 4V

IH VIL VIL VIL VIH See

Figure 5 XD

OUT High Z(9)

Read Query 5 VIH VIL VIL VIL VIH See Table 6 X DOUT High Z(9)

Write 3,6,7 VIH VIL VIL VIH VIL XV

PPH1/2/3 DIN X

NOTES:

1. Refer to

DC Characteristics

. When VPP ≤ VPPLK, memory contents can be read, but not altered.

2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2/3 for VPP. See Section 6.4,

DC Characteristics

for VPPLK and VPPH1/2/3 voltages.

3. STS in level RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit

configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive),

program suspend mode, or deep power-down mode.

4. See Section 4.3 for read identifier code data.

5. See Section 4.2 for read query data.

6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V

PP = VPPH1/2/3 and

VCC = VCC1/2 (see Section 6.2).

7. Refer to Table 3 for valid DIN during a write operation.

8. DQ refers to DQ0–7 if BYTE# is low and DQ0–15 if BYTE# is high.

9. High Z will be VOH with an external pull-up resistor.

10. RP# at GND ± 0.2 V ensures the lowest deep power-down current.

11. OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.

28F160S3/28F320S3 E

14 PRELIMINARY

Table 3. 3 Volt FlashFile™ Memory (28F160S3. 28F320S3) Command Set Definitions(13)

Command Scaleable

or Basic

Command

Set(14)

Bus

Cycles

Req'd

Notes First Bus Cycle Second Bus Cycle

Oper(1) Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4)

Read Array SCS/BCS 1 Write X FFH

Read Identifier Codes SCS/BCS ≥2 5 Write X 90H Read IA ID

Read Query SCS ≥ 2 Write X 98H Read QA QD

Read Status Register SCS/BCS 2 Write X 70H Read X SRD

Clear Status Register SCS/BCS 1 Write X 50H

Write to Buffer SCS > 2 8, 9, 10 Write BA E8H Write BA N

Word/Byte Program SCS/BCS 2 6,7 Write X 40H

10H

Write PA PD

Block Erase SCS/BCS 2 6,10 Write X 20H Write BA D0H

Block Erase, Word/Byte

Program Suspend SCS/BCS 1 6 Write X B0H

Block Erase, Word/Byte

Program Resume SCS/BCS 1 6 Write X D0H

STS pin Configuration SCS 2 Write X B8H Write X CC

Set Block Lock-Bit SCS 2 11 Write X 60H Write BA 01H

Clear Block Lock-Bits SCS 2 12 Write X 60H Write X D0H

Full Chip Erase SCS 2 10 Write X 30H Write X D0H

E28F160S3/28F320S3

PRELIMINARY

NOTES:

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.

BA = Address within the block being erased or locked.

IA = Identifier Code Address: see Table 12.

QA = Query database Address.

PA = Address of memory location to be programmed.

3. ID = Data read from Query database.

SRD = Data read from status register. See Table 15 for a description of the status register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.

CC = Configuration Code. (See Table 14.)

4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation.

5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See

Section 4.3 for read identifier code data.

6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and

suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V

will fail.

7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.

8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.

9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1

byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the

correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write

cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the

buffer boundary causes unexpected results and should be avoided.

10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.

Confirm also reactivates suspended operations.

11. A block lock-bit can be set only while WP# is VIH.

12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.

13. Commands other than those shown above are reserved for future use and should not be used.

14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The

Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.

28F160S3/28F320S3 E

16 PRELIMINARY

4.1 Read Array Command

Upon initial device power-up and after exit from

deep power-down mode, the device defaults t o read

array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is writ ten. Once t he internal WSM has s tarted block

erase, program, or lock-bi t c onfigurati on, the devic e

will not recognize the Read Array command until

the WSM c ompletes i t s operation—unles s the WSM

is suspended via an Erase-Suspend or Program-

Suspend command. The Read Array command

functions independently of the VPP voltage.

4.2 Read Query Mode Command

This section defines the data structure or

“database” returned by the Common Flash Interface

(CFI) Query command. System software should

parse this structure to gain crit ical inform ation such

as block size, density, x8/x16, and electrical

specifications. Once this information has been

obtained, the software will know which command

sets t o use to enable f l ash writes, block eras es, and

otherwise control the flash component. The Query

is part of an overall specification for multiple

command set and control interface descriptions

called Common Flash Interface, or CFI.

4.2.1 QUERY STRUCTURE OUTPUT

The Query “database” allows system software to

gain critical information for controlling the flash

component. This section describes the device’s

CFI-compliant interface that allows the host system

to access Query data.

Query data are always presented on the lowest-

order data outputs (DQ0-7) only. The numerical

offset v alue is the addres s relative to t he maximum

bus width supported by the device. On this device,

the Query table device starting address is a 10h

word address, since the maximum bus width is x16.

For this word-wide (x16) device, the first two bytes

of the Query structure, “Q” and ”R” in ASCII, appear

on the low byte at word addresses 10h and 11h.

This CFI-compliant device outputs 00H data on

upper bytes. Thus, the device outputs ASCII “Q” in

the low byte (DQ0-7) and 00h in the high byte

(DQ8-15).

Since the device is x8/x16 capable, the x8 data is

still presented in word-relative (16-bit) addresses.

However, the “fill data” (00h) is not the same as

driven by the upper bytes in the x16 mode. As in

x16 mode, the byte address (A0) is ignored for

Query output so that the “odd byte address” (A0

high) repeats the “ev en byt e address ” data (A 0 low).

Therefore, in x8 mode using byte addressing, the

device will output the sequence “Q”, “Q”, “R”, “R”,

“Y”, “Y”, and so on, beginning at byte-relative

address 20h (whic h is equiv alent to word of fset 10h

in x16 mode).

At Query addresses containing two or more bytes

of information, the least significant data byte is

presented at the lower address, and the most

significant data byte is presented at the higher

address.

E28F160S3/28F320S3

PRELIMINARY

Table 4. Summary of Query Structure Output as a Function of Device and Mode

Device Type/Mode Word Addressing Byte Addressing

Location Query Data

Hex, ASCII Location Query Data

Hex, ASCII

x16 device/

x16 mode 10h

11h

12h

0051h “Q”

0052h “R”

0059h “Y”

20h

21h

22h

51h “Q”

00h null

52h “R”

x16 device/

x8 mode N/A(1) N/A 20h

21h

22h

51h “Q”

52h “R”

NOTE:

1. The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8

mode. Therefore, word addressing where lower addresses are not toggled by the system is “Not Applicable” for x8-

configured devices.

Table 5. Example of Query Structure Output of a x16- and x8-Capable Device

Device

Address Word Addressing:

Query Data Byte

Address Byte Addressing:

Query Data

A16–A1D15–D0A7–A0D7–D0

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051h “Q”

0052h “R”

0059h “Y”

P_IDLO PrVendor

P_IDHI ID #

PLO PrVendor

PHI TblAdr

A_IDLO AltVendor

A_IDHI ID #

...

20h

21h

22h

23h

24h

25h

26h

27h

28h

...

51h “Q”

52h “R”

59h “Y”

P_IDLO PrVendor

P_IDLO ID #

P_IDHI “

...

28F160S3/28F320S3 E

18 PRELIMINARY

4.2.2 QUERY STRUCTURE OVERVIEW

The Query command causes the flash component

to display the Common Flash I nterface (CFI) Query

structure or “database.” The structure sub-sections

and address locations are summarized in Table 8.

The following s ections des cribe the Query s tructure

sub-sections in detail.

Table 6. Query Structure(1)

Offset Sub-Section Name Description

00h Manufacturer Code

01h Device Code

(BA+2)h(2) Block Status Register Block-specific information

04-0Fh

Reserved Reserved for vendor-specific information

10h CFI Query Identification String Command set ID and vendor data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P(3) Primary Intel-Specific Extended Query

Table Vendor-defined additional information

specific to the Primary Vendor Algorithm

NOTES:

1. Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode.

2. BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is

32 Kword).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

E28F160S3/28F320S3

PRELIMINARY

4.2.3 BLOCK STATUS REGISTER

The block status register indicates whether an

erase operation completed successfully or whether

a given bloc k i s loc ked or c an be ac ces sed f or f las h

program/erase operations.

Block Erase Status (BSR.1) allows system software

to determine the success of the last block erase

operation. B S R.1 can be used j ust after power-up to

verify that the VCC supply was not accidentally

removed during an erase operation. This bit is only

reset by issuing another erase operation to the

block. The block status register is accessed from

word address 02h within each block.

Table 7. Block Status Register

Offset Length

(bytes) Description 28F320S3/

28F160S3

x16 Device/Mode

(BA+2)h(1) 01h Block Status Register BA+2: 0000h or

0001h

BSR.0 = Block Lock Status

1 = Locked

0 = Unlocked

BA+2 (bit 0): 0 or 1

BSR.1 = Block Erase Status

1 = Last erase operation did not complete

successfully

0 = Last erase operation completed successfully

BA+2 (bit 1): 0 or 1

BSR 2-7 Reserved for future use

BA+2 (bits 2-7): 0

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)

28F160S3/28F320S3 E

20 PRELIMINARY

4.2.4 CFI QUERY IDENTIFICATION STRING

The Identification String provides verification that

the component supports the Common Flash

Interface specification. Additionally, it indicates

which version of the specification and which

vendor-specified command set(s) is (are)

supported.

Table 8. CFI Identification

Offset Length

(Bytes) Description 28F320S3/

28F160S3

10h 03h Query-Unique ASCII string “QRY“ 10: 0051h

11: 0052h

12: 0059h

13h 02h Primary Vendor Command Set and Control Interface ID Code

16-bit ID Code for Vendor-Specified Algorithms 13: 0001h

14: 0000h

15h 02h Address for Primary Algorithm Extended Query Table

Offset value =

= 31h 15: 0031h

16: 0000h

17h 02h Alternate Vendor Command Set and Control Interface ID Code

Second Vendor-Specified Algorithm Supported

Note: 0000h means none exists

17: 0000h

18: 0000h

19h 02h Address for Secondary Algorithm Extended Query Table

Note: 0000h means none exists 19: 0000h

1A: 0000h

E28F160S3/28F320S3

PRELIMINARY

4.2.5 SYSTEM INTERFACE INFORMATION

The following device information can be useful in

optimizing system interface software.

Table 9. System Interface Information

Offset Length

(bytes) Description 28F160S3 28F320S3

1Bh 01h VCC Logic Supply Minimum Program/Erase Voltage

bits 7–4 BCD volts

bits 3–0 BCD 100 mv

1B: 0027h 1B: 0027h

1Ch 01h VCC Logic Supply Maximum Program/Erase Voltage

bits 7–4 BCD volts

bits 3–0 BCD 100 mv

1C: 0055h 1C: 0055h

1Dh 01h VPP [Programming] Supply Minimum Program/Erase

Voltage

bits 7–4 HEX volts

bits 3–0 BCD 100 mv

1D: 0027h 1D: 0027h

1Eh 01h VPP [Programming] Supply Maximum Program/Erase

Voltage

bits 7–4 HEX volts

bits 3–0 BCD 100 mv

1E: 0055h 1E: 0055h

1Fh 01h Typical Time-Out per Single Byte/Word Program,

2N µsec 1F: 0003h

(23 = 8) 1F: 0003h

(23 = 8)

20h 01h Typical Time-Out for Max. Buffer Write, 2N µsec 20: 0006h

(26 = 64) 20: 0006h

(26 = 64)

21h 01h Typical Time-Out per Individual Block Erase,

2N msec 21: 000Ah

(0Ah = 10d,

210 = 1024)

21: 000Ah

(0Ah = 10d,

210 = 1024)

22h 01h Typical Time-Out for Full Chip Erase, 2N msec 22: 000Fh

(0Fh = 15d,

215 = 32768)

22: 000Fh

(0Fh = 15d,

215 = 32768)

23h 01h Maximum Time-Out for Byte/Word Program,

2N Times Typical 23: 0004h

(24 = 16,

16xTypical)

23: 0004h

(24 = 16,

16xTypical)

24h 01h Maximum Time-Out for Buffer Write, 2N Times

Typical (24 = 16, 16 x Typical) 24: 0004h

(24 = 16,

16xTypical)

24: 0004h

(24 = 16,

16xTypical)

25h 01h Maximum Time-Out per Individual Block Erase,

2N Times Typical (24 = 16, 16 x Typical) 25: 0004h

(24 = 16,

16xTypical)

25: 0004h

(24 = 16,

16xTypical)

26h 01h Maximum Time-Out for Full Chip Erase, 2N Times

Typical (24 = 16, 16 x Typical) 26: 0004h

(24 = 16,

16xTypical)

26: 0004h

(24 = 16,

16xTypical)

28F160S3/28F320S3 E

22 PRELIMINARY

4.2.6 DEVICE GEOMETRY DEFINITION

This fi eld provides c ritic al details of the flash devic e

geometry.

Table 10. Device Geometry Definition

Offset Length

(bytes) Description 28F160S3 28F320S3

27h 01h Device Size = 2N in Number of Bytes 27: 0015h

(15h = 21d, 221 =

2097152 bytes =

2 MB = 16 Mb)

27: 0016h

(16h = 22d, 222=

4194304 bytes =

4 MB = 32 Mb)

28h 02h Flash Device Interface Description

value meaning

0002h x8/x16 asynchronous

28: 0002h

29: 0000h 28: 0002h

29: 0000h

2Ah 02h Maximum Number of Bytes in Write Buffer

= 2N2A: 0005h

2B: 0000h

(25 = 32)

2A: 0005h

2B: 0000h

(25 = 32)

2Ch 01h Number of Erase Block Regions within

Device:

bits 7–0 = x = # of regions within the

device containing one or more

contiguous Erase Blocks of the

same size.

2C: 0001h 2C: 0001h

2Dh 04h Erase Block Region Information

bits 15–0 = y, where y+1 = number of

erase blocks of identical size within region.

bits 31–16 = z, where the erase block(s)

within this region are z × 256 Bytes. z is

the number of “256-Byte” clusters in an

erase block.

y: 2D: 001Fh

2E: 0000h

(1Fh+1=32 blocks)

z: 2F: 0000h

30: 0001h

(100h = 256,

256 x 256 = 64 KB)

y: 2D: 003Fh

2E: 0000h

(3Fh+1=64 blocks)

z: 2F: 0000h

30: 0001h

(100h = 256,

256 x 256= 64 KB)

E28F160S3/28F320S3

PRELIMINARY

4.2.7 INTEL-SPECIFIC EXTENDED QUERY

TABLE

Certain flash features and commands are optional.

The Intel-Specific Extended Query table specifies

this and other similar types of information.

Table 11. Primary-Vendor Specific Extended Query

Offset(1) Length

(bytes) Description Data

(P)h 03h Primary Extended Query Table

Unique ASCII String “PRI“ 31: 0050h

32: 0052h

33: 0049h

(P+3)h 01h Major Version Number, ASCII 34: 0031h

(P+4)h 01h Minor Version Number, ASCII 35: 0030h

(P+5)h 04h Optional Feature & Command Support

bit 0 Chip Erase Supported (1=yes, 0=no)

bit 1 Suspend Erase Supported (1=yes, 0=no)

bit 2 Suspend Program Supported (1=yes, 0=no)

bit 3 Lock/Unlock Supported (1=yes, 0=no)

bit 4 Queued Erase Supported (1=yes, 0=no)

bits 5–31 Reserved for future use; undefined bits

are “0”

36: 000Fh

37: 0000h

38: 0000h

39: 0000h

(P+9)h 01h Supported Functions after Suspend

Read Array, Status, and Query are always supported during

suspended Erase or Program operation. This field defines

other operations supported.

bit 0 Program Supported after Erase Suspend

(1=yes, 0=no)

bits 1-7 Reserved for future use; undefined bits are “0”

3A: 0001h

(P+A)h 02h Block Status Register Mask

Defines which bits in the Block Status Register section of

Query are implemented.

bit 0 Block Status Register Lock-Bit [BSR.0] active

(1=yes, 0=no)

bit 1 Block Erase Status Bit [BSR.1] active

(1=yes, 0=no)

bits 2-15 Reserved for future use; undefined bits

are “0”

3B: 0003h

3C: 0000h

NOTES:

1. The variable P is a pointer which is defined at offset 15h in Table 8.

28F160S3/28F320S3 E

24 PRELIMINARY

Table 11. Primary-Vendor Specific Extended Query (Continued)

Offset Length

(bytes) Description Data

(P+C)h 01h VCC Logic Supply Optimum Program/Erase voltage (highest

performance)

bits 7–4 BCD value in volts

bits 3–0 BCD value in 100 mv

3D: 0050h

(P+D)h 01h VPP [Programming] Supply Optimum Program/Erase voltage

bits 7–4 HEX value in volts

bits 3–0 BCD value in 100 mv

3E: 0050h

(P+E)h

reserved Reserved for future use

Table 12. Identifier Codes

Code Address(2) Data

Manufacturer Code 000000 B0

Device Code 16 Mbit 000001 D0

32 Mbit 000001 D4

Block Lock Configuration X0002(1)

• Block Is Unlocked DQ0 = 0

• Block Is Locked DQ0 = 1

• Reserved for Future Use DQ2-7

Block Erase Status x0002(1)

• Last erase completed

successfully DQ1 = 0

• Last erase did not

complete successfully DQ1 = 1

• Reserved for Future Use DQ2-7

NOTES:

1. X selects the specific block lock configuration code.

See Figure 5 for the device identifier code memory

map.

2. A0 should be ignored in this address. The lowest order

address line is A1 in both word and byte mode.

4.3 Read Identifier Codes

Command

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command wri te, read cycles from addresses s hown

in Figure 5 retrieve the manufacturer, device, block

lock configuration, and block erase status codes

(see Table 12 for identifier code values). To

terminate the operation, write another valid

command. Like the Read Array command, the

Read Identifier Codes command functions

independently of the VPP voltage. Following the

Read Identifier Codes command, the information in

Table 12 can be read.

4.4 Read Status Register

Command

The status register may be read to det ermine when

programming, block erasure, or lock-bit

configurat ion is com plet e and whether the operat ion

completed succ essfully. It may be read at any time

by writing the Read Status Register command.

After writing this command, all subsequent read

operations out put data from the st atus register until

another valid command is written. The status

OE#, CE0#, or CE1# whichever occurs last . OE# or

CEX# must toggle to VIH to update the status

functions independently of the VPP voltage.

E28F160S3/28F320S3

PRELIMINARY

Following a program, bl ock erase, set block lock-bit,

or clear block lock-bits command sequence, only

SR.7 is valid until the Write State Machine

completes or suspends the operation. Device I/O

pins DQ0-6 and DQ8-15 are invalid. When the

operation completes or suspends (SR.7 = 1), all

contents of the status register are valid when read.

The eXtended Status Register (XSR) may be read

to determine Write Buffer availability (see Table 16).

The XSR may be read at any time by writing the

Write to Buffer command. After writing this

command, all subsequent read operations output

data from the XSR, until another valid command is

written. The contents of the X SR are lat ched on the

falling edge of OE# or CEX# whichever occurs last

in the read cycle. Write to buffer command must be

re-issued to update the XSR latch.

4.5 Clear Status Register

Command

Status regis ter bit s S R.5, SR. 4, SR. 3, and S R.1 are

set to “1”s by the WSM and can only be reset by

the Clear Status Register command. These bits

indicate various failure conditions (see Table 15).

By allowing system software to reset these bits,

several operat ions (such as cumulativ ely erasing or

locking multiple blocks or programming several

bytes/words in sequence) may be performed. The

status register may be polled to determine if an

error occurred during the sequence.

To clear the status register, the Clear Status

independently of the applied VPP voltage. This

command is not functional during block erase or

program suspend modes.

4.6 Block Erase Command

Block Erase is executed one block at a time and

initiated by a two-cycle command. A Block Erase

Setup command is written first, followed by a

Confirm command. This command sequence

requires appropriate sequencing and an address

within the block to be erased (erase changes all

block data to FFH). Block preconditioning, erase,

and verify are handled internally by the WSM

(invisible to the system). After the two-cycle block

erase sequence is written, the device automatically

outputs status register data when read (see Figure

9). The CPU can detect block erase completion by

analyzing STS in level RY/BY# mode or status

update the status register.

When the block erase is complete, status register

bit SR. 5 should be chec ked. If a bl ock erase error i s

detected, the status register should be cleared

before system software attempts corrective actions.

The CUI remains in read status register mode until

a new command is issued.

This two-step command sequence of set-up

followed by execution ensures that block contents

are not accidentally erased. An invalid Block Erase

command sequence will result in both status

reliable block erasure can only occur when

VCC = VCC1/2 and VPP = VPPH1/2/3. In the abs ence of

these voltages, block contents are protected

against erasure. If block erase is attempted while

VPP ≤ V

PPLK, SR.3 and SR.5 will be set to “1.”

Successful block erase requires that the

corresponding block lock-bit be cleared, or WP# =

VIH. If block erase is attempted when the

corresponding block lock-bit is set and WP# = VIL,

the block erase will fail and SR.1 and SR.5 will be

set to “1.”

4.7 Full Chip Erase Command

The Full Chip Erase command followed by a

Confirm c ommand erases all unlock ed blocks. After

the Confirm command is written, the device erases

all unlocked blocks from block 0 to block 31 (or 63)

sequentially. Block preconditioning, erase, and

verify are handled internally by the WSM. After the

Full Chip Erase command sequence is written to

the CUI, the device aut omatical ly output s the s tatus

chip erase completion by polling the STS pin in

level RY/BY# mode or status register bit SR.7.

When the full chip erase is compl ete, st atus regis ter

bit SR.5 should be checked to see if the operation

completed successfully. If an erase error occurred,

the status register should be cleared before issuing

the next c ommand. The CUI remai ns in read st atus

error is detected while erasing a block during a full

chip erase operation, the WSM sk ips the remaining

cells in that block and proceeds to erase the next

block. Reading the block valid status code by

issuing the Read Identifier Codes command or

Query comm and informs the user of which block(s )

failed to erase.

28F160S3/28F320S3 E

26 PRELIMINARY

This two-s tep command sequence of setup fol l owed

by execution ensures that block contents are not

accidentally erased. An invalid Full Chip Erase

command sequence will result in both status

reliable full chip erasure can only occur when

VCC = VCC1/2 and VPP = VPPH1/2/3. In the abs ence of

these voltages, block contents are protected

against eras ure. If ful l chip erase is att empted while

VPP ≤ VPPLK, SR.3 and SR.5 will be set to 1. When

WP# = VIL, only unlocked blocks are erased. Full

chip erase cannot be suspended.

4.8 Write to Buffer Command

To program the flash devic e via the write buffers, a

Write to Buffer command sequence is initiated. A

variable number of bytes or words, up to the buffer

size, can be wri tt en into t he buf fer and programmed

to the flash device. First, the Write to Buffer Setup

command is issued along with the Block Address.

At this point, the XSR information is loaded and

XSR.7 indicates that another Write to Buffer

command is possible. If XSR.7 = 0, no write buffer

is avai lable. To retry , cont inue monit oring X SR.7 by

issui ng the Write t o Buffer S etup comm and with the

Block Address until XSR.7 = 1. When XSR.7

transitions to a “1,” the buffer is ready for loading.

Next, a word or byte count is issued at a valid

address within the block. On the next write, a

device start address is given along with the write

buffer data. For maximum programming

performance and lower power, align the start

address at the beginning of a writ e buffer boundary.

Subsequent writes must supply additional device

addresses and data, depending on the count. All

subsequent addresses must lie within the start

address plus the count.

After the final buffer data is given, a Write Confirm

command is iss ued. This ini t i ates t he WSM to begi n

copying the buffer data to the flash memory. If a

command other than Write Conf irm is written t o the

device, an “Invalid Command/Sequence” error will

be generated and status register bits SR.5 and

SR.4 will be set to “1.” For additional buffer writes,

issue another Write to Buffer Setup command and

check XSR.7. The write buf fers can be l oaded while

the WSM is bus y as long as X SR.7 indicat es that a

buffer is available. Refer to Figure 6 f or the

Write to

Buffer Flowchart

If an error occurs while writing, the device will stop

programming, and status register bit SR.4 will be

set to a “1” to indicat e a program failure. Any ti me a

media failure occurs during a program or an erase

(SR.4 or SR.5 is set), the device will not accept any

more Write to Buffer c ommands. Additionally, if the

user attempts t o wri te past an erase block boundary

with a Write to Buffer command, the device will

abort programming. This will generate an “Invalid

Command/Sequence” error and status register bits

SR.5 and SR.4 will be set to “1.” To clear SR.4

and/or SR.5, issue a Clear Status Register

command.

Reliable buffered programming can only occur

when VCC = VCC1/2 and VPP = VPPH1/2/3. If

programming is attempted while VPP ≤ V

PPLK,

status register bits SR.4 and SR.5 will be set to “1. ”

Programming attempts with invalid VCC and VPP

voltages produce spurious results and should not

be attempted. Finally, successful programming

requires that the corresponding Block Lock-Bit be

cleared, or WP# = VIH. If a buffered write is

attempted when the corresponding Block Lock-Bit

is set and WP# = VIL, SR.1 and SR.4 will be set to

“1.”

4.9 Byte/Word Program Commands

Byte/Word programming is executed by a two-cycle

command sequence. Byte/Word Program setup

(standard 40H or alternate 10H) is written, followed

by a second write that specifies the address and

data (latched on the ri si ng edge of WE#). The WSM

then takes over, controlling the program and verify

algorithms internally. After the write sequence is

written, the device automatically outputs status

completion of the program event by analyzing STS

in level RY/BY# mode or status register bit SR.7.

When programming is complete, status register bit

SR.4 should be checked. If a programming error is

detected, the st atus regis ter should be c leared. The

internal WSM verif y only detect s errors for “1”s that

do not successfully program to “0”s. The CUI

remains in read status register mode until it

receives another command. Refer to Figure 7 for

the

Single Word/Byte Program Flowchart

Also, Reliable byte/word programming can only

occur when VCC = VCC1/2 and V PP = VPPH1/2/3. In the

absence of thi s high v olt age, c ontent s are prot ect ed

against programming. If a byte/word program is

E28F160S3/28F320S3

PRELIMINARY

attempted while VPP ≤ V

PPLK, status register bits

SR.4 and SR.3 will be set to “1.” Successful

byte/word programming requires that the

corresponding block lock-bit be cleared. If a

byte/word program is attempted when the

corresponding block lock-bit is set and WP# = VIL,

SR.1 and SR.4 will be set to “1.”

4.10 STS Configuration Command

The Status (STS) pin can be c onfigured to different

states using the STS pin Configuration command.

Once the STS pin has been configured, it remains

in that configuration until another configuration

command i s issued or RP # is low. Ini tially, the ST S

pin defaults to level RY/BY# operation where STS

low indicates that the state machine is busy. STS

high indicates that the state machine is ready for a

new operation or suspended.

To reconfigure t he Status (STS) pin to other modes,

the STS pin Configuration command is issued

followed by the desired configuration code. The

three alternate conf igurations are all pulse mode for

use as a system interrupt as described in Table 14.

For these configurations, bit 0 controls Erase

Complete interrupt pulse, and bit 1 controls Write

Complete interrupt pulse. When the device is

configured in one of the pulse modes, the STS pin

pulses low with a typical pulse width of 250 ns.

Supplying the 00h configuration code with the

Configuration command resets the STS pin to the

default RY/BY# level mode. Refer to Table 14 for

configuration coding definitions. The Configuration

command may only be giv en when the dev ice i s not

busy or suspended. Check SR.7 for device status.

An invalid configuration code will result in both

status register bits SR.4 and SR.5 being set to “1.”

4.11 Block Erase Suspend

Command

The Block Erase Suspend command allows

block-erase interruption to read or program data in

another block of memory. Once the block erase

process starts, writing the Block Erase Suspend

command requests that the WSM suspend the

block erase sequence at a predetermined point in

the algorithm. The device outputs status register

data when read after the Block Erase Suspend

command is written. Polling status register bit

SR.7 can determine when the bl ock erase operati on

has been sus pended. When SR.7 = 1, SR. 6 should

also be set to “1, ” indic ati ng that t he devic e is i n t he

erase suspend mode. STS in level RY/BY# mode

will also transition to VOH. Specification tWHRH2

defines the block erase suspend latency.

At thi s point , a Read A rray c omm and can be writ ten

to read data from blocks other than that which is

suspended. A Program command sequence can

also be issued during erase suspend to program

data in other blocks. Using the Program Suspend

command (see Section 4.12), a program operation

can also be suspended. Duri ng a program operation

with block erase suspended, status register bit

SR.7 will return to “0” and STS in RY/BY# mode will

transition to VOL. However, SR.6 will remain “1” to

indicate block erase suspend status.

The only other v alid c omm ands whil e bloc k erase is

suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status

and STS in RY/BY# mode will return to VOL. After

the Erase Resume command is written, the device

automatically outputs status register data when

read (see Figure 10). VPP must remain at VPPH1/2/3

and VCC must remain at VCC1/2 (the same VPP and

VCC levels used for block erase) while block erase

is suspended. RP# must also remain at VIH (the

same RP# level used for block erase). Block erase

cannot resume until program operations initiated

during block erase suspend have completed.

4.12 Program Suspend Command

The Program Suspend command allows program

interruption to read data in other flash memory

locations. Once the programming process starts,

writing the Program Suspend command requests

that the WSM suspend the program sequence at a

predetermined point in the algorithm. The device

continues to output status register data when read

after the Program Suspend command is written.

Polling status register bits SR.7 can determine

when the programming operation has been

suspended. When SR.7 = 1, SR.2 should also be

set to “1”, indicating that the device is in the

program suspend mode. STS in level RY/BY#

mode will also transition to VOH. Specification

tWHRH1 defines the program suspend latency.

28F160S3/28F320S3 E

28 PRELIMINARY

At thi s point , a Read A rray c omm and can be writ ten

to read data from locations other than that whi ch is

suspended. The only other valid commands while

programming is suspended are Read Status

Resume command is written, the WSM will

continue the programming process. Status register

bits SR.2 and SR.7 will automatically cl ear and STS

in RY/BY# mode will return to VOL. After the

Program Resume command is written, the device

automatically outputs status register data when

read. VPP must remain at VPPH1/2/3 and VCC must

remain at V CC1/2 (the same VPP and VCC levels used

for programming) while in program suspend mode.

RP# must also remain at VIH (the same RP# level

used for programming). Refer to Figure 8 for the

Program Suspend/Resume Flowchart

4.13 Set Block Lock-Bit Command

A flexible block locking and unlocking scheme is

enabled via a combination of block lock-bits. The

block lock-bits gate program and erase operations.

With WP# = VIH, individual block lock-bits can be

set using the Set Block Lock-Bit command.

Set block lock-bit is initiated using a two-cycle

command sequence. The Set Block Lock-Bit setup

along with appropriate block or device address is

written followed by the Set Block Lock-Bit Confirm

and an address within the block to be locked. The

WSM then controls the set lock-bit algorithm. After

the sequence is written, the device automatically

outputs status register data when read. The CPU

can detect the completion of the set lock-bit event

by analyzing STS in level RY/BY# mode or status

When the set lock-bit operation is complete, status

detected, the st atus regis ter should be c leared. The

CUI will remain in read status register mode until a

new command is issued.

This two-step sequence of setup followed by

execut ion ensures t hat loc k-bi ts are not ac ci dentall y

set. An invalid Set Block Lock-Bit command will

result in status register bits SR.4 and SR.5 being

set to “1.” Also, reli able operations occ ur only when

VCC = VCC1/2 and V PP = VPPH1/2/3. In the absenc e of

these voltages, lock-bit contents are protected

against alteration.

A successful set block lock-bit operation requires

that WP# = VIH. If it is attempted with WP# = VIL,

the operation will fail and S R.1 and SR.4 will be set

to “1.” See Tabl e 13 f o r wri t e protecti on al ternativ es.

Refer to Figure 11 for the

Set Block Lock-Bit

Flowchart.

4.14 Clear Block Lock-Bits

Command

All set block lock-bits are cleared in parallel via the

Clear Block Lock-Bits command. This command is

valid only when WP# = VIH.

The clear block lock -bits operation is initiat ed using

a two-cycle command sequence. A Clear Block

Lock-Bits setup command is written followed by a

Confirm command. Then, the device automatically

outputs status register data when read (see Figure

12). The CPU can detect completion of the clear

block lock-bits event by analyzing STS in level

RY/BY# mode or status register bit SR.7.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block

Lock-Bits command sequence will result in status

reliable clear block lock-bits operation can only

occur when VCC = VCC1/2 and VPP = VPPH1/2/3. If a

clear block lock-bits operation is attempted while

VPP ≤ VPPLK, SR.3 and S R. 5 will be set to “1. ” In t he

absence of these voltages, the block lock-bits

contents are protected against alteration. A

successful clear block lock-bits operation requires

that WP# = VIH.

If a cl ear block loc k-bits operati on is aborted due t o

VPP or VCC transit ioning out of val id range or RP# or

WP# active transition, block lock-bit values are left

in an undetermined state. A repeat of clear block

lock-bits is required to initialize block lock-bit

contents to known values.

When the operation is complete, status register bit

SR.5 should be checked. If a clear block lock-bit

error is detected, the status register should be

cleared. The CUI will remain in read status register

mode until another command is issued.

E28F160S3/28F320S3

PRELIMINARY

Table 13. Write Protection Alternatives

Operation Block

Lock-

Bit WP# Effect

Program and 0 VIL or VIH Block erase and programming enabled

Block Erase 1 VIL Block is locked. Block erase and programming disabled

VIH Block lock-bit override. Block erase and programming enabled

Full Chip Erase 0,1 VIL All unlocked blocks are erased

IH Block lock-cit override. All blocks are erased

Set or Clear X VIL Set or clear block lock-bit disabled

Block Lock-Bit VIH Set or clear block lock-bit enabled

Table 14. Configuration Coding Definitions

Reserved Pulse on

Write

Complete

Pulse on

Erase

Complete

bits 7–2 bit 1 bit 0

DQ7–DQ2 = Reserved

DQ1/DQ0 = STS Pin Configuration Codes

00 = default, level mode RY/BY#

(device ready) indication

01 = pulse on Erase complete

10 = pulse on Flash Program complete

11 = pulse on Erase or Program Complete

Configuration Codes 01b, 10b, and 11b are all pulse

mode such that the STS pin pulses low then high

when the operation indicated by the given

configuration is completed.

Configuration Command Sequences for STS pin

configuration (masking bits D7–D2 to 00h) are as

follows:

Default RY/BY# level mode B8h, 00h

ER INT (Erase Interrupt): B8h, 01h

Pulse-on-Erase Complete

PR INT (Program Interrupt): B8h, 02h

Pulse-on-Flash-Program Complete

ER/PR INT (Erase or Program Interrupt): B8h, 03h

Pulse-on-Erase or Program Complete

DQ7–DQ2 are reserved for future use.

default (DQ1/DQ0 = 00) RY/BY#, level mode

—used to control HOLD to a memory controller to

prevent accessing a flash memory subsystem while

any flash device's WSM is busy.

configuration 01 ER INT, pulse mode(1)

—used to generate a system interrupt pulse when

any flash device in an array has completed a block

erase or sequence of queued block erases. Helpful

for reformatting blocks after file system free space

reclamation or ‘cleanup’

configuration 10 PR INT, pulse mode(1)

—used to generate a system interrupt pulse when

any flash device in an array has complete a

program operation. Provides highest performance

for servicing continuous buffer write operations.

configuration ER/PR INT, pulse mode(1)

—used to generate system interrupts to trigger

servicing of flash arrays when either erase or flash

program operations are completed when a common

interrupt service routine is desired.

NOTE:

1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.

28F160S3/28F320S3 E

30 PRELIMINARY

Table 15. Status Register Definition

WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R

76543210

NOTES:

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

Check STS in RY/BY# mode or SR.7 to determine

block erase, programming, or lock-bit configuration

completion. SR.6-0 are invalid while SR.7 = “0.”

SR.6 = ERASE SUSPEND STATUS

1 = Block erase suspended

0 = Block erase in progress/completed

SR.5 = ERASE AND CLEAR LOCK-BITS STATUS

1 = Error in block erasure or clear lock-bits

0 = Successful block erase or clear lock-bits

If both SR.5 and SR.4 are “1”s after a block erase

or lock-bit configuration attempt, an improper

command sequence was entered.

SR.4 = PROGRAM AND SET LOCK-BIT

STATUS

1 = Error in program or block lock-bit

0 = Successful program or set block lock-bit

SR.3 = VPP STATUS

1 = VPP low detect, operation abort

0 = VPP OK

SR.3 does not provide a continuous indication of

VPP level. The WSM interrogates and indicates the

VPP level only after a block erase, program, or lock-

bit configuration operation. SR.3 reports accurate

feedback only when VPP = VPPH1/2/3.

SR.2 = PROGRAM SUSPEND STATUS

1 = Program suspended

0 = Program in progress/completed

SR.1 = DEVICE PROTECT STATUS

1 = Block Lock-Bit and/or

WP# lock detected, operation abort

0 = Unlock

SR.1 does not provide a continuous indication of

block lock-bit values. The WSM interrogates the

block lock-bit, and WP# only after a block erase,

program, or lock-bit configuration operation. It

informs the system, depending on the attempted

operation, if the block lock-bit is set.

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS SR.0 is reserved for future use and should be

masked when polling the status register.

Table 16. Extended Status Register Definition

WBS R R R R R R R

76543210

NOTES:

XSR.7 = WRITE BUFFER STATUS

1 = Write to buffer available

0 = Write to buffer not available

After a Write to buffer command, XSR.7 indicates

that another Write to buffer command is possible.

XSR.6-0 = RESERVED FOR FUTURE

ENHANCEMENTS SR.6–0 are reserved for future use and should be

masked when polling the status register

E28F160S3/28F320S3

PRELIMINARY

Start

Write Word or Byte

Count, Block Address

Write Buffer Data,

Start Address

X = 0

X = X + 1

Write Next Buffer Data,

Device Address

Abort Buffer Write

Command?

Check

X = N?

Another Buffer

Write?

Read Status Register

SR.7 =

Buffer Write to

Flash Complete

Read Extended

Status Register

XSR.7 =

Yes

Buffer Write to

Flash Aborted

Yes

Full Status

Check if Desired

Buffer Write to Flash

Confirm D0H

Issue Write Command

E8H, Block Address

Write to Another

Block Address

Write

Buffer Time-Out?

Set Time-Out

Issue Read

Status Command

Yes

Bus

Operation Command Comments

Write Write to

Buffer Data = E8H

Block Address

Read XSR. 7 = Valid

Addr = X

Standby Check XSR. 7

1 = Write Buffer Available

0 = Write Buffer Not Available

Write

(Note 1, 2)

Data = N = Word/Byte Count

N = 0 Corresponds to Count = 1

Addr = Block Address

Write

(Note 3, 4) Data = Write Buffer Data

Addr = Device Start Address

Write

(Note 5, 6) Data = Write Buffer Data

Addr = Device Address

Write Buffer Write

to Flash

Confirm

Data = D0H

Addr = X

Read

Status Register Data with the

Device Enabled, OE# Low

Updates SR

Addr = X

Standby Check SR.7

1 = WSM Ready

0 = WSM Busy

1. Byte or word count values on DQ

-DQ

are loaded into the

count register. Count ranges on this device for byte mode are

N = 00H to 1FH and for word mode are N = 0000H to 000FH.

2. The device now outputs the status register when read (XSR is

no longer available).

3. Write Buffer contents will be programmed at the device start

address or destination flash address.

4. Align the start address on a Write Buffer boundary for

maximum programming performance (i.e., A

- A

of the start

address = 0).

5. The device aborts the Write to Buffer command if the current

address is outside of the original block address.

6. The status register indicates an "improper command

sequence" if the Write to Buffer command is aborted. Follow this

with a Clear Status Register command.

Full status check can be done after all erase and write sequences

complete. Write FFH after the last operation to reset the device to

read array mode.

0Suspend Write? Yes

No Suspend

Write Loop

0608_07

Figure 6. Write to Buffer Flowchart

28F160S3/28F320S3 E

32 PRELIMINARY

Start

Write 40H,

Address

Write Data and

Address

Read Status

SR.7 =

Full Status

Check if Desired

Byte/Word

Program Complete

Read Status

(See Above)

Voltage Range Error

Device Protect Error

Programming Error

Byte/Word

Program

Successful

SR.3 =

SR.1 =

SR.4 =

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

Repeat for subsequent programming operations.

SR full status check can be done after each program operation, or

after a sequence of programming operations.

Write FFH after the last program operation to place device in read

array mode.

Bus

Operation

Standby

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed before

full status is checked.

If an error is detected, clear the status register before attempting retry

or other error recovery.

Command

Setup Byte/

Word Program

Byte/Word

Program

Comments

Data = 40H

Addr = Location to Be Programmed

Data = Data to Be Programmed

Addr = Location to Be Programmed

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command Comments

Check SR.3

1 = Programming Voltage Error

Detect

Check SR.4

1 = Programming Error

Read Status Register Data

Standby

Check SR.1

1 = Device Protect Detect

RP# = V

, Block Lock-Bit Is Set

Only required for systems

implemeting lock-bit configuration.

Suspend

Byte/Word

Program

Suspend Byte/

Word Program

Loop

Yes

0608_08

Figure 7. Single Byte/Word Program Flowchart

E28F160S3/28F320S3

PRELIMINARY

Start

Write B0H

Read Status Register

SR.7 =

SR.2 = Programming Completed

Write D0H

Programming Resumed

Write FFH

Read Array Data

Bus

Operation Command Comments

Write Program

Suspend Data = B0H

Addr = X

Read Status Register Data

Addr = X

Standby Check SR.7

1 - WSM Ready

0 = WSM Busy

Standby Check SR.6

1 = Programming Suspended

0 = Programming Completed

Read Read array locations other

than that being programmed.

Write FFH

Read Data Array

Done Reading

Yes

Write Read Array Data = FFH

Addr = X

Write Program

Resume Data = D0H

Addr = X

0608_09

Figure 8. Program Suspend/Resume Flowchart

28F160S3/28F320S3 E

34 PRELIMINARY

Erase Block

Time-Out?

Start

Read

Status Register

SR.7 =

Erase Flash

Block(s) Complete

Full Status

Check if Desired

Suspend Erase

Device Supports

Queuing

Issue Block Queue Erase

Command 28H, Block

Address

Read Extended Status

Is Queue

Available?

XSR.7=

Another

Block

Erase?

Issue Erase Command 28H

Block Address

Read Extended

Status Register

Write Confirm D0H

Block Address

Another

Block

Erase?

Is Queue Full?

XSR.7=

0=Yes

1=No

Yes

1=Yes

Yes

Issue Single Block Erase

Command 20H, Block

Address

0=No

Suspend

Erase Loop

Yes

Write Confirm D0H

Block Address

Set Time-Out

Issue Read

Status Command

Queued Erase Section

(Include this section for compatibility

with future SCS-compliant devices)

Bus

Operation Command Comments

Write Erase Block Data = 28H or 20H

Addr = Block Address

Read XSR.7 = Valid

Addr = X

Standby Check XSR.7

1 = Erase Queue Avail.

0 = No Erase Queue Avail.

Write Erase Block Data = 28H

Addr = Block Address

Read

SR.7 = Valid; SR.6 - 0 = X

With the device enabled,

OE# low updates SR

Addr = X

Standby Check XSR.7

1 = Erase Queue Avail.

0 = No Erase Queue Avail.

Write (Note 1) Erase

Confirm Data = D0H

Addr = X

Read

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Standby Check SR.7

1 = WSM Ready

0 = WSM Busy

1. The Erase Confirm byte must follow Erase Setup when

the Erase Queue status (XSR.7) = 0.

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

Yes

0608_10

Figure 9. Block Erase Flowchart

E28F160S3/28F320S3

PRELIMINARY

Start

Write B0H

Read Status Register

SR.7 =

SR.6 = Block Erase Completed

Read or Program?

Done?

Write D0H

Block Erase Resumed

Write FFH

Read Array Data

Program

Loop

Read Array

Data

Read

Yes

Bus

Operation Command Comments

Write Erase Suspend Data = B0H

Addr = X

Read Status Register Data

Addr = X

Standby Check SR.7

1 - WSM Ready

0 = WSM Busy

Standby Check SR.6

1 = Block Erase Suspended

0 = Block Erase Completed

Write Erase Resume Data = D0H

Addr = X

0608_11

Figure 10. Block Erase Suspend/Resume Flowchart

28F160S3/28F320S3 E

36 PRELIMINARY

Start

Write 60H,

Block/Device Address

Write 01H,

Block/Device Address

Read Status Regist er

SR.7 =

Full Stat us

Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

Repeat for subsequent lock-bit set

Full status check can be done after each lock-bit set operation or

a sequence of lock-bit set

Write FFH after the last lock-bit set operation to place device in

array mode.

Bus

Operation

Standby

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear

full status is

If an error is detected, clear the status register before attempting

or other error

Standby

Command

Set Lo ck-Bit Setup

Set Block Lock-Bit

Confirm

Comments

Data = 60H

Addr = X

Data = 01H

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command Comments

Check SR.3

1 = Programming Voltage Error

Detect

Check SR.1

1 = Device Protect Detect

WP# = VIL

Read Status Regist er

Data (See Above)

Voltage Range Error

Device Protect Error

SR.3 =

SR. 1 =

Command Sequence

Error

SR.4,5 = 1

Set Lock-Bit ErrorSR.4 = 1

Read Status Register Data

Standby Check SR.4, 5

Both 1 = Command

Error

Standby Check SR.4

1 = Set Lock-Bit Error

Set Lock-Bit

Successful

0608_12

Figure 11. Set Block Lock-Bit Flowchart

E28F160S3/28F320S3

PRELIMINARY

Start

Write 60H

Write D0H

Read Status Register

SR.7 =

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

Write FFH after the clear block lock-bits set operation to place device

in read array mode.

Bus

Operation

Standby

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

If an error is detected, clear the status register before attempting retry

or other error recovery.

Standby

Command

Clear Block Lock-

Bits Setup

Clear Block

Lock-Bits Confirm

Comments

Data = 60H

Addr = X

Data = D0H

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command Comments

Check SR.3

1 = Programming Voltage Error

Detect

Check SR.1

1 = Device Protect Detect

WP# = V

Read Status Register

Data (See Above)

Voltage Range Error

Device Protect Error

SR.3 =

SR. 1 =

Command Sequence

Error

SR.4,5 = 1

Clear Block Lock-Bits

Error

SR.5 = 1

Read Status Register Data

Standby Check SR.4, 5

Both 1 = Command Sequence

Error

Standby Check SR.5

1 = Clear Block Lock-Bits Error

Clear Lock-Bits

Successful

0608_13

Figure 12. Clear Block Lock-Bits Flowchart

28F160S3/28F320S3 E

38 PRELIMINARY

5.0 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control

Intel provides three control inputs to accommodate

multiple memory connections: CEX# (CE0#, CE1#),

OE#, and RP#. Three-line control provides for:

a. Lowest possible memory power dissipation;

b. Data bus contention avoidance.

To use these control inputs efficiently, an address

decoder should enable CEx# while OE# should be

connected to all memory devices and the system’s

READ# cont rol line. Thi s assures that only select ed

memory devices have active outputs, while de-

selected memory devices are in standby mode.

RP# should be connected to the system

POWERGOOD signal to prevent unintended writes

during system power transitions. POWERGOOD

should also toggle during system reset.

5.2 STS and WSM Polling

STS is an open drain output that should be

connected to VCC by a pull-up resistor to provide a

hardware form of detecting block erase, program,

and lock-bit configuration completion. In default

mode, it transitions low during execution of these

commands and returns to VOH when the WSM has

finished executing the internal algorithm. For

alternate STS pin configurations, see Section 4.10.

STS can be connected to an interrupt input of the

system CPU or controller. It is active at all times.

STS, in default mode, is also VOH when the device

is in block erase suspend (with programming

inactive) or in reset/power-down mode.

5.3 Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. Standby current

levels, active current levels and transient peaks

produced by falling and rising edges of CEX# and

OE# are areas of interest. Two-line control and

proper decoupling capacitor selection will suppress

transient voltage peaks . Each dev ice s hould have a

0.1 µF ceramic capacitor connected between its

VCC and GND and VPP and GND. These high-

frequency, low-inductance capacitors should be

placed as close as possible to package leads.

Additionally, for every eight devices, a 4.7 µF

electrol ytic capacit or should be placed at the array’s

power supply connection between VCC and GND.

The bulk capacitor will overcome voltage slumps

caused by PC board trace inductance.

5.4 VPP Trace on Printed Circuit

Boards

Updating target-system resident flash memories

requires that the printed circuit board designer pay

attention to VPP power supply traces. The VPP pin

supplies the memory cell current for programming

and block erasing. Use similar trace widths and

layout considerations given to the VCC power bus.

Adequate VPP supply traces and decoupling will

decrease VPP voltage spikes and overshoots.

5.5 VCC, VPP, RP# Transitions

Block erase, program, and lock -bit c onfi guration are

not guaranteed if RP# ≠ VIH, or if VPP or VCC fall

outside of a valid voltage range (VCC1/2 and

VPPH1/2/3). If VPP error is detected, st at us register bi t

SR.3 and SR.4 or SR.5 are set to “1.” If RP#

transitions to VIL during block erase, program, or

lock-bit configuration, STS in level RY/BY# mode

will remain low until the reset operat ion is c omplete.

Then, the operation will abort and the device will

enter deep power-down. Because the aborted

operation may leave data partially altered, the

command s equence must be repeated aft er normal

operation is restored.

5.6 Power-Up/Down Protection

The device offers protection against accidental

block erase, programming, or lock-bit configuration

during power transitions.

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is

active. Since both WE# and CEX# mus t be low f or a

command wri te, dri vi ng either i nput s ignal t o VIH will

inhibit writes. The CUI’s two-step command

sequence architecture provides an added level of

protection against data alteration.

In-system block lock and unlock renders additional

protection during power-up by prohibiting block

erase and program operations. RP# = VIL disables

the device regardless of its control inputs states.

E28F160S3/28F320S3

PRELIMINARY

6.0 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

Temperature under Bias.........................................

Commercial................................. 0 °C to 70 °C

Extended............................... –40 °C to +85 °C

Storage Temperature................. –65 °C to +125 °C

Voltage On Any Pin

(except VCC and VPP )

..................................–0.5 V to + VCC +0.5 V(1)

VCC Supply Voltage ..........–0.2 V to + VCC+0.5 V(1)

VPP Update Voltage during

Block Erase, Flash Write, and

Lock-Bit Configuration ......... –0.2 V to +7.0 V(2)

Output Short Circuit Current.....................100 mA(3)

NOTICE: This datasheet contains preliminary information

on new products in production. The specifications are

subject to change without notice. Verify with your local

Intel Sales office that you have the latest datasheet before

finalizing a design.

*WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These

are stress ratings only. Operation beyond the “Operating

Conditions” is not recommended and extended exposure

beyond the “Operating Conditions” may affect device

reliability

NOTES:

1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC and

VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output

pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.

2. Maximum DC voltage on VPP may overshoot to +7.0 V for periods <20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. Operating temperature is for extended product defined by this specification.

6.2 Operating Conditions

Table 17. Temperature and VCC Operating Conditions(1)

Symbol Parameter Notes Min Max Unit Test Condition

TAOperating Temperature

Commercial 0 +70 °C Ambient Temperature

Extended –40 +85 °C Ambient Temperature

VCC1 VCC Supply Voltage (2.7 V to 3.6 V) 2.7 3.6 V

VCC2 VCC Supply Voltage (3.3 V ± 0.3 V) 3.0 3.6 V

NOTES:

1. Device operations in the VCC voltage ranges not covered in the table produce spurious results and should not be

attempted.

28F160S3/28F320S3 E

40 PRELIMINARY

6.3 Capacitance(1)

TA = +25°C, f = 1 MHz

Symbol Parameter Typ Max Unit Condition

CIN Input Capacitance 6 8 pF VIN = 0.0 V

COUT Output Capacitance 8 12 pF VOUT = 0.0 V

NOTE:

1. Sampled, not 100% tested.

6.4 DC Characteristics

TA = –40 °C to +85 °C (Extended) and TA = 0 °C to +70 °C (Commercial)

Sym Parameter Notes Typ Max Unit Conditions

ILI Input Load Current 1 ±0.5 µAV

CC = VCC1/2 Max

VIN = VCC1/2 or GND

ILO Output Leakage Current 1 ±0.5 µAV

CC = VCC1/2 Max

Vout = VCC1/2 or GND

ICCS VCC Standby Current 1,3,7 20 100 µA CMOS Inputs

VCC = VCC1/2 Max

CEX# = RP# = VCC ± 0.2 V

1 4 mA TTL Inputs

VCC = VCC1/2 Max

CEX# = RP# = VIH

ICCD VCC Deep Power-Down

Current 16-Mb Commercial

Temperature 115µA RP# = GND ± 0.2 V

IOUT (RY/BY#) = 0 mA

16-Mb Extended

Temperature 120µA RP# = GND ± 0.2 V

IOUT (RY/BY#) = 0 mA

32-Mb Commercial

Temperature 120µA RP# = GND ± 0.2 V

IOUT (RY/BY#) = 0 mA

32-Mb Extended

Temperature 1 TBD µA RP# = GND ± 0.2 V

IOUT (RY/BY#) = 0 mA

ICCR VCC Read Current 1,6,7 25 mA CMOS Inputs

VCC = VCC1/2 Max

CEX# = GND

f = 5 MHz, IOUT = 0 mA

30 mA TTL Inputs

VCC = VCC1/2 Max

CEX# = VIL

f = 5 MHz, IOUT = 0 mA

E28F160S3/28F320S3

PRELIMINARY

6.4 DC Characteristics (Continued)

TA = –40 °C to +85 °C (Extended) and TA = 0 °C to +70 °C (Commercial)

Sym Parameter Notes Typ Max Unit Conditions

ICCW VCC Programming and Set

Lock-Bit Current 1,8 17 mA VPP = VPPH1/2/3

ICCE VCC Block Erase or Clear

Block Lock-Bits Current 1,8 17 mA VPP = VPPH1/2/3

ICCWS

ICCES

VCC Program Suspend or

Block Erase Suspend Current 1,2 1 6 mA CEX# = VIH

IPPS VPP Standby or VPP Read 1 ± 2 ± 15 µA VPP ≤ VCC

IPPR Current 10 200 µA VPP ≥ VCC

IPPD VPP Deep Power-Down

Current 1 0.1 5 µA RP# = GND ± 0.2 V

IPPW VPP Program or Set Lock-Bit

Current 1,8 80 mA VPP = VPPH1/2/3

IPPE VPP Block Erase or Clear

Block Lock-Bits Current 1,8 40 mA VPP = VPPH1/2/3

IPPWS

IPPES

VPP Program Suspend or

Block Erase Suspend Current 1 10 200 µA VPP = VPPH1/2/3

28F160S3/28F320S3 E

42 PRELIMINARY

6.4 DC Characteristics (Continued)

TA = –40 °C to +85 °C (Extended) and TA = 0 °C to +70 °C (Commercial)

Sym Parameter Notes Typ Max Unit Conditions

Sym Parameter Notes Min Max Unit Conditions

VIL Input Low Voltage 8 -0.5 0.8 V

VIH Input High Voltage 8 2.0 VCC

+0.5 V

VOL Output Low Voltage 3,8 0.4 V VCC = VCC1/2 Min

IOL = 5.8 mA

VOH1 Output High Voltage (TTL) 3,8 2.4 V VCC = VCC1/2 Min

IOH = –2.5 mA

VOH2 Output High Voltage (CMOS) 3,8 0.85 ×

VCC VV

CC = VCC1/2 Min

IOH = –2.5 mA

VCC –

0.4 VV

CC = VCC1/2 Min

IOH = –100 µA

VPPLK VPP Lockout Voltage 4,8 1.5 V

VPPH1 VPP Voltage 4,5 2.7 3.6 V

VPPH2 VPP Voltage 4,5 3.0 3.6 V

VPPH3 VPP Voltage 4,5 4.5 5.5 V

VLKO VCC Lockout Voltage 9 2.0 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are

valid for all product versions (packages and speeds).

2. ICCWS and ICCES are specified with the device de-selected. If read or programmed while in erase suspend mode, the

device’s current is the sum of ICCWS or ICCES and ICCR or ICCW.

3. Includes STS in level RY/BY# mode.

4. Refer to Figure 13.

5. Refer to

AC Characteristics—Read-Only Operations

. If VCC is in the range from 2.7 V to 3.6 V (VCC1) then VPP must be is in

the range from 2.7 V to 3.6 V (VPPH1) or 4.5 V to 5.5 V (VPPH3). If VCC is in the range from 3.0 V to 3.6 V (VCC2) then VPP

must be is in the range from

3.0 V to 3.6 V (VPPH2) or 4.5 V to 5.5 V (VPPH3).

6. Automatic Power Savings (APS) reduces typical ICCR to 3 mA at 2.7 V and 3.3 V VCC static operation.

7. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.

8. Sampled, not 100% tested.

9. With VCC ≤ VLKO flash memory writes are inhibited.

E28F160S3/28F320S3

PRELIMINARY

PPLK

PPH1/2

(min)

PPH1/2

(max)

PPH3

(min)

PPH3

(max)

In the following ranges

Block erase,

program, and

lock-bit configurations

are:

0 V

not guaranteed

enabled

not guaranteed

enabled

not guaranteed

inhibited

NOTES:

1. Diagram is not to scale

2. VPPLK(max) = 1.5 V

0608_21

Figure 13. Block Erase, Program, and Lock-Bit Configurations under VPP/VCC Voltage Combinations

Table 18. Valid VPP/VCC Voltage Combinations for 28F160/320S3

VCC Voltage VPP Voltage

VCC1 = 2.7 V to 3.6 V VPPH1 = 2.7 V to 3.6 V,

VPPH2 = 3.0 V to 3.6 V, or

VPPH3 = 4.5 V to 5.5 V

VCC2 = 3.0 V to 3.6 V VPPH2 = 3.0 V to 3.6 V or

VPPH3 = 4.5 V to 5.5 V

28F160S3/28F320S3 E

44 PRELIMINARY

OutputTest PointsInput 1.351.35

2.7

0.0

AC test inputs are driven at 2.7 V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at

1.35 V. Input rise and fall times (10% to 90%) <10 ns.

0608_14

Figure 14. Transient Input/Output Reference Waveform for VCC = 2.7 V–3.6 V

OutputTest PointsInput 1.51.5

3.0

0.0

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.

Input rise and fall times (10% to 90%) <10 ns.

0608_15

Figure 15. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V

(High Speed Testing Configuration)

Device

Under Test Out

= 3.3 k

Ω

1N914

1.3 V

0608_16

NOTE: CL Includes Jig Capacitance

Figure 16. Transient Equivalent Testing

Load Circuit

Test Configuration Capacitance Loading Value

Test Configuration CL (pF)

VCC = 3.3 V ± 0.3 V, 2.7 V to 3.6 V 50

E28F160S3/28F320S3

PRELIMINARY

6.5 AC Characteristics—Read-Only Operations(1, 5)

TA = –40 oC to +85 oC (Extended) and TA = 0 °C to +70 °C (Commercial)

Versions(4) 3.3V ± 0.3V VCC 16Mb/32Mb

-75/-110 16Mb/32Mb

-130/-140

(All units in ns unless otherwise noted) 2.7V - 3.6V VCC 16Mb/32Mb

-100/-130 16Mb/32Mb

-150/-160

# Sym Parameter Notes Min Max Min Max Min Max Min Max

R1 tAVAV Read/Write Cycle Time 16 Mbit 1 100 100 130 150

32 Mbit 1 110 130 140 160

R2 tAVQV Address to Output Delay 16 Mbit 1 75 100 130 150

32 Mbit 1 110 130 140 160

R3 tELQV CEX# to Output Delay 16 Mbit 2 75 100 130 150

32 Mbit 2 110 130 140 160

R4 tGLQV OE# to Output Delay 2 45 50 50 55

R5 tPHQV RP# High to Output Delay 600 600 600 600

R6 tELQX CEX# to Output in Low Z 3 0 0 0 0

R7 tGLQX OE# to Output in Low Z 3 0 0 0 0

R8 tEHQZ CEX# High to Output in High Z 3 50 50 55 55

R9 tGHQZ OE# High to Output in High Z 3 20 20 25 25

R10 tOH Output Hold from Address, CEX#, or

OE# Change, Whichever Occurs First 30000

R11 tELFL

tELFH

CEX# Low to BYTE# High or Low 35555

R12 tFLQV

tFHQV

BYTE# to Output Delay 16 Mbit 3 100 120 130 150

32 Mbit 3 110 130 140 160

R13 tFLQZ BYTE# to Output in High Z 3 30 30 40 40

NOTES:

1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.

2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact on tELQV.

3. Sampled, not 100% tested.

4. See

Ordering Information

for device speeds (valid operational combinations).

5. See Figures 14 through 16 for testing characteristics.

28F160S3/28F320S3 E

46 PRELIMINARY

Address Stable

Device

Address Se lection

ADDRESSES (A)

OE# (G)

Data

Valid

Standby

WE# (W)

DATA (D/Q)

(DQ0-DQ15)

High Z Valid Ou tp ut Hig h Z

RP# (P)

R10

R11 R12 R13

BYTE# (F)

CE # (E )

Note: CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.

0608_17

Figure 17. AC Waveform for Read Operations

E28F160S3/28F320S3

PRELIMINARY

6.6 AC Characteristics—Write Operations(1, 5, 6)

TA = –40 oC to +85 oC (Extended) and TA = 0 °C to +70 °C (Commercial)

Versions(5) 3.3 V ± 0.3 V,

2.7 V–3.6 V VCC Valid for All

Speeds

# Sym Parameter Notes Min Max Unit

W1 tPHWL (tPHEL)RP# High Recovery to WE# (CEX#) Going Low 2 1 µs

W2 tELWL CEX# Setup to WE# Going Low 10 ns

(tWLEL)(WE# Setup to CEX# Going Low) 0 ns

W3 tWLWH WE# Pulse Width 50 ns

(tELEH)(CEX# Pulse Width) 70 ns

W4 tDVWH (tDVEH)Data Setup to WE# (CEX# ) Going High 3 50 ns

W5 tAVWH (tAVEH)Address Setup to WE# (CEX# ) Going High 3 50 ns

W6 tWHEH CEX# Hold from WE# High 10 ns

(tEHWH)(WE# Hold from CEX# High) 0 ns

W7 tWHDX (tEHDX)Data Hold from WE# (CEX# ) High 5 ns

W8 tWHAX (tEHAX)Address Hold from WE# (CEX# ) High 5 ns

W9 tWHWL WE# Pulse Width High 30 ns

(tEHEL)(CEX# Pulse Width High) 25 ns

W10 tSHWH (tSHEH)WP# VIH Setup to WE# (CEX# ) Going High 100 ns

W11 tVPWH (tVPEH)VPP Setup to WE# (CEX# ) Going High 2 100 ns

W12 tWHGL (tEHGL)Write Recovery before Read 0 ns

W13 tWHRL (tEHRL)WE# High to STS in RY/BY# Low 100 ns

W14 tQVSL WP# VIH Hold from Valid SRD 2,4 0 ns

W15 tQVVL VPP Hold from Valid SRD, STS in RY/BY# High 2,4 0 ns

NOTES:

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to

AC Characteristics—Read-Only Operations

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.

4. VPP should be at VPPH1/2/3 until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).

5. See

Ordering Information

for device speeds (valid operational combinations).

6. See Figures 14 through 16 for testing characteristics.

28F160S3/28F320S3 E

48 PRELIMINARY

ADDRESSES [A]

DATA [D/Q]

AIN

Valid

SRD

High Z

V [V]

AB C D F

PPH2,1

PPLK

RP# [P]

VIH

STS [R] IH

OE# [G] W1

W10

W11

W16

W13

W12

W14

W15

WP# [S] IH

CE # (WE#) [E(W)]

WE# (CE #) [W(E)]

NOTES:

A. VCC power-up and standby.

B. Write block erase or program setup.

C. Write block erase confirm or valid address and data.

D. Automated erase or program delay.

E. Read status register data.

F. Write Read Array command.

CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.

0608_18

Figure 18. AC Waveform for Write Operations

E28F160S3/28F320S3

PRELIMINARY

RP # (P)

VIH

VIL

STS (R)

VCC1

VCC P3

VIH

VIL

0608_19

Figure 19. AC Waveform for Reset Operation

Table 19. Reset AC Specifications(1)

VCC = 2.7 V VCC = 3.3 V

# Sym Parameter Notes Min Max Min Max Unit

P1 tPLPH RP# Pulse Low Time

(If RP# is tied to VCC, this specification is

not applicable)

100 100 ns

P2 tPLRH RP# Low to Reset during Block Erase,

Program, or Lock-Bit Configuration 2,3 20 20 µs

P3 t3VPH VCC at 2.7 V to RP# High

VCC at 3.0 V to RP# High 50 50 µs

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete

within tPLPH.

3. A reset time, tPHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.

28F160S3/28F320S3 E

50 PRELIMINARY

6.7 Erase, Write, and Lock-Bit Configuration Performance(3, 4)

2.7 V–3.6 V VCC

Version 2.7 V VPP 3.3 V VPP 5 V VPP

# Sym Parameter Note Typ(1) Max(6) Typ(1) Max(6) Typ(1) Max(6) Unit

W16 Byte/word program time

(using write buffer) 5 5.76 TBD 5.76 TBD 2.76 TBD µs

W16 tWHQV1

tEHQV1

Per byte program time

(without write buffer) 2 18.0 160 17.0 150 12.0 100 µs

W16 tWHQV1

tEHQV1

Per word program time

(without write buffer) 2 20.0 190 19.0 180 12.0 100 µs

W16 Block program time

(byte mode) 2 1.2 2.0 1.1 1.7 0.87 1.2 sec

W16 Block program time

(word mode) 2 0.7 1.1 0.6 1.0 0.44 0.6 sec

W16 Block program time

(using write buffer) 2 0.37 TBD 0.37 TBD 0.16 TBD sec

W16 tWHQV2

tEHQV2

Block erase time 2 0.56 6.0 0.35 4.0 0.3 3.5 sec

W16 Full chip erase time 16 Mbit 17.9 192 12.0 128 9.6 112 sec

32 Mbit 35.8 384 24.0 256 19.2 224 sec

W16 tWHQV3

tEHQV3 Set Lock-Bit time 2 20.0 190 19.0 180 12.0 100 µs

W16 tWHQV4

tEHQV4 Clear block lock-bits time 2 0.56 6.0 0.35 4.0 0.3 3.5 sec

W16 tWHRH1

tEHRH1 Program suspend latency

time to read 7.24 10.2 7.24 10.2 6.73 9.48 µs

W16 tWHRH2

tEHRH2 Erase suspend latency time

to read 15.5 21.5 15.5 21.5 12.54 17.54 µs

NOTES:

1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to

change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled but not 100% tested.

5. Uses whole buffer.

6. Maximum values represent less than 1% of units exposed to greater than 100K cycles.

E28F160S3/28F320S3

PRELIMINARY

6.8 Erase, Write, and Lock-Bit Configuration Performance(3, 4)

3.3 V ± 0.3 V VCC

Version 3.3 V VPP 5 V VPP

# Sym Parameter Notes Typ(1) Max Typ(1) Max Units

W16 Byte/word program time

(using write buffer) 5 5.66 TBD 2.7 TBD µs

W16 tWHQV1

tEHQV1 Per byte program time

(without write buffer) 2 19.51 TBD 12.95 TBD µs

W16 tWHQV1

tEHQV1 Per word program time

(without write buffer) 2 21.75 TBD 12.95 TBD µs

W16 Block program time

(byte mode) 2 1.6 TBD 0.85 TBD sec

W16 Block program time

(word mode) 2 0.89 TBD 0.43 TBD sec

W16 Block program time

(using write buffer) 2 0.36 TBD 0.18 TBD sec

W16 tWHQV2

tEHQV2 Block erase time 2 0.55 TBD 0.41 TBD sec

W16 Full chip erase time 16 Mbit 17.6 TBD 13.1 TBD sec

32 Mbit 35.2 TBD 26.2 TBD sec

W16 tWHQV3

tEHQV3 Set Lock-Bit time 2 22.75 TBD 12.95 TBD µs

W16 tWHQV4

tEHQV4 Clear block lock-bits time 2 0.55 TBD 0.41 TBD sec

W16 tWHRH1

tEHRH1 Program suspend latency

time to read 7.1 10 6.6 9.3 µs

W16 tWHRH2

tEHRH2 Erase suspend latency time

to read 15.2 21.1 12.3 17.2 µs

NOTES:

1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to

change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled but not 100% tested.

5. Uses whole buffer.

28F160S3/28F320S3 E

52 PRELIMINARY

7.0 ORDERING INFORMATION

T E 2 8 F 1 6 0 S 3 - 1 0 0

Package

DT = Extended Temp. 56-Lead SSOP

TE = Extended Temp. 56-Lead TSOP

Product Line Designator

for all Intel Flash products

Access Speed (ns)

Product Family

S = FlashFile™ Memory

Device Density

160 = 16 Mbit

320 = 32 Mbit

Device Type

5 = 2.7 V/ 3.3 V V

2.7 V/ 3.3 V/ 5 V V

Order Code by Density Valid Operational Combinations

16 Mb 32 Mb tAVAV/tAVQV

2.7 V-3.6 V VCC

50 pF load

(16 Mb / 32 Mb)

tAVAV/tAVQV

3.3 V ± 0.3 V VCC

50 pF load

(16 Mb / 32 Mb)

TE28F160S3-75 –100 –75

TE28F160S3-100 –120 –100

TE28F160S3-130 –150 –130

DT28F160S3-75 –100 –75

DT28F160S3-100 DT28F320S3-110 –120 / –130 –100 / –110

DT28F160S3-130 DT28F320S3-140 –150 / –160 –130 / –140

E28F160S3/28F320S3

PRELIMINARY

8.0 ADDITIONAL INFORMATION (1,2)

Order Number Document/Tool

290609

5 Volt FlashFile™ Memory;28F160S5 and 28F320S5

datasheet

292204

AP-646 Common Flash Interface and Command Sets

292203

AP-645 3 Volt and 5 Volt FlashFile™ Memory Migration Guide

292163

AP-610 Flash Memory In-System Code and Data Update Techniques

297849

Word-Wide FlashFile™ Memory Family 28F160S3, 28F160S5,

28F320S3, 28F320S5 Specification Update

Note 3

28F016SV 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory

Datasheet

Note 3

28F016SA 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory

Datasheet

Note 3

AP-374 Flash Memory Write Protection Techniques

Note 3

AP-393 28F016SV Compatibility with 28F016SA

Note 3

AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,

Including ROM Capability

www.mcif.com

Common Flash Interface Specification

Contact Intel/Distribution

Sales Office

CFI - Common Flash Interface Reference Code

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

3. These documents can be located at the Intel World Wide Web support site, http://www.intel.com/support/flash/memory