Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but th ere is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
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Notes regar ding these materials
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contained therein.
HM62W4100HC Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-1202C (Z)
Rev. 2.0
Nov. 9, 2001
Description
The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for
high density surface mounting.
Features
• Single supply : 3.3 V ± 0.3 V
• Access time : 10/12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current : 115/100 mA (max)
• TTL standby current : 40 mA (max)
• CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
• Data retention current : 0.6 mA (max) (L-version)
• Data retention voltage: 2 V (min) (L-version)
• Center VCC and VSS type pin out
HM62W4100HC Series
Rev. 2, Nov. 2001, page 2 of 13
Ordering Information
Type No. Access time Device marking Package
HM62W4100HCJP-10
HM62W4100HCJP-12
10 ns
12 ns
HM62W4100CJP10
HM62W4100CJP12
400-mil 32-pin plastic SOJ (CP-32DB)
HM62W4100HCLJP-10
HM62W4100HCLJP-12
10 ns
12 ns
HM62W4100CLJP10
HM62W4100CLJP12
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
A4
I/O1
V
CC
V
SS
I/O2
A5
A6
A7
A8
A9
A19
A18
A17
A16
A15
I/O4
V
SS
V
CC
I/O3
A14
A13
A12
A11
A10
NC
(Top view)
32-pin SOJ
Pin Description
Pin name Function
A0 to A19 Address input
I/O1 to I/O4 Data input/output
CS Chip select
OE Output enable
WE Write enable
VCC Power supply
VSS Ground
NC No connection
HM62W4100HC Series
Rev. 2, Nov. 2001, page 3 of 13
Block Diagram
I/O1
.
.
.
I/O4
Input
data
control
Column I/O
Column decoder
1024-row × 64-column ×
16-block × 4-bit
(4,194,304 bits)
Row
decoder
CS
CS
VCC
VSS
CS
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB) (MSB)
(LSB)
(MSB)
HM62W4100HC Series
Rev. 2, Nov. 2001, page 4 of 13
Operation Table
CS
CSCS
CS OE
OEOE
OE WE
WEWE
WE Mode VCC current I/O Ref. cycle
H × × Standby ISB, ISB1 High-Z —
L H H Output disable ICC High-Z —
L L H Read ICC Dout Read cycle (1) to (3)
L H L Write ICC Din Write cycle (1)
L L L Write ICC Din Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC –0.5 to +4.6 V
Voltage on any pin relative to VSS V
T –0.5*1 to VCC+0.5*2 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC*3 3.0 3.3 3.6 V
V
SS*4 0 0 0 V
Input voltage VIH 2.0 — VCC + 0.5*2 V
V
IL –0.5*1 — 0.8 V
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
HM62W4100HC Series
Rev. 2, Nov. 2001, page 5 of 13
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)
Parameter Symbol Min Typ*1 Max Unit Test conditions
Input leakage current IILII — — 2 µA Vin = VSS to VCC
Output leakage current IILOI — — 2 µA Vin = VSS to VCC
Operation power
supply current
10 ns cycle ICC — — 115 mA Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
12 ns cycle ICC — — 100 mA
Standby power supply current ISB — — 40 mA Min cycle, CS = VIH,
Other inputs = VIH/VIL
I
SB1 — 2.5 5 mA f = 0 MHz
VCC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
—*2 0.5*2 1*2
Output voltage VOL — — 0.4 V IOL = 8 mA
V
OH 2.4 — — V IOH = –4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1 Cin — — 6 pF Vin = 0 V
Input/output capacitance*1 C
I/O — — 8 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
HM62W4100HC Series
Rev. 2, Nov. 2001, page 6 of 13
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
Dout
353Ω
319Ω
3.3 V
5 pF
Output load (B)
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
OW
)
Output load (A)
1.5 V
30 pF
Dout
RL=50 Ω
Zo=50 Ω
Read Cycle
HM62W4100HC
-10 -12
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 10 — 12 — ns
Address access time tAA — 10 — 12 ns
Chip select access time tACS — 10 — 12 ns
Output enable to output valid tOE — 5 — 6 ns
Output hold from address change tOH 3 — 3 — ns
Chip select to output in low-Z tCLZ 3 — 3 — ns 1
Output enable to output in low-Z tOLZ 0 — 0 — ns 1
Chip deselect to output in high-Z tCHZ — 5 — 6 ns 1
Output disable to output in high-Z tOHZ — 5 — 6 ns 1
HM62W4100HC Series
Rev. 2, Nov. 2001, page 7 of 13
Write Cycle
HM62W4100HC
-10 -12
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 10 — 12 — ns
Address valid to end of write tAW 7 — 8 — ns
Chip select to end of write tCW 7 — 8 — ns 9
Write pulse width tWP 7 — 8 — ns 8
Address setup time tAS 0 — 0 — ns 6
Write recovery time tWR 0 — 0 — ns 7
Data to write time overlap tDW 5 — 6 — ns
Data hold from write time tDH 0 — 0 — ns
Write disable to output in low-Z tOW 3 — 3 — ns 1
Output disable to output in high-Z tOHZ — 5 — 6 ns 1
Write enable to output in high-Z tWHZ — 5 — 6 ns 1
Note: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. If CS and OE are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS or WE going low.
7. tWR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginning of write to the end of write.
9. tCW is measured from the later of CS going low to the end of write.
HM62W4100HC Series
Rev. 2, Nov. 2001, page 8 of 13
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
t
AA
t
ACS
t
RC
t
OE
t
CLZ
Valid data
Address
CS
Dout
Valid address
High impedance
t
OHZ
OE
t
OH
t
CHZ
t
OLZ
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
tAA
tRC
Valid data
Address
Dout
Valid address
tOH
tOH
HM62W4100HC Series
Rev. 2, Nov. 2001, page 9 of 13
Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*2
Valid data
CS
Dout High
impedance
High
impedance
tCLZ
tACS
tRC
tCHZ
Write Timing Waveform (1) (WE Controlled)
Address
*
3
Dout
Din
t
WC
t
WP
t
WR
t
CW
t
DW
t
DH
Valid address
t
AW
Valid data
t
AS
*
3
t
OHZ
*
4
*
4
High impedance*
5
HM62W4100HC Series
Rev. 2, Nov. 2001, page 10 of 13
Write Timing Waveform (2) (CS Controlled)
Address
*
3
Dout
Din
t
WC
t
WP
t
WR
t
CW
t
DW
t
DH
Valid address
t
AW
Valid data
t
AS
*
3
t
WHZ
t
OW
*
4
*
4
High impedance*
5
HM62W4100HC Series
Rev. 2, Nov. 2001, page 11 of 13
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter Symbol Min Typ*1 Max Unit Test conditions
VCC for data retention VDR 2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current ICCDR — 300 600 µA VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data
retention time
tCDR 0 — — ns See retention waveform
Operation recovery time tR 5 — — ms
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C, and not guaranteed.
Low VCC Data Retention Timing Waveform
CC
V
3.0 V
0 V
t
CDR
t
R
V
CC
≥ ≥ V
CC
– 0.2 V
2.0 V
DR
V
Data retention mode
HM62W4100HC Series
Rev. 2, Nov. 2001, page 12 of 13
Package Dimensions
HM62W4100HCJP/HCLJP Series (CP-32DB)
20.71
21.08 Max
32 17
116
0.74
10.16 ± 0.13
11.18 ± 0.13
3.50 ± 0.26
*0.43 ± 0.10 9.40 ± 0.25
2.85 ± 0.12
1.30 Max
0.10
1.27
0.80 +0.25
–0.17
0.41 ± 0.08
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
CP-32DB
Conforms
Conforms
1.2 g
*Dimension including the plating thickness
Base material dimension
As of January, 2001
Unit: mm
HM62W4100HC Series
Rev. 2, Nov. 2001, page 13 of 13
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Sales Offices
Hitachi, Ltd.
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
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Tel : <65>-538-6533/538-8577
Fax : <65>-538-6933/538-3877
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URL http://www.hitachisemiconductor.com/
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(Taipei Branch Office)
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Hung-Kuo Building
Taipei (105), Taiwan
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Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
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URL : http://semiconductor.hitachi.com.hk
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Postfach 201, D-85619 Feldkirchen
Germany
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Fax: <49> (89) 9 29 30 00
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For further information write to:
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