HM514258A Series 262,144-Word X 4-Bit CMOS Dynamic RAM @ DESCRIPTION The Hitachi HM514258A is a CMOS dynamic RAM organized 262144-word x 4-bit. HM514258A has realized higher density, higher performance and various func- tions by employing 1.3 um CMOS technology and some new CMOS circuit design technologies. The HM514258A offers Static Column Mode as a high speed access mode. Multiplexed address input permits the HM514258A to be packaged in standard 20-pin plastic DIP, 20-pin plastic SOU and 20-pin plastic ZIP. @ FEATURES Single 5V (+ 10%) e High Speed Access Time .......--.-. 0c eee eee 60 ns/70 ns/80 ns/100 ns/120 ns (max) Low Power Standby ........ 0... e cece cece e renee teen es 14 mW (max) Active ..............0. 495 mW/440 mW/413 mW/358 mW/303 mW (max) Static Column Mode Capability 512 Refresh Cycles 0.0.0... ccc cece enn erent e een en eenes (8 ms) * 2 Variations of Refresh RAS Only Refresh CS Before RAS Refresh @ ORDERING INFORMATION HMS514258AP Series S3DDP20NA (DP-20NA) HMS514258AJP Series (CP-20D) gOCP20D HMS514258AZP Series Part No. Access Time Package HMS514258AP-6 60 ns HMS514258AP-7 70 ns 300 mi! 20-pin HMS14258AP-8 80 ns Plastic DIP HM514258AP-10 100 ns (DP-20NA) HM514258AP-12 120 ns spze20 HM514258AJP-6 60 ns (ZP-20) HMS514258AJP-7 70 ns 300 mil 20-pin HMS14258AJP-8 80 ns Plastic SOJ @ PIN DESCRIPTION HMS514258AJP-10 100 ns (CP-20D) - - HM514258AJP-12 120 ns Pin Name Function HMS514258AZP-6 60 ns Ao-Ag Address Input HMS514258AZP-7 70 ns 400 mil 20-pin Ag-Ag Refresh Address Input HM514258AZP-8 80 ns Plastic ZIP HM514258AZP-10 100 ns (ZP-20) 1/09-1/04 Data Input/Data Output HM514258AZP-12 120 ns RAS Row Address Strobe PIN OUT Ss Chip Seleet - WE Write Enabie HM514258AP Series HM514258AJP Series HM514258AZP Series OE Output Enable Hitachi Pin No. 1 OE 20] } vs JEDEC Pin No. S2 + os Voc Power Supply (+ 5V) s{_] 0s oe 4 Vss Ground Sif fi20 Ves vo. 6i=y iy Jes 25gD19 L/O | 7 W402 oE WE 8Fq OE 2a| ia os a 6H 2a{fhiz 5 Ne old 9 RAS is[ Tas 2et[)16 OE rf a0 i] Al 1257 af} a7 y | he is[_Jas A3 144 Lf reipis as ce i 17{flla az A4 16 AS uf ja 16/13 a6 AG 18 1s] 12 as aT ral fpur ae AS 20 0114-1 (Top View) o11a-2 ont (Top View) (Bottom View) Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 59HM514258A Series @ BLOCK DIAGRAM RAS cs RAS Controi B Contra WE Control OE Contra! Circuit Circuit Circuit Circuit 1/01 1/02 1/03 1/04 a a 1/0 Butter 1/0 Buffer | a} [a a} (a 5 of & Jo ~ a Sg} E48 ala spe iF 8 S| 256k fs] S jal 256K |S] 256m 4) S 18) 256k 2 Z| Memory a ; a Memory [Z{=| Memory S| 5 Ja] Memory [~ al cel z| 8 iz} ce e[81 cell &| 8 2} cen z | Array [2] & fT] Array <]S| Array a} Jal Array 8 2 e 2. ale El c JE # 2 gle ie SIs <i |< 3 a < BIA = 8 gla lg 3 3 a 218 s & & a a Word Driver Word Driver Word Driver Row Decoder Row Decoder Row Address Bufter Calumn Address Buffer 0114-4 @ HITACHI 60 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300@ ABSOLUTE MAXIMUM RATINGS HN514258A Series Parameter Symbol Value Unit Voltage on Any Pin Relative to Vss Vr 1.0to +7.0 Vv Supply Voltage Relative to Vs Voc 10tc +7.0 v Short Circuit Output Current Tout 50 mA Power Dissipation Py 1.0 WwW Operating Temperature Topr Oto +70 c Storage Temperature Tstg 55to +125 C @ ELECTRICAL CHARACTERISTICS Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Symbol Min Typ Max Unit Note Vss 0 0 0 Vv Supply Voltage Vec 45 5.0 5.5 Vv 1 Input High Voltage Vin 2.4 6.5 Vv 1 Input Low 1/0 Pin Vit 1.0 _ 0.8 Vv 1 Voltage Others VIL 20 0.8 Vv 1 Note: 1. All voltage referenced to Vss. * DC Electrical Characteristics (Ta = 0 to + 70C, Voc = 5V +10%, Vss = OV) HM514258A | HM514258A | HM514258A | HM514258A | HM514258A Parameter Symbol] 6 a 8 10 712 Unit} Test Conditions | Note Min | Max | Min | Max | Min | Max] Min | Max | Min | Max . RAS, CS Cycling Operating Current |Icc _ 90 _ 80 _- 75 _ 65 _ 55 |mA trc = Min 1,2 TTL Interface _ 2 _ 2 - 2 _ 2 _ 2 |mA|RAS, CS = Vox, Dout = High-Z Standby Current Icc2 = CMOS Interface, RAS, _ 1 1 _ i _ 1 _ 1 |mA|CS 2 Vcc 0.2V, Dour = High-Z RAS Only = Mj Refresh Current Iec3 _ 90 _ 80 _ 75 - 65 _ 55 |mA|tpc = Min 2 RAS = Vin Standby Current Iocs _ 5 _ 5 _ 5 _ 5 5 |mAICS = Viz, 1 Dout = Enable CS Before RAS =v Refresh Current Ioce _ 80 _ 70 65 _ 55 _ 45 |mA|trc = Min Static Column MG Mode Current Iceco - 80 - 70 _ 65 - 55 _ 45 |mA|tsc = Min 1,3 Input Leakage = jy ~10/ 10 | -10| 10 | -10| 10 | -10} 10 | -10] 10 |pAlov s Vin < 7V Current Li He om Output Leakage _ _ _ _ _ OV S Vout 3 7V, Current ILo 10] 10 10} 10 10] 10 10} 10 10} 10 | pA Dout = Disable Output High Voltage|/ Vou 2.4 Vee 2.4 Voc 2.4 Vcc 2.4 Voc 2.4 Veco | Vv High Inu, = 5 mA Output Low Voltage | VoL 0 0.4 0 0.4 0 0.4 0.4 0 0.4 | V {Low Ipy: = 4.2 mA Notes: 1. Icc depends on output load condition when the device is selected. Loc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = Viz- 3. Address can be changed once or less while CS = Vyp. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 61HM514258A Series Capacitance (Ta = 25C, Vcc = 5V +10%) Parameter Symbol Typ Max Unit Note Input Capacitance (Address) Cy _ 5 pF 1 Input Capacitance (Clocks) Cp _ 7 pF 1 Input/Output Capacitance (Data Input, Data Output) Cyo 10 pF 1,2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CS = Vyy to disable Dout. AC Characteristics (T, = 0 to +70C, Voc = 5V +10%, Vsg = OV)I7, 18 Test Conditions Input Rise and Fall Times: 5 ns input timing reference levels: 0.8V, 2.4V Output load: 2 TTL Gate + C, (100 pF) {Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) HMS514258A HM514258A HM514258A | HM514258A HMS514258A Parameter Symbol -6 -7 -& -10 -12 Unit | Note Min Max Min Max Min | Max | Min | Max | Min Max Random Read or Write Cycle Time | tre 120 _ 130 _ 160 _ 190 _ 220 _ ns RAS Precharge Time trp 50 50 70 80 90 | os RAS Pulse Width tRAS 60 10000 70 10000 80 | 10000} 100 | 10000) 120 | 10000] ns CS Pulse Width tsp 20 10000 20 10000 25 10000] 30 | 10000} 30 10000 | ns Row Address Setup Time tasR 0 _ 0 _ 0 _ 0 _ 0 _ ns Row Address Hold Time tRAH 10 _ 10 _ 12 15 _ 15 ns Column Address Setup Time tasw 0 _ 0 _ 0 _ 0 _ 0 _ ns Column Address Hold Time taHw 15 ~_ 15 _ 20 _ 25 _ 25 ns RAS to CS Delay Time trop 20 40 20 50 22 55 25 70 25 90 os | 8 RAS Hold Time trsi 20 _ 20 25 30 30 | os CS Hold Time tcsH 60 _ 70 80 _ 100 _ 120 _ ns CS to RAS Precharge Time tsps 10 10 _ 10 10 10 | as OE to Din Delay Time topp 20 20 ~ 20 ~_ 25 30 | ns OE Delay Time from Din tpzo 0) _ 0 0 _ 0 _ i) | os CS Delay Time from Djn tozc 0 _ 0 _ 0 _ 0 _ 0 _ ns Transition Time (Rise and Fal!) ty 3 50 3 50 3 50 3 50 3 50 ns | 1,7 Refresh Period. tREF _ 8 _ 8 _ 8 _ 8 _ 8 ms Read Cycle HMS514258A HMS514258A HM514258A | HM514258A HMS14258A. Parameter Symbol -6 7 8 -10 -12 Unit! Note Min Max Min Max Min | Max | Min | Max | Min Max Access Time from RAS tRAc _ 60 _ 70 80 _ 100 | 120 | ns | 2,3 Access Time from CS tacs _ 20 _ 20 25 30 _ 30 ns | 3,4 Access Time from Address tAA _ 30 _ 35 _ 40 _ 30 _ 55 ns }3,5, 14 Access Time from OE toac _ 20 _ 20 _ 25 _ 25 _ 30 ns Read Command Setup Time trcs 0 _ 0 _ 0 _ 0 _ 0 _ ns Read Command Hold Time toCS | troy 0 0 0 0 _ 0 ~ ns Read Command Hold Time to RAS| tra 10 10 10 _ 10 10 ns @ HITACHI 62 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300Read Cycle (continued) HM514258A Series HMS514258A HMS514258A | HM514258A | HM514258A | HM514258A Parameter Symbol -6 7 8 -10 -12 Unit| Note Min | Max | Min | Max | Min | Max | Min | Max | Min | Max RAS to Column Address Hold Time |tanr 15 _ 15 _ 15 _ 15 15 _ ns | 16 RAS to Column Address Delay Time |tpap 15 30 15 35 17 40 20 50 20 65 ns | 9 Column Address to RAS Lead Time |trat 30 _ 35 _ 40 50 55 ns Column Address Hold Time from RAS|tar 60 _ 70 _ 80 _ 100 _ 120 _ ns Output Buffer Turn-off Time toFF _- 20 _ 20 _ 20 _ 25 _ 30 ns | 6 Output Buffer Turn-off to OE tOFF2 _ 20 _ 20 _ 20 _ 25 _ 30 ns | 6 Output Hold Time from Address taou 5 _ 5 _ 5 _ 5 5 ns CS to Din Delay Time tcpp | 20 _ 20 20 25 _ 30 | os CS Hold Time from OE tocH 20 20 25 25 30 | ns OE Hold Time from RAS tRoH 60 _ 70 _ 80 100 120 _ ns OE Hold Time from CS tcon 20 20 25 25 _ 30 | ns OE Pulse Width toEP 20 20 25 25 30 | nos Write Cycle HMS514258A HM514258A | HM514258A | HM514258A | HM514258A Parameter Symbol -6 7 8 -10 12 Unit| Note Min | Max | Min | Max | Min | Max | Min | Max | Min | Max Write Command Setup Time twes 0 _ 0 0 _ 0 _ 0 _ ns | 10 Write Command Hold Time twcH 15 _ 15 _ 20 _ 25 _ 25 ns Write Command Hold TimetoRAS |twcr | 55 65 _ 75 95 115 | ns Write Command Pulse Width twp 10 _ 10 _ 15 _ 15 _ 20 _ ns Write Command to RAS Lead Time |tpwi | 20 20 25 25 _ 30 | ns Write Command to CS Lead Time tcwWL 20 _ 20 _ 25 _ 25 30 ns Diy Setup Time tps 0 _ 0 _ 0 _ 0 0 _ ns | 11 Din Hold Time tpH 15 _ 15 _ 20 _ 25 _ 25 _ ns | 11 Dj, Hold Time to RAS tpuR | 55 _ 65 75 95 115 | ns Column Address Hold Time from RAS} tawr 55 _ 65 _ 75 _ 95 115 _ ns Read-Modify-Write Cycle HMS514258A HMS14258A HM514258A | HMS514258A HMS14258A Parameter Symbol -6 7 8 -10 -12 Unit | Note Min Max | Min Max Min | Max | Min | Max | Min Max Read-Modify-Write Cycle Time trwc 170 - 180 _ 220 _ 255 _ 295 _ ns RAS to WE Delay Time trwD 85 _ 93 110 _ 135 _ 160 ns | 10 CS to WE Delay Time tcwo | 45 45 _ 55 65 70 | ns] 10 Column Address to WE Delay Time|tawp | 55 60 70 85 _ 95 | nos] 10 Refresh Cycle HMS14258A HM514258A HMS514258A | HMS514258A HMS514258A Parameter Symbol 6 7 8 -10 12 Unit | Note Min Max Min Max Min Max Min | Max Min Max (GS Belce RAS Refresh Cycle) [SR | 1 | | 1 | | WH | ~ | WB) |] P| | CS betone RAS Refresh Cycle) [HR | 15 | | 1 | | 2% | | 7% | | | | RAS Precharge to CS Hold Time | tzpH 10 _ 10 _ 10 _ 10 _ 10 _ ns @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 63HM514258A Series Static Column Mode Cycle HIM514258A | HM514258A | HM514258A | HM514258A | HM514258A Parameter Symbol -6 7 8 -10 -12 Unit| Note Min | Max | Min | Max | Min | Max | Min | Max | Min | Max Static Column Mode Cycle Time tsc 35 _ 40 _ 45 55 _ 60 ns Static Column Mode RAS Pulse Width |tpasc} | 100000} | 100000] |100000/ |100000/ | 100000] ns RAS to Second WE Delay Time trswp| 70 _ 80 _ 90 | 10 | | 135 | ns Static Column Mode CS Precharge Time |tsy 10 10 _ 10 _ 10 15 | nos Static Column Mode WE Precharge Time] twy 10 10 _ 10 _ 10 15 | ns Static Column Mode Read-Modify-Write Cycle and Mixed Cycle HMS514258A | HM514258A | HM514258A | HM514258A | HM514258A Parameter Symbol -6 -7 8 -10 -12 Unit | Note Min | Max | Min | Max | Min | Max | Min | Max] Min | Max Static Column Mode Cycle Time on Read-Modify-Write tspw 90 _ 100 - 120 _ 140 _ 160 | ns | 12 Access Time from First WE taLw _ 65 - 75 _ 85 _ 100 _ 115 | ns [3,13 Last WE to Column Address Delay Time!thwap} 20 35 20 40 25 45 25 50 30 60 ns | 15 Last WE to Column Address Hold Time |tayrw| 65 _ 75 _ 85 100 _ 115 | os Notes: 1. AC measurements assume tr = 5 ns. 2. I 10. 11. 12. 13. 14, 15. 64 Assumes that tpcp trcp (max) and trap S trap (max). If trcp or trap is greater than the maximum recommended value shown in this table, trac exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL load and 100 pF. 4. 5. 6 Assumes that tpcp 2 trcp (max) and trap S trap (max). . Assumes that tpcp * trcp (max) and trap 2 trap (imax). . torr (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. . Transition times are measured between Vyyy and Vy. Operation with the tpcp (max) limit insures that trac (max) can be met, trcp (max) is specified as a reference point only, if trcp is greater than the specified tacp (max) limit, then access time is controlled exclusively by tacs- . Operation with the trap (max) limit insures that trac (max) can be met, trap (max) is specified as a reference point only, if trap is greater than the specified tpap (max) limit, then access time is controlled exclusively by taa. twcs, trwp, tcwp and tawp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2 twes (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tpwp 2 trwp (min), tcwp 2 tcwp (min) and tawp 2 tawp (min) the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. These parameters are referenced to CS leading edge in early write cycles and to WE leading edge in delayed write or read- modify-write cycles. tsrw (min) = tawp (min) + thwap (max) + ty Assumes that tuewap * tLwap (max). If tuwap is greater than the maximum recommended value shown in this table, taLw exceeds the value shown. Assumes that thwap 2 tLlwap (max). Operation with the thwap (max) limit insures that tar w (max) can be met, tpwap (max) is specified as a reference point only, if thwap is greater than the specified t, wap (max) limit, then access time is controlled exclusively by ta a- . taHR is defined as the time at which the column address hold is set. . An initial pause of 100 ps is required after power-up followed by eight or more initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). If internal refresh counter is used, eight or more CS before RAS refresh cycles are required. . In delayed write or read-modify-write cycles, OE must disable output buffers prior to applying data to the device. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HM514258A Series B TIMING WAVEFORMS Read Cycle Address Din P77: Dont care 0114-5 * Early Write Cycle Address WE Din Valid Input High-2*? DE : Don't care twes2twes (min) : Don't care 0114-6 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 65HM514258A Series * Delayed Write Cycle Address Column Din Dout : Don't care. 0114-7 Read-Modify-Write Cycle Address Din Dout : Don't care. 0134-8 @ HITACHI 66 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, GA 94005-1819 (415) 589-8300HM51425B8A Series * RAS Only Refresh Cycle Address High- Dout ighZ OE, WE : Don't care : Don't care Refresh address: AQ-A8 (AX0-AX8) 0114-9 e CS Before RAS Refresh Cycle veers WML Le Dout High=Z WE, GE : Don't care : Don't care 0114-10 Static Column Mode Read Cycle RAS cs Address Column1 Column2 Column3 Dout 77) : Dont care. o114-11 @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 67HM514258A Series * Static Column Mode Write Cycle (1) RAS cs Address WE : Valid Din Input 2 High-Z*? Dout 1. ZA : Don't care 2. twos 2 twos (min) 3. OE : Don't care O1t4-12 * Static Column Mode Write Cycle (2) RAS ts Address WE t t Din Valid 2 Valid High-2*? Dout tg! 1. ZZ] : Don't care. 2. twos = twes(min) 3. OE: Don't care. 0114-13 @ HITACHI 68 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300HM514258A Series Static Column Mode Read-Modify-Write Cycle RAS Address Column2 Din : Dont care. O114-14 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 69HM514258A Series 70 Supply Current Icci (Normalized) Supply Current Icct (Normalized) Supply Current Iccz (Normalized) Supply Current (Active) vs Supply Voltage a9 0.8 0.7 4.50 4.75 5.00 5.25 5.50 Supply Voltage Vcc (V) Supply Current (Active) vs Frequency as 0.1 0.1 05 1.0 5.0 10.0 Frequency f (MHz) Supply Current (Standby) vs Supply Voltage interface 0.8 06 4 4y50 878 5.00 5.25 5.50 Supply Voltage Vcc (V) @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 Supply Current Ice: (Normalized) Supply Current Icc2 (Normalized) Supply Current Icc2 (Normalized) Supply Current (Active) vs Ambient Temperature oO 20 40 66 80 Ambient Temperature Ta (C) Supply Current (Standby) vs Supply Voltage 0.9 0.8 Oa50 478 5.00 5.25 5.50 Supply Voltage Vec() Supply Current (Standby) vs Ambient Temperature 20 40 60 Ambient Temperature Ta (C) 0114-15HM514258A Series RAS Access Time vs RAS Access Time vs Supply Voltage Ambient Temperature ag RAS Access Time trac (Normalized) RAS Access Time trac (Normalized) 0.8 oT 4.75 5.00 $.25 5.50 0.7 20 40 60 Supply Voltage Vcc (V) Ambient Temperature Ta (C) CS Access Time vs CS Access Time vs Supply Voltage Ambient Temperature 3 3 z g 3 eo o E i Bo, 6 4.50 5.00 $.25 0 20 40 60 80 Supply Voltage Vcc (V) Ambient Temperature Ta (C) Address Access Time vs Address Access Time vs Supply Voltage Ambient Temperature 0.8 Address Access Time taa (Normalized) Address Access Time taa (Normalized) 0.7 O70 475 50 5.25 5.50 0 7 0 Supply Voltage Vec(V) Ambient Temperature Ta (C) 0114-16 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 71