TD62C805FG
2006-01-20
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TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TD62C805FG
48BIT THERMAL HEAD DRIVER
The TD62805FG is a general purpose 48bit driver IC consisting of
8 block 8bit shift register and 48bit drivers (Open Drain).
This device is best suited as a 48 dot thermal printer head
drivers.
The suffix (G) appended to the part number represents a Lead
(Pb)-Free product.
Features
8bit parallel input and 6 block 8bit shift register
CMOS compatible input.
High driverability ·········· 30 V / 100 mA / ch
Built in monostable multivibrator for head protection
16 steps gray scale operating with 4bit data
48bit open drain outputs
Package ·························· µPFP−80 pin
Weight: 1.53 g (typ.)
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Pin Connection (top view)
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Block Diagram
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Pin Function
PIN No. PIN NAME FUNCTION
24 CLK “ ” : Data shift
25 WRITE·CLK “H” : enable clock signal, “L” : disable clock signal pull−up input terminal
37 RESET “L” : all outputs “OFF”, reset PWM counter reset PWM counter and MMV circuit
Pull−up input terminal
28~36 DATA1~8
Input terminals for output data
“H” : output “ON”, “L” : output “OFF”
And input terminals for PWM data
26 OUT / PWM “H” : enable output data for shift register
“L” : enable PWM data for counter
38 PWM “L” : output enable (PWM operating)
39 COUNTER·CLOCK Input terminal for clock of PWM counter and for trigger of MMV
40 OUT· E “L” : all outputs “ON”
42 E·CLK “ ” : outputs “OFF” when OUT·E is “High”. Outputs “ON” when OUT·E is “Low”.
Pull−up input terminal
41 WRITE· E “H” : enable E−CLK signal pull−up input terminal
43 MMV / E CR connection terminal for MMV
22 MO ON / OFF monitor terminal of output OF8
23, 44 VDD Supply voltage terminal for control logic
― V
SS (O) GND terminals for driver
PIN No. : 2, 3, 12, 21, 45, 54, 63, 64, 73
27, 32 VSS (L) GND terminals for control logic
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(1) Data Input
D1~D6 of Input Dates are entered to shift Register by the clock signal with the timing of rise.
Outputs are latched by holding the WRITE·CLK “Low” or to stop the clock signal.
PWM Data (DATA1~4) are latched by OUT / PWM signal “Low”.
(2) Output Enable
Outputs become “OFF” at the first rising edge of E·CLK after the OUT·E to “High”, and become “ON” at
the first rising edge of E·CLK after the OUT·E to “Low”.
Output ON / OFF duty is controlled by controlling OUT·E signal directly or to change the timing of
WRITE·E and E·CLK.
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(3) PWM Control
Outputs ON / OFF duty are controlled by OUT· E and PWM DATA of D1~D4 PWM control is performed
by comparing the internal 4bit PWM Counter out and PWM DATA of D1~D4.
For example, when PWM DATA is 7, 50% Output Duty is obtained.
(Refer to tables below.)
PWM DATA 0 1 2 3 4 5 6 7 8 9
Duty (%) 0 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25
PWM DATA A B C D E F
Duty (%) 62.50 68.75 75.00 81.25 87.50 100.00
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MMV Operation
MMV output of Q becomes “L” when the MMV / E voltage becomes less than Vref (L) after the first rising edge of
INTERNAL CLOCK.
And becomes “H” when the MMV / E voltage above Vref (H) after re−charging of external capacitance connect to
MMV / E. The external capacitance and Resistor connect to MMV / E control MMV Output “ON” period.
So Output Load is protected from burn−out. It’s required enough discharging time of external capacitance.
(Refer to figure below)
● Pulse width of MMV
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Input Circuit
1. DATA1~8, CLK, COUNTER·CLK, OUT /PWM , OUT·E
2. E·CLK, RESET , WRITE·E, WRITE·CLK
3. PWM
Output Circuit
1. 8~OA1 ~8~OF1
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Absolute Maximum Ratings (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD 7 V
Output Voltage VDS 30 V
Output Current IDS 100 mA / ch
Input Current IIN ±5 mA
Input Voltage VIN −0.4~VDD±0.4 V
Free Air 1.0
Power
Dissipation On PCB (Note)
PD 1.3
W
Operating Temperature Topr −40~85 °C
Storage Temperature Tstg −55~150 °C
Note: On Glass Epoxy PCB (100 × 100 × 1.6 mm, Cu 40%)
Recommended Operating Conditions (Ta = −40~85°C)
CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP. MAX UNIT
Output Voltage VDS ― ― ― 26 V
Supply Voltage VDD ― 4.5 ― 5.5 V
Duty 50% ― ― 33.3
Duty 80% ― ― 26.4
Output Current IDS
Duty 100% ― ― 23.6
mA /ch
Input Voltage VIN ― GND ― V
DD V
Operating Clock Frequency fCLK Duty 50% ― ― 5 MHz
COUNTER·CLK
Clock Pulse Width tw CLK
50 ― ― ns
Data Set−Up Time tsetup
Data Hold Time thold
― 20 ― ― ns
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Electrical Characteristics (Ta = 25°C, VDD = 5.5 V)
CHARACTERISTIC SYMBOL
TEST
CIR−
CUIT
TEST CONDITION MIN TYP. MAX UNIT
“H” Level VIH ― ― 3.5 ― VDD
+ 0.4
Input Voltage
“L” Level VIL ― ― −0.4 ― 1.5
V
WRITE·CLK
E·CLK, RESET
WRITE· E
IINH ― V
IN = 0 V, VDD = 5 V −34 −70 −145
Input Current
PWM IINL ― V
IN = 5 V, VDD = 5 V 34 70 145
µA
IDS = 80 mA ― ― 960
Output Voltage VDS ― OA1~OF8
IDS = 50 mA ― ― 600
mV
Output On Resistor RON ― I
DS = 50 mA ― ― 12.0 Ω
Output Leak Current IOZ ― V
DS = 30 V ― ― 10 µA
Quiescent Current IDD ― ― ― ― 20 µA
Operating Supply Current IDDopr ― VDD = 5 V, fCLK = 5MHz
Output OPEN ― ― 5 µA
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Switching Characteristics (VDD = 5.5 V, VDS = 26 V, Ta = 25°C)
CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP. MAX UNIT
Maximum Operating Clock Frequency fMAX Duty 50% 10 ― ― MHz
CLK−OUTn , WRITE·CLK−OUTn ― 80 ―
RESET −OUTn ― 100 ―
COUNTER, CLK−OUTn
(Note)
― 110 ―
OUT· E−OUTn , WRITE· E−OUTn
E·CLK−OUTn ― 100 ―
Propagation
Delay Time
“L”−”H”
MMV / E−OUTn
tpLH
― 130 ―
CLK−OUTn , WRITE·CLK−OUTn ― 60 ―
RESET −OUTn ― 100 ―
COUNTER, CLK−OUTn (Note) ― 90 ―
OUT· E−OUTn , WRITE· E−OUTn
E·CLK−OUTn ― 70 ―
Propagation
Delay Time
“H”−”L”
MMV / E−OUTn
tpHL
― 80 ―
Minimum Clock Pulse Width tw
Duty 50%
VIN (H) = 4.5 V
VIN (L) = 0 V
RL = 375 Ω
CL = 15 pF
25 ―
DATA−OUT / PWM
DATA−CLK
Data Set Up Time
OUT· E−E·CLK
tsetup ― ― 10 ―
DATA−OUT / PWM
DATA−CLK
Data Hold Time
OUT· E−E·CLK
thold ― ― 10 ―
ns
COUNTER·CLK
Maximum Rise Time
CLK
tr ― ― ― 1
COUNTER·CLK
Maximum Fall Time
CLK
tf ― ― ― 1
Output Rise Time tor ― ― 0.02 1
Output Fall Time
OUTn
tof ― ― 0.05 0.4
µs
MMV Pulse Width tMMV ― ― 3 ― ms
Note: COUNTER DATA = F
Precautions for Using
This IC does not integrate protection circuits such as overcurrent and overvoltage protectors.
Thus, if excess current or voltage is applied to the IC, the IC may be damaged. Please design the IC so that
excess current or voltage will not be applied to the IC.
Utmost care is necessary in the design of the output line, VCC and GND line since IC may be destroyed due to
short−circuit between outputs, air contamination fault, or fault by improper grounding.
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Package Dimensions
QFP80−P−1420−0.80C Unit: mm
Weight: 1.53 g (Typ.)
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Notes on Contents
1. Block Diagrams
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Absolute Maximum Ratings
The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must
not be exceeded during operation, even for an instant.
If any of these ratings are exceeded during operation, the electrical characteristics of the device may be
irreparably altered and the reliability and lifetime of the device can no longer be guaranteed.
Moreover, any exceeding of the ratings during operation may cause breakdown, damage and/or degradation
in other equipment. Applications using the device should be designed so that no absolute maximum rating
will ever be exceeded under any operating conditions.
Before using, creating and/or producing designs, refer to and comply with the precautions and conditions
set forth in this document.
4. Recommended Operating Conditions
The values of the conditions are applied within the range of the operating temperature and not guaranteed.
Handling of the IC
Ensure that the product is installed correctly to prevent breakdown, damage and/or degradation in the product or
equipment.
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