FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
CLOCK GENERATOR
ICS843011C
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 1 ICS843011CG REV A March 2, 2009
GENERAL DESCRIPTION
The ICS843011C is a Fibre Channel Clock Generator
and a member of the HiPerClocksTM family of high
performance devices from IDT. The ICS843011C
uses a 26.5625MHz crystal to synthesize 106.25MHz
or a 25MHz crystal to synthesize 100MHz. The
ICS843011C has excellent <1ps phase jitter performance, over
the 637kHz – 10MHz integration range. The ICS843011C is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
FEATURES
•One differential 3.3V LVPECL output
•Crystal oscillator interface designed for 26.5625MHz,
18pF parallel resonant crystal
•Output frequency: 106.25MHz or 100MHz
•VCO range: 560MHz - 680MHz
•RMS phase jitter @ 100MHz, using a 25MHz crystal
(637kHz - 10MHz): 0.29ps (typical)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
FREQUENCY TABLE
)zHM(latsyrC)zHM(ycneuqerFtuptuO
5265.6252.601
52001
ICS843011C
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
VCCA
VEE
XTAL_OUT
XTAL_IN
1
2
3
4
VCC
Q
nQ
nc
8
7
6
5
OSC Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = ÷24 (fixed)
÷6
BLOCK DIAGRAM PIN ASSIGNMENT
Q
nQ
XTAL_IN
XTAL_OUT
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 2 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
ACC
rewoP.nipylppusgolanA
2V
EE
rewoP.nipylppusevitageN
,3
4
,TUO_LATX
NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoehtsiTUO_LATX
5cndesunU.tcennocoN
7,6Q,QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
8V
CC
rewoP.nipylppuseroC
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 3 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
21.0–3.3V
CC
V
I
ACC
tnerruCylppuSgolanAInidedulcni
EE
21Am
I
EE
tnerruCylppuSrewoP 09Am
TABLE 2B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
TABLE 4. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3. CRYSTAL CHARACTERISTICS
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noitallicsOfoedoM latnemadnuF
ycneuqerF 525265.62zHM
)RSE(ecnatsiseRseireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
leveLevirD 1Wm
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
F
TUO
ycneuqerFtuptuO zHM52001zHM
zHM5265.6252.601zHM
t
)Ø(tij ;)modnaR(rettiJesahPSMR
1ETON
;zHM52.601
zHM01-zHk736:egnaRnoitargetnI 92.0sp
;zHM001
zHM01-zHk736:egnaRnoitargetnI 92.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052005sp
cdoelcyCytuDtuptuO 9415%
.stolPesioNesahPehtotreferesaelP:1ETON
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 4 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 106.25MHZ
106.25MHz
RMS Phase Noise Jitter
637kHz to 10MHz = 0.29ps (typical)
OFFSET FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M
➤
➤
➤
dBc
Hz
NOISE POWER
Phase Noise Result by adding
a Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 5 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VEE
2V
-1.3V ± 0.165V
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
Q
nQ
VCC
RMS PHASE JITTER
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
2V
VCCA
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 6 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843011C has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum
C1 and C2 values can be slightly adjusted for different board
layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843011C provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1
illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VCCA
10µF
.01µF
3.3V
.01µF
VCC
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 7 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A
shows a schematic example of the ICS843011C. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 26.5625MHz crystal is used for generating
106.25MHz output frequency. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 values may be slightly adjusted for optimizing
frequency accuracy.
FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE
FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B
shows an example of ICS843011C P.C. board
layout. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole HC49
package. The footprints of other components in this example are
listed in the
Table 6.
There should be at least one decoupling
capacitor per power pin. The decoupling capacitors should be
located as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
ecnerefeReziS
2C,1C2040
3C5080
5C,4C3060
2R3060
tnenopmocstsil,6elbaT:ETON
.elpmaxetuoyalsihtninwohssezis
R5
50
Zo = 50 Ohm
C4
0.1u
C2
33pF
XTAL_IN
Q
nQ
18pF
VCCA
R5
133
R2
10
Zo = 50 Ohm
C5
0.1u
R6
50
Zo = 50 Ohm
R4
82.5
+
-
Optional
Y-Termination
Q
XTAL_OUT
X1
26.5625MHz
Zo = 50 Ohm
nQ
VCC
VCC
C1
27pF
+
-
R7
50
U2
843011C
1
2
3
4
8
7
6
5
VCCA
VEE
XT AL _ O U T
XT AL _ I N
VCC
Q
nQ
nc
R6
82.5
C3
10uF
VCC
R3
133
843011C
27pF
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 8 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843011C.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 90mA = 311.85mW
•Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 311.85mW + 30mW = 341.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.342W * 90.5°C/W = 101°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 9 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCCO_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (V
CC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (V
CC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 10 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS843011C is: 2436
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 11 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°0°8
aaa--01.0
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 12 ICS843011CG REV A March 2, 2009
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
TABLE 8. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
GC110348SCIC1103POSSTdael8ebutC°07otC°0
TGC110348SCIC1103POSSTdael8leer&epat0052C°07otC°0
FLGC110348SCIDBTPOSST"eerF-daeL"dael8ebutC°07otC°0
TFLGC110348SCIDBTPOSST"eerF-daeL"dael8leer&epat0052C°07otC°0
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffusFL"nahtiwderedroeratahtstraP:ETON
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Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
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800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
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Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
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Leatherhead, Surrey
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England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS843011C
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
