ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843011C is a Fibre Channel Clock Generator ICS and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS843011C uses a 26.5625MHz crystal to synthesize 106.25MHz or a 25MHz crystal to synthesize 100MHz. The ICS843011C has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS843011C is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * One differential 3.3V LVPECL output * Crystal oscillator interface designed for 26.5625MHz, 18pF parallel resonant crystal * Output frequency: 106.25MHz or 100MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 100MHz, using a 25MHz crystal (637kHz - 10MHz): 0.29ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages FREQUENCY TABLE Crystal (MHz) Output Frequency (MHz) 26.5625 106.25 25 100 BLOCK DIAGRAM XTAL_IN OSC XTAL_OUT PIN ASSIGNMENT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. Q /6 nQ 1 2 3 4 8 7 6 5 VCC Q nQ nc ICS843011C M = /24 (fixed) IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR VCCA VEE XTAL_OUT XTAL_IN 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 1 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VCCA Power Analog supply pin. 2 3, 4 5 VEE XTAL_OUT, XTAL_IN nc Power Unused Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core supply pin. Input IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR Description 2 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICCA Analog Supply Current IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC - 0.12 3.3 VCC V 12 mA 90 mA Maximum Units included in IEE TABLE 2B. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCC - 2V. TABLE 3. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 26.5625 MHz Equivalent Series Resistance (ESR) Frequency 25 50 Shunt Capacitance 7 pF Drive Level 1 mW TABLE 4. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter FOUT Output Frequency tjit(O) RMS Phase Jitter (Random); NOTE 1 t R / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 25MHz 100 MHz 26.5625MHz 106.25MHz; Integration Range: 637kHz - 10MHz 100MHz; Integration Range: 637kHz - 10MHz 20% to 80% 106.25 MHz 0.29 ps 0.29 ps 250 500 ps 49 51 % NOTE 1: Please refer to the Phase Noise Plots. IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 3 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 106.25MHZ 0 -10 -20 Fibre Channel Filter -30 -40 106.25MHz -50 RMS Phase Noise Jitter 637kHz to 10MHz = 0.29ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 -120 NOISE POWER dBc Hz -60 -130 -140 -150 -160 -170 -180 -190 100 1k 10k Phase Noise Result by adding a Fibre Channel Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 4 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot VCC Qx Noise Power 2V SCOPE VCCA Phase Noise Mask LVPECL nQx f1 VEE Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.3V 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ 80% Q 80% VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR OUTPUT RISE/FALL TIME 5 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843011C provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F 10 VCCA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843011C has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 6 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR APPLICATION SCHEMATIC Figure 3A shows a schematic example of the ICS843011C. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for generating 106.25MHz output frequency. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VCCA VCC VCC R2 10 C3 10uF C4 0.1u R3 133 U2 R5 133 Zo = 50 Ohm Q XTAL_OUT C2 33pF 27pF X1 26.5625MHz 18pF 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ nc 8 7 6 5 VCC + Zo = 50 Ohm - nQ XTAL_IN 843011C 843011C R4 82.5 C5 0.1u C1 27pF R6 82.5 Zo = 50 Ohm Q + Zo = 50 Ohm nQ R5 50 Optional Y-Termination R6 50 R7 50 FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS843011C P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 7 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843011C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 90mA = 311.85mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 311.85mW + 30mW = 341.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.342W * 90.5C/W = 101C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 0 1 2.5 101.7C/W 90.5C/W 89.8C/W 8 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V L CC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 9 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS843011C is: 2436 IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 10 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 11 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843011CG 3011C 8 lead TSSOP tube 0C to 70C ICS843011CGT 3011C 8 lead TSSOP 2500 tape & reel 0C to 70C ICS843011CGLF TBD 8 lead "Lead-Free" TSSOP tube 0C to 70C ICS843011CGLFT TBD 8 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 3.3V LVPECL CLOCK GENERATOR 12 ICS843011CG REV A March 2, 2009 ICS843011C FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. 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