Current Output, Parallel Input, 16-/14-Bit
Multiplying DACs with Four-Quadrant Resistors
Data Sheet AD5546/AD5556
Rev. D
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FEATURES
16-bit resolution
14-bit resolution
2- or 4-quadrant multiplying DAC
±1 LSB DNL
±1 LSB INL
Operating supply voltage: 2.7 V to 5.5 V
Low noise: 12 nV/√Hz
Low power: IDD = 10 μA
0.5 μs settling time
Built-in RFB facilitates current-to-voltage conversion
Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,
or ±10 V outputs
2 mA full-scale current ±20%, with VREF = 10 V
Automotive operating temperature: –40°C to +125°C
Compact TSSOP-28 package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Digital waveform generation
FUNCTIONAL BLOCK DIAGRAM
DAC
AD5546/
AD5556
WR
LDAC
MSB RS
DB0 TO DB15
CONTROL
LOGIC DAC
REGISTER
POR
16/14
V
DD
R1 R2 R
OFS
R
FB
R1 R
COM
REF R
OFS
R
FB
I
OUT
GND
03810-001
Figure 1. AD5546/AD5556 Simplified Block Diagram
GENERAL DESCRIPTION
The AD5546/AD5556 are precision 16-/14-bit, multiplying, low
power, current output, parallel input digital-to-analog converters
(DACs). They operate from a single 2.7 V to 5.5 V supply with
±10 V multiplying references for four-quadrant outputs. Built-
in four-quadrant resistors facilitate the resistance matching and
temperature tracking that minimize the number of components
needed for multiquadrant applications. The feedback resistor
(RFB) simplifies the I-V conversion with an external buffer. The
AD5546/AD5556 are packaged in compact TSSOP-28 packages
with operating temperatures from –40°C to +125°C.
The EVAL-AD5546SDZ is available for evaluating DAC perfor-
mance. For more information, see the UG-309 evaluation board
user guide.
03810-024
VDD
ROFS
ROFSA
VOUT
RFB
RFBA
C6
GND
U1
AD5546/AD5556
IOUT
R2R1
RCOMA
R1A
16-/14-BIT
DATA
16-/14-BIT
DATA
VREFA
U2B
OP2177
–
+
C4
1µF
C5
0.1µF
C8
1µF
C9
0.1µF
+15V
–15V
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
C2
0.1µF
C1
1µF V+
V–
U2A
OP2177
+
–
C7
+5V
+10V
–
10V
Figure 2. 16-/14-Bit, Four-Quadrant Multiplying DAC with a Minimum of External Components
AD5546/AD5556 Data Sheet
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Operation ........................................................................... 10
Digital-to-Analog (DAC) Converter Section ......................... 10
Digital Section ............................................................................ 11
ESD Protection Circuits ............................................................ 11
Amplifier Selection .................................................................... 11
Reference Selection .................................................................... 11
Applications Information .............................................................. 12
Unipolar Mode ........................................................................... 12
Bipolar Mode .............................................................................. 13
AC Reference Signal Attenuator ............................................... 14
System Calibration ..................................................................... 14
Reference Selection .................................................................... 15
Amplifier Selection .................................................................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
11/11—Rev. C to Rev. D
Changes to General Description Section ...................................... 1
Changes to Ordering Guide .......................................................... 18
1/11—Rev. B to Rev. C
Changes to Figure 2 .......................................................................... 1
Changes to Figure 21 ...................................................................... 13
4/10—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 4
Moved Timing Diagram Section and Figure 5 to
Specifications Section....................................................................... 4
Moved Table 5 Through Table 7 to Digital Section Section ....... 7
Replaced Figure 15 and Figure 16 .................................................. 9
Deleted Figure 17 and Figure 18 ..................................................... 9
Added Reference Selection Section, Amplifier Selection Section,
and Table 11 Through Table 13 .................................................... 15
9/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Static Performance, Relative Accuracy,
Grade: AD5546C Parameter, Table 1 ............................................. 3
Changes to Ordering Guide .......................................................... 16
1/04—Revision 0: Initial Version
Data Sheet AD5546/AD5556
Rev. D | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, IOUT = virtual GND, GND = 0 V, VREF = –10 V to 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
STATIC PERFORMANCE1
Resolution N AD5546, 1 LSB = VREF/216 = 153 µV at
VREF = 10 V
16 Bits
AD5556, 1 LSB = VREF/214 = 610 µV at
VREF = 10 V
14 Bits
Relative Accuracy INL Grade: AD5556C ±1 LSB
Grade: AD5546B ±2 LSB
Grade: AD5546C ±1 LSB
Differential Nonlinearity DNL Monotonic ±1 LSB
Output Leakage Current IOUT Data = zero scale, TA = 25°C 10 nA
Data = zero scale, TA = TA maximum 20 nA
Full-Scale Gain Error GFSE Data = full scale ±1 ±4 mV
Bipolar Mode Gain Error GE Data = full scale ±1 ±4 mV
Bipolar Mode Zero-Scale
Error
GZSE Data = full scale ±1 ±2.5 mV
Full-Scale Tempco2 TCVFS 1 ppm/°C
REFERENCE INPUT
VREF Range VREF –18 +18 V
REF Input Resistance REF 4 5 6 kΩ
R1 and R2 Resistance R1 and R2 4 5 6 kΩ
R1-to-R2 Mismatch ∆(R1 to R2) ±0.5 ±1.5 Ω
Feedback and Offset
Resistance
RFB, ROFS 8 10 12 kΩ
Input Capacitance2 CREF 5 pF
ANALOG OUTPUT
Output Current IOUT Data = full scale 2 mA
Output Capacitance2 COUT Code dependent 200 pF
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage VIL VDD = 5 V 0.8 V
VDD = 3 V 0.4 V
Logic Input High Voltage VIH VDD = 5 V 2.4 V
VDD = 3 V 2.1 V
Input Leakage Current IIL 10 µA
Input Capacitance2 CIL 10 pF
INTERFACE TIMING2, 3
Data to WR Setup Time tDS VDD = 5 V 20 ns
VDD = 3 V 35 ns
Data to WR Hold Time tDH VDD = 5 V 0 ns
VDD = 3 V 0 ns
WR Pulse Width tWR VDD = 5 V 20 ns
VDD = 3 V 35 ns
LDAC Pulse Width tLDAC VDD = 5 V 20 ns
VDD = 3 V 35 ns
AD5546/AD5556 Data Sheet
Rev. D | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
RS Pulse Width tRS V
DD = 5 V 20 ns
V
DD = 3 V 35 ns
WR to LDAC Delay Time tLWD V
DD = 5 V 0 ns
V
DD = 3 V 0 ns
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE 2.7 5.5 V
Positive Supply Current IDD Logic inputs = 0 V 10 μA
Power Dissipation PDISS Logic inputs = 0 V 0.055 mW
Power Supply Sensitivity PSS ∆VDD = ±5% 0.003 %/%
AC CHARACTERISTICS4
Output Voltage Settling
Time
tS To ±0.1% of full scale, data cycles from zero
scale to full scale to zero scale
0.5 μs
Reference Multiplying BW BW VREF = 100 mV rms, data = full scale, C6 =5.6 pF5 6.8 MHz
DAC Glitch Impulse Q VREF = 0 V, midscale minus 1 to midscale −3 nV-s
Multiplying Feedthrough
Error
VOUT/VREF V
REF = 100 mV rms, f = 10 kHz 79 dB
Digital Feedthrough QD WR = 1, LDAC toggles at 1 MHz 7 nV-s
Total Harmonic Distortion THD VREF = 5 V p-p, data = full-scale, f = 1 kHz –103 dB
Output Noise Density eN f = 1 kHz, BW = 1 Hz 12 nV/rt Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system, using an external precision OP97 I-V converter amplifier. The AD554x RFB terminal is
tied to the amplifier output. The op amp +IN is grounded, and the DAC IOUT is tied to the op amp –IN. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and are not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-V converter amplifier except for THD where an AD8065 was used.
5 C6 is the C6 capacitor shown in Figure 20.
TIMING DIAGRAM
03810-005
t
WR
t
DS
t
DH
t
LWD
t
LDAC
t
RS
WR
DATA
LDAC
RS
Figure 3. AD5546/AD5556 Timing Diagram
Data Sheet AD5546/AD5556
Rev. D | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND –0.3 V, +8 V
RFB, ROFS, R1, RCOM, and REF to GND –18 V, 18 V
Logic Inputs to GND –0.3 V, +8 V
V (IOUT) to GND –0.3 V, VDD + 0.3 V
Input Current to Any Pin Except Supplies ±50 mA
Thermal Resistance (θJA) 128°C
Maximum Junction Temperature (TJ MAX) 150°C
Operating Temperature Range –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Lead Temperature:
Vapor Phase, 60 s 215°C
Infrared, 15 s 220°C
Package Power Dissipation (TJ MAX – TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5546/AD5556 Data Sheet
Rev. D | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03810-003
AD5546
TOP VIEW
(No t t o Scal e)
D7
1
V
DD
28
D6
2
D8
27
D5
3
D9
26
D4
4
D10
25
D3
5
D11
24
D2
6
D12
23
D1
7
D13
22
D0
8
D14
21
R
OFS 9
D15
20
R
FB 10
GND
19
R1
11
RS
18
R
COM 12
MSB
17
REF
13
WR
16
I
OUT 14
LDAC
15
Figure 4. AD5546 Pin Configuration
03810-004
AD5556
TOP VIEW
(No t t o Scal e)
NC = NO CONNECT
D5
1
V
DD
28
D4
2
D6
27
D3
3
D7
26
D2
4
D8
25
D1
5
D9
24
D0
6
D10
23
NC
7
D11
22
NC
8
D12
21
R
OFS 9
D13
20
R
FB 10
GND
19
R1
11
RS
18
R
COM 12
MSB
17
REF
13
WR
16
I
OUT 14
LDAC
15
Figure 5. AD5556 Pin Configuration
Table 3. AD5546 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 8 D7 to D0 Digital Input Data Bits[D7: D0]. The signal level must be ≤ VDD + 0.3 V.
9 ROFS Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
10 RFB Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
11 R1 Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
12 RCOM Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
13 REF DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14 IOUT DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
15 LDAC Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.
16 WR Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17 MSB Power-On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
18 RS Reset in Active Low. Resets to zero scale if MSB = 0, and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
19 GND Analog and Digital Grounds.
20 to 21 D15 to D14 Digital Input Data Bits[D15:D14]. The signal level must be ≤ VDD + 0.3 V.
22 to 27 D13 to D8 Digital Input Data Bits[D13:D8]. The signal level must be ≤ VDD + 0.3 V.
28 VDD Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
Table 4. AD5556 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 6 D5 to D0 Digital Input Data Bits[D5:D0]. The signal level must be ≤ VDD+0.3 V.
7 to 8 NC No Connection. The user should not connect anything other than dummy pads on these terminals.
9 ROFS Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
10 RFB Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
11 R1 Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
12 RCOM Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
Data Sheet AD5546/AD5556
Rev. D | Page 7 of 20
Pin No. Mnemonic Description
13 REF DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14 IOUT DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
15 LDAC Digital Input Load DAC Control. The signal level must be ≤ VDD + 0.3 V.
16 WR Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17 MSB Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
18 RS Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
19 GND Analog and Digital Grounds.
20 to 27 D13 to D6 Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V.
28 VDD Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
AD5546/AD5556 Data Sheet
Rev. D | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
03810-006
1.0
0.8
0.6
0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
INL (LSB)
CODE (Decimal)
Figure 6. AD5546 Integral Nonlinearity Error
03810-007
1.0
0.8
0.6
0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DNL (LSB)
CODE ( Decimal)
Figure 7. AD5546 Differential Nonlinearity Error
03810-008
1.0
0.8
0.6
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
INL (LSB)
CODE ( Decimal)
Figure 8. AD5556 Integral Nonlinearity Error
03810-009
1.0
0.8
0.6
0 0248 4096 6144 8192 10,240 12,288 14,336 16,384
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DNL (LSB)
CODE ( Deci mal)
Figure 9. AD5556 Differential Nonlinearity Error
03810-010
1.5
1.0
24
GE
DNL
INL
6810
0.5
0
–0.5
–1.0
–1.5
LI NE ARI TY E RRO R (L S B)
SUPPLY VOLTAGE V
DD
(V)
V
REF
= 2. 5V
T
A
= 25 °C
Figure 10. Linearity Error vs. VDD
03810-011
5
4
0 0.5 1.0 1.5 2.0 3.0 3.52.5 4.0 4.5 5.0
3
2
1
0
SUPP LY CURRENT I DD (LSB)
LOGI C INPUT VOLTAGE VIH (V)
VDD = 5V
TA= 25 °C
Figure 11. Supply Current vs. Logic Input Voltage
Data Sheet AD5546/AD5556
Rev. D | Page 9 of 20
03810-012
3.0
2.5
10k 100k 1M 10M 100M
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT ( mA)
CLOCK FRE QUENCY (Hz)
0x5555
0x8000
0xFFFF
0x0000
Figure 12. AD5546 Supply Current vs. Clock Frequency
03810-013
90
70
10 100 1k 10k 100k 1M
50
40
60
80
30
10
20
0
PSRR ( –dB)
FREQUENCY (Hz)
V
DD
= 5V ± 10%
V
REF
= 10V
Figure 13. Power Supply Rejection Ratio vs. Frequency
03810-014
LDAC
V
OUT
1
2
CH1 5.00V CH2 2.00V M 200ns A CH1 2.70V
B CH1 –6.20V
400.00ns
Figure 14. Settling Time from Full Scale to Zero Scale
–4.20
–4.15
–4.10
–4.05
–4.00
–3.95
–3.90
–3.85
–3.80
–200 –100 0100 200 300 400
TIME (n s)
V
OUT
(V)
03810-115
Figure 15. AD5546 Midscale Transition
Figure 16. AD5546 Unipolar Reference Multiplying Bandwidth
AD5546/AD5556 Data Sheet
Rev. D | Page 10 of 20
CIRCUIT OPERATION
DIGITAL-TO-ANALOG (DAC) CONVERTER SECTION
The AD5546/AD5556 are 16-/14-bit multiplying, current out-
put, and parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply and provide both unipolar 0 V to –VREF, or
0 V to +VREF, and bipolar ±VREF output ranges from a –18 V to
+18 V reference. In addition to the precision conversion RFB
commonly found in current output DACs, there are three addi-
tional precision resistors for four-quadrant bipolar applications.
The AD5546/AD5556 consist of two groups of precision R-2R
ladders, which make up the 12/10 LSBs, respectively. Further-
more, the four MSBs are decoded into 15 segments of resistor
value 2R. Figure 17 shows the architecture of the 16-bit AD5546.
Each of the 16 segments in the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor, RFB, and four-quadrant resistor, ROFS, have values of 10
kΩ. Each four-quadrant resistor, R1 and R2, equals 5 kΩ. In
four-quadrant operation, R1, R2, and an external op amp work
together to invert the reference voltage and apply it to the REF
input. With ROFS and RFB connected as shown in Figure 2, the
output can swing from –VREF to +VREF.
The reference voltage inputs exhibit a constant input resistance
of 5 kΩ ±20%. The DAC output, IOUT, impedance is code depen-
dent. External amplifier choice should take into account the
variation of the AD5546/AD5556 output impedance. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended to bypass the power supply
with a 0.01 μF to 0.1 μF ceramic or chip capacitor in parallel
with a 1 μF tantalum capacitor. Also, to minimize gain error,
PCB metal traces between VREF and RFB should match.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 20 pF capacitor is
generally adequate for the compensation.
The VDD power is used primarily by the internal logic and to
drive the DAC switches. Note that the output precision
degrades if the operating voltage falls below the specified
voltage. The user should also avoid using switching regulators
because device power supply rejection degrades at higher
frequencies.
03810-019
2R
80kΩ
R
40kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
R
40kΩ
2R
80kΩ
R
2R
80kΩ
R
2R
80kΩ
R
2R
80kΩ
R
2R
80kΩ
2R
80kΩ
R
40kΩ
R2
5kΩ
R1
5kΩ
REF
2R
80kΩ
R
40kΩ
2R
80kΩ
R
40kΩ
2R
80kΩ
R
40kΩ
2R
80kΩ
R
40kΩ
2R
80kΩ
R
40kΩ
2R
80kΩ
R
COM
R1
ADDRESS DECODER
DAC REGISTER
INPUT REGISTER
LDAC
WR
RS
RS
4 MSB
15 SEGMENTS
8-BIT R–2R
4-BIT R–2R
16 8 4
LDAC
WR
D15 D14 D0
RS
10kΩ10kΩ
R
OFS
R
FB
I
OUT
GND
RA
RB
Figure 17. 16-Bit AD5546 Equivalent R-2R DAC Circuit with Digital Section
Data Sheet AD5546/AD5556
Rev. D | Page 11 of 20
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
controller bus when the WR pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie WR
low and LDAC high. The asynchronous RS pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
MSB LSB
Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 6. AD5556 Parallel Input Data Format
MSB LSB
Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 7. Control Inputs
RS WR LDAC Register Operation
0 X1 X1 Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
1 0 0 Load input register with data bits.
1 1 1 Load DAC register with the contents of the input register.
1 0 1 Input and DAC registers are transparent.
1 When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
1 1 0 No register operation.
1 X = don’t care.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD, as shown in Figure 18. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
03810-020
5kΩ
DIGITAL
INPUTS
DGND
VDD
Figure 18. Equivalent ESD Protection Circuits
AMPLIFIER SELECTION
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
are good candidates for the I-V conversion.
REFERENCE SELECTION
The initial accuracy and the rated output of the voltage refer-
ence determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V ref-
erence with a TC of 5 ppm/oC means that the output changes by
25 µV per degree Celsius. As a result, the reference that operates
at 55oC contributes an additional 750 µV full-scale error.
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means that the output may change by ±250 µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
AD5546/AD5556 Data Sheet
Rev. D | Page 12 of 20
APPLICATIONS INFORMATION
UNIPOLAR MODE
Two-Quadrant Multiplying Mode, VOUT = 0 V to –VREF
The AD5546/AD5556 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op
amp to convert the unipolar mode of output voltage to
AD5546
VOUT = –VREF × D/65,536 (1)
AD5556
VOUT = –VREF × D/16,384 (2)
where D is the decimal equivalent of the input code.
The output voltage polarity is opposite to the VREF polarity in
this case (see Figure 19). Table 8 shows the negative output vs.
code for the AD5546.
Table 8. AD5546 Unipolar Mode Negative Output vs. Code
D in Binary VOUT (V)
1111 1111 1111 1111 –VREF(65,535/65,536)
1000 0000 0000 0000 –VREF/2
0000 0000 0000 0001 –VREF(1/65,536)
0000 0000 0000 0000 0
Two-Quadrant Multiplying Mode, VOUT = 0 V to +VREF
The AD5546/AD5556 are designed to operate with either
positive or negative reference voltages. As a result, positive
output can be achieved with an additional op amp, (see
Figure 20), and the output becomes
AD5546
VOUT = +VREF × D/65,536 (3)
AD5556
VOUT = +VREF × D/16,384 (4)
Table 9 shows the positive output vs. code for the AD5546.
Table 9. AD5546 Unipolar Mode Positive Output vs. Code
D in Binary VOUT (V)
1111 1111 1111 1111 +VREF(65,535/65,536)
1000 0000 0000 0000 +VREF/2
0000 0000 0000 0001 +VREF(1/65,536)
0000 0000 0000 0000 0
03810-021
2
+5V
5
4
GND
V
IN
TRIM
U3
ADR03
V
OUT
V
DD
R1
R
OFS
R
OFS
VOUT
–2.5V TO 0V
R
FB
R
FB
C6
2.2pF
GND
U1
AD5546/AD5556
I
OUT
R2
C4
0.1µF
C5
1µF
R
COM
R1
16-/14-BIT
DATA
16-/14-BIT
DATA
REF
U2
AD8628
–
+
–5V
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
C2
0.1µF
C1
1µF
C3
0.1µF V+
V–
Figure 19. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to –VREF
Data Sheet AD5546/AD5556
Rev. D | Page 13 of 20
03810-024
V
DD
R
OFS
R
OFSA
VOUT
R
FB
R
FBA
C6
GND
U1
AD5546/AD5556
I
OUT
R2
R1
R
COMA
R1A
16-/14-BIT
DATA
16-/14-BIT
DATA
VREFA
U2B
OP2177
–
+
C4
1µF
C5
0.1µF
C8
1µF
C9
0.1µF
+15V
–15V
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
C2
0.1µF
C1
1µF V+
V–
U2A
OP2177
+
–C7
+5V
+10V
–10V
Figure 20. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to +VREF
2
5V
6
5
4
GND
V
IN
TRIM
U3
ADR03
V
OUT
5V V
DD
R1
R
OFS
R
OFS
–VREF TO +VREF
VOUT
R
FB
R
FB
C2
GND
U1
AD5546/AD5556
I
OUT
R2
U2A
OP2177
+
–C1 –VREF +VREF
R
COM
R1
16-/14-BIT
DATA
16-/14-BIT
DATA
REF
U2B
OP2177
–
+
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
03810-002
Figure 21. Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
BIPOLAR MODE
Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
The AD5546/AD5556 contain on-chip all the four-quadrant
resistors necessary for the precision bipolar multiplying
operation. Such a feature minimizes the number of exponent
components to only a voltage reference, dual op amp, and
compensation capacitor (see Figure 21). For example, with a
10 V reference, the circuit yields a precision, bipolar –10 V to
+10 V output.
AD5546
VOUT = (D/32768 − 1) × VREF (5)
AD5556
VOUT = (D/16384 − 1) × VREF (6)
Table 10 shows some of the results for the 16-bit AD5546.
AD5546/AD5556 Data Sheet
Rev. D | Page 14 of 20
Table 10. AD5546 Output vs. Code
D in Binary VOUT
1111 1111 1111 1111 +VREF(32,767/32,768)
1000 0000 0000 0001 +VREF(1/32,768)
1000 0000 0000 0000 0
0111 1111 1111 1111 –VREF(1/32,768)
0000 0000 0000 0000 –VREF
AC REFERENCE SIGNAL ATTENUATOR
Besides handling digital waveforms decoded from parallel input
data, the AD5546/AD5556 handle equally well low frequency
ac reference signals for signal attenuation, channel equalization,
and waveform generation applications. The maximum signal
range can be up to ±18 V (see Figure 22).
SYSTEM CALIBRATION
The initial accuracy of the system can be adjusted by trimming
the voltage reference ADR0x with a digital potentiometer (see
Figure 23). The AD5170 provides an OTP (one time program-
mable), 8-bit adjustment that is ideal and reliable for such cali-
bration. The Analog Devices, Inc., OTP digital potentiometer
comes with programmable software that simplifies the factory
calibration process.
03810-0-024
16/14-BIT
VDD
ROFS
ROFSA
VOUT
RFB
RFBA
C6
GND
U1
AD5546/AD5556
IOUT
R2R1
RCOMAR1A
16/14 DATA
VREFA
U2B
OP2177
–
+
C4
1F
C5
0.1F
C8
1F
C9
0.1F
+15V
–15V
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
C2
0.1F
C1
1FV+
V–
U2A
OP2177
+
–
C7
+5V
+10V
–10V
Figure 22. Signal Attenuator with AC Reference
C8
0.1µF
C9
1µF
–5V
03810-025
16-/14-BIT
DATA
16-/14-BIT
DATA
2
+5V
5
6
4
GND
V
IN
TRIM
U3
ADR03
V
OUT
V
DD
R
OFS
R3
470kΩ
U4
AD5170
10kΩ
B
R7
1kΩ
R
OFSA
VOUT
0V TO +2.5V
R
FB
R
FBA
C6
GND
U1
AD5546/AD5556
I
OUT
R2R1
R
COMA
R1A
+2.5V
VREFA
U2B
AD8628
–
+
C4
1µF
C5
0.1µF
+5V
WR
WR
LDAC
LDAC
RS
RS
MSB
MSB
C2
0.1µF
C1
1µF
C3
0.1µF V+
V–
U2A
AD8628
+
–
C7
–2.5V
V+
V–
Figure 23. Full Span Calibration
Data Sheet AD5546/AD5556
Rev. D | Page 15 of 20
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 11 lists some of the references
available from Analog Devices that are suitable for use with this
range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources, they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit is
determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
VREF node (the voltage output node in this application) of the
DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 12 and Table 13.
Table 11. Suitable Analog Devices Precision References
Part No. Output Voltage (V) Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C) ISS (mA) Output Noise (µV p-p) Package(s)
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-5, SC70-5
ADR02 5.0 0.06 3 1 10 SOIC-8
ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5
ADR03 2.5 0.1 3 1 6 SOIC-8
ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5
ADR06 3.0 0.1 3 1 10 SOIC-8
ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5
ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8
ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8
ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8
ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8
ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8
ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8
ADR391 2.5 0.16 9 0.12 5 TSOT-5
ADR395 5.0 0.10 9 0.12 8 TSOT-5
AD5546/AD5556 Data Sheet
Rev. D | Page 16 of 20
Table 12. Suitable Analog Devices Precision Op Amps
Part No. Supply Voltage (V)
VOS Maximum
(µV)
IB Maximum
(nA)
0.1 Hz to 10 Hz
Noise (µV p-p) Supply Current (µA) Package(s)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8
AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8
AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8
ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5
AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5
AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8
AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5
AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-23-5
AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8
Table 13. Suitable Analog Devices High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) VOS (Max) (µV) IB (Max) (nA) Package(s)
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5
AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8
AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
ADA4899-1 5 to 12 600 310 35 100 LFCSP-8, SOIC-8
AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8
AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8
AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8
AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8
AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8
Data Sheet AD5546/AD5556
Rev. D | Page 17 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AE
28 15
141
8°
0°
SEATING
PLANE
COPLANARITY
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
Figure 24. 28-Lead Thin Shrink Small Outline Package [TSSOP]
RU-28
Dimensions shown in millimeters
ORDERING GUIDE
Model1
RES
(Bit)
DNL
(LSB)
INL
(LSB)
Temperature
Range (°C) Package Description Package Option Ordering Quantity
AD5546BRU 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 50
AD5546BRU-REEL7 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 1,000
AD5546BRUZ 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 50
AD5546BRUZ-REEL7 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 1,000
AD5546CRUZ 16 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50
AD5546CRUZ-REEL7 16 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 1,000
AD5556CRU 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50
AD5556CRU-REEL7 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 1,000
AD5556CRUZ 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50
EVAL-AD5546SDZ Evaluation Board
1 Z = RoHS Compliant Part.
AD5546/AD5556 Data Sheet
Rev. D | Page 18 of 20
NOTES
Data Sheet AD5546/AD5556
Rev. D | Page 19 of 20
NOTES
AD5546/AD5556 Data Sheet
Rev. D | Page 20 of 20
NOTES
©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03810-0-11/11(D)