NT1GD64S8HA0F-75B - Nanya Technology Corporation

NT1GD64S8HA0F

1GB

PC2700 and PC2100

Unbuffered DDR DIMM

REV 2.1 1

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

184 pin Unbuffered DDR DIMM

Based on DDR333/266 512M bit A Die device

Features

• 184 Dual In-Line Memory Module (DIMM)

• Unbuffered DDR DIMM based on 512M bit die A device,

organized as either 64Mbx8

• Performance:

PC2700

PC2100

Speed Sort 6K 75B

DIMM

CAS

Latency 2.5 2.5 Unit

fCK Clock Frequency 166 133 MHz

tCK Clock Cycle 6 7.5 ns

fDQ DQ Burst Frequency 333 266 MHz

• Intended for 133 and 166 MHz applications

• Inputs and outputs are SSTL-2 compatible

• VDD = VDDQ = 2.5V ± 0.2V

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM

CAS

Latency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts

• SDRAMs are packaged in BGA packages

Description

NT1GD64S8HA0F is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered Dual In-Line Memory Module

(UDIMM). NT1GD64S8HA0F is organized as two ranks of 64Mbx64 high-speed memory array and uses sixteen 64Mbx8 DDR SDRAMs

BGA packages.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves

high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation

type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC and the remaining are

available for use by the customer.

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 2

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Ordering Information

Part Number Organization

Speed Power Leads

NT1GBD64S8HA0F-6K 128Mx64 DDR333

PC2700

2.5-3-3

166MHz (6ns @ CL = 2.5)

133MHz (7.5ns @ CL = 2)

NT1GBD64S8HA0F-75B 128Mx64 DDR266B

PC2100

2.5-3-3

133MHz (7.5ns @ CL = 2.5)

100MHz (10ns @ CL = 2)

2.5V Gold

For the closest sales office or information, please visit: www.nanya.com

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 3

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Pin Description

CK0, CK1, CK2,

CK0

CK1

CK2

Differential Clock Inputs. DQ0-DQ63 Data input/output

CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes

RAS

Row Address Strobe

DM0-DM7 Input Data Mask

CAS

Column Address Strobe VDD Power

Write Enable VDDQ Supply voltage for DQs

Chip Selects VSS Ground

A0-A9, A1 1, A12 Address Inputs NC No Connect

A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input

BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output

VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs

VDDID V

DD Identification flag. VDDSPD Serial EEPROM positive power supply

Pinout

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 VREF 93 VSS 32 A5 124 VSS 62 VDDQ 154

RAS

2 DQ0 94 DQ4 33 DQ24 125 A6 63

155 DQ45

3 VSS 95 DQ5 34 VSS 126 DQ28 64 DQ41 156 VDDQ

4 DQ1 96 VDDQ 35 DQ25 127 DQ29 65

CAS

157

5 DQS0 97 DM0/DQS9 36 DQS3 128 VDDQ 66 VSS 158

6 DQ2 98 DQ6 37 A4 129 DM3/DQS12 67 DQS5 159 DM5/DQS14

7 VDD 99 DQ7 38 VDD 130 A3 68 DQ42 160 VSS

8 DQ3 100 VSS 39 DQ26 131 DQ30 69 DQ43 161 DQ46

9 NC 101 NC 40 DQ27 132 VSS 70 VDD 162 DQ47

10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC

11 VSS 103 NC 42 VSS 134 NC 72 DQ48 164 VDDQ

12 DQ8 104 VDDQ 43 A1 135 NC 73 DQ49 165 DQ52

13 DQ9 105 DQ12 44 NC 136 VDDQ 74 VSS 166 DQ53

14 DQS1 106 DQ13 45 NC 137 CK0 75

CK2

167 NC

15 VDDQ 107 DM1/DQS10 46 VDD 138

CK0

76 CK2 168 VDD

16 CK1 108 VDD 47 NC 139 VSS 77 VDDQ 169 DM6/DQS15

CK1

109 DQ14 48 A0 140 NC 78 DQS6 170 DQ54

18 VSS 110 DQ15 49 NC 141 A10 79 DQ50 171 DQ55

19 DQ10 111 CKE1 50 VSS 142 NC 80 DQ51 172 VDDQ

20 DQ11 112 VDDQ 51 NC 143 VDDQ 81 VSS 173 NC

21 CKE0 113 NC 52 BA1 144 NC 82 VDDID 174 DQ60

22 VDDQ 114 DQ20 KEY KEY 83 DQ56 175 DQ61

23 DQ16 115 A12 53 DQ32 145 VSS 84 DQ57 176 VSS

24 DQ17 116 VSS 54 VDDQ 146 DQ36 85 VDD 177 DM7/DQS16

25 DQS2 117 DQ21 55 DQ33 147 DQ37 86 DQS7 178 DQ62

26 VSS 118 A11 56 DQS4 148 VDD 87 DQ58 179 DQ63

27 A9 119 DM2/DQS11 57 DQ34 149 DM4/DQS13 88 DQ59 180 VDDQ

28 DQ18 120 VDD 58 VSS 150 DQ38 89 VSS 181 SA0

29 A7 121 DQ22 59 BA0 151 DQ39 90 WP 182 SA1

30 VDDQ 122 A8 60 DQ35 152 VSS 91 SDA 183 SA2

31 DQ19 123 DQ23 61 DQ40 153 DQ44 92 SCL 184 VDDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 4

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Input/Output Functional Description

Symbol Type Polarity Function

CK0, CK1, CK2,

CK0

CK1

CK2

(SSTL) Cross

point

The system clock inputs. All address and command lines are sampled on the cross point of

the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is synchronized to the input

clock.

CKE0, CKE1 (SSTL) Active

High

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when lo w.

deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

(SSTL) Active

Low

Enables the associated DDR SDRAM command decoder when low and disables the

command

decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S

0; Bank 1 is

selected by S1.

RAS

CAS

(SSTL) Active

Low When sampled at the positive rising edge of the clock,

RAS

CAS

define the operation to

be executed by the SDRAM.

VREF Supply

Reference voltage for SSTL-2 inputs

VDDQ Supply Isolated pow

er supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1 (SSTL) -

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A1 1, A12 (SSTL) -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) whe

sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9

)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke auto-precharge operation at the end of the B

urst Read or Write cycle. If AP is high,

auto-

precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) t

o precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63 (SSTL) -

Data and Check Bit input/output pins operate in the same manner as on

conventional

DRAMs.

DQS0 - DQS7,

DQS9 – DQS16 (SSTL) Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

CB0 – CB7 (SSTL) - Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

DM0 – DM8 Input Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write op

eration if it is high.

In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-

CB7, and is

not used on x64 modules.

VDD, VSS Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 – SA2 -

Address inputs. Connected to either VDD or VSS

on the system board to configure th e Serial

Presence Detect EEPROM address.

SDA -

This bi-

directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

SCL -

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

VDDSPD Supply

Serial EEPROM positive power supply.

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 5

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

2 Ranks, 16 devices, 64Mx8 DDR SDRAMs

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

A0-A13

RAS

BA0-BA1 BA0-BA1 : SDRAMs D0-D15

A0-A13 : SDRAMs D0-D15

RAS

: SDRAMs D0-D1 5

CKE0

CAS CAS

: SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D1 5

: SDRAMs D0-D15

CKE1

VDDSPD

VSS

VREF

VDDID

VDD/VDDQ

Strap: see Note 4

SPD

D0-D15

* Wire per Clock Loadi ng Table/

Wiring Diagrams

* Clock Wiring

Clock Input SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

4 SDRAMs

6 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/C KE/S relationshi ps must be maint ained as shown.

3. DQ, DQS, DM/DQ S resistors: 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

DM0/DQS9

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS0 DM4/DQS13

DQS4

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DM1/DQS10

DQS1

DQS

DM2/DQS11

DQS2

DM3/DQS12

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS5

DM5/DQS14

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6/DQS15

DQS7

DM7/DQS16

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D10

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D11

DQS I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7

I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D12

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D13

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D14

DQS

I/O 0

I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D15

DQS

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 6

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Serial Presence Detect

SPD Description

Byte Description Byte Description

0 Number of Serial PD Bytes Written during Production 26 Maximum Data Access Time from Clock at CL=1

1 Total Number of Bytes in Serial PD device 27 Minimum Row Precharge Time (tRP)

2 Fundamental Memory Type 28 Minimum Row Active to Row Active delay (tRRD)

3 Number of Row Addresses on Assembly 29 Minimum RAS to CAS delay (tRCD)

4 Number of Column Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS)

5 Number of DIMM Rank 31 Module Bank Density

6 Data Width of Assembly 32 Address and Command Setup Time Before Clock

7 Data Width of Assembly (cont’) 33 Address and Command Hold Time After Clock

8 Voltage Interface Level of this Assembly 34 Data Input Setup Time Before Clock

9 DDR SDRAM Device Cycle Time

CL=2.5 35 Data Input Hold Time After Clock

10 DDR SDRAM Device Access Time from Clock

CL=2.5 36-40 Reserved

11 DIMM Configuration Ty pe 41 Minimum Active/Auto-refresh Time (tRC)

12 Refresh Rate/Type 42 Auto-refresh to Active/Auto-refresh Command Period

(tRFC)

13 Primary DDR SDRAM Width 43 Max Cycle Time (tCK max)

14 Error Checking DDR SDRAM Device Width 44 Maximum DQS-DQ Skew Time (tDQSQ)

15 DDR SDRAM Device Attr: Min CLK Delay , Random Col

Access 45 Maximum Read Data Hold Skew Factor (tQHS)

16 DDR SDRAM Device Attributes: Burst Length

Supported 46-61 Reserved

17 DDR SDRAM Device Attributes: Number of Device

Banks 62 SPD Revision

18 DDR SDRAM Device Attributes:

CAS Latencies Supported 63 Checksum Data

19 DDR SDRAM Device Attributes: CS Latency 64-71 Manufacturer’s JEDEC ID Code

20 DDR SDRAM Device Attributes: WE Latency 72 Module Manufacturing Location

21 DDR SDRAM Device Attributes: 73-90 Module Part number

22 DDR SDRAM Device Attributes: General 91-92 Module Revision Code

23 Minimum Clock Cycle

CL=2.5 93-94

Module Manufacturing Data

yy= Binary coded decimal year code, 0-99(Decimal),

00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal),

01-34(Hex)

24 Maximum Data Access Time from Clock at

CL=2 95-98 Module Serial Number

25 Minimum Clock Cycle Time at CL=1 99-127 Reserved

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 7

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

SPD Values for NT1GD64S8HA0F

PC2700 (6K) PC2100 (75B)

Byte

Value

Hex

Byte

Value

128

256

SDRAM DDR

x64

SSTL 2.5V

6.0ns

7.5ns

.0ns

7.5ns

Non

Parity

Non

Parity

SR/1x(

7.8

us)

SR/1x(

7.8

us)

N/A

1 Cloc

1 Clock

2,4,8

2/2.5

Differential Clock

0.2V Tolerance

7.5ns

0.7

0.75ns

N/A

20ns

15ns

20ns

45ns

512

0.90ns

5ns

0.50ns

5ns

0.50ns

Reserved

60ns

72ns

12ns

0.4ns

0.5

0.55ns

5ns

Reserved

Initial

Checksum

64-71 NANYA

7F7F7F0B

00000000

NANYA 7F7F7F0B

00000000

Assembly

Asse

mbly

Module PN

Revision

Year/Week Code

Serial Number

127

Reserved

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 8

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to VSS -0.5 to VDDQ +0.5 V

VIN Voltage on Input relative to VSS -0.5 to +3.6 V

VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V

TA Operating Temperature (Ambient) 0 to +70 °C

TSTG Storage Te mperature (Plastic) -55 to +150 °C

PD Power Dissipation (per device component) 1 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress

rating only, and functional operation of the device at these or any other conditions above those indicated in the operational secti

ons of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics and Operating Conditions

TA= 0°C ~ 70°C; VDDQ= VDD= 2.5V±0.2V(PC2100,PC2700)

Symbol Parameter Min Max Units Notes

VDD Supply Voltage 2.3 2.7 V 1

VDDQ I/O Supply Voltage 2.3 2.7 V 1

VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ

0.51 x VDDQ V 1, 2

VTT I/O Termination Voltage (System) VREF – 0.04 VREF + 0.04 V 1, 3

VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1

VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1

VIN (DC) Input Voltage Level, CK and

Inputs -0.3 VDDQ + 0.3 V 1

VID (DC) Input Differential Voltage, CK and

Inputs 0.30 VDDQ + 0.6 V 1, 4

II Input Leakage Current

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) -10 10 µA 1

IOZ Output Leakage Current

(DQs are disabled; 0V ≤ Vout ≤ VDDQ -10 10 µA 1

IOH Output High Current

(VOUT = VDDQ -0.373V, min VREF, min VTT) -16.8 - mA 1

IOL Output Low Current

(VOUT = 0.373, max VREF, max VTT) 16.8 - mA 1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 9

Mar 16, 2004

Preliminary © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

AC Characteristics

Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the

related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to

the crossing point for CK,

), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions.

The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW

(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700)

Symbol

Parameter/Condition Min Max Unit Notes

VIH (AC) Input High (Logic 1) Voltage. VREF + 0.31 V 1, 2

VIL (AC) Input Low (Logic 0) Voltage. VREF



- 0.31 V 1, 2

VID (AC) Input Differential Voltage, CK and

Inputs 0.62 VDDQ + 0.6 V 1, 2, 3

VIX (AC) Input Differential Pair Cross Point Voltage, CK and

Inputs (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 10

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

Operating, Standby, and Refresh Currents

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700)

Symbol

Parameter/Condition Notes

IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle 1,2

IDD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (M IN); IOUT

= 0mA; address and

control inputs changing once per clock cycle 1,2

IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD2N Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once

per clock cycle 1,2

IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 1,2

IDD3N Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN)

; DQ, DM , and

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,2

IDD4R Operating Current: one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1,2

IDD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and cont

rol inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1,2

IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 1,2,3

IDD6 Self-Refresh Current: CKE ≤ 0.2V 1,2

IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of

data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8

s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8

All IDD current values are calculated from device level.

NT1GD64S8HA0F

Symbol

(mA)

PC2700

(6K)

PC2100

(75B)

IDD0 2630 2070

IDD1 2790 2470

IDD2P 255 255

IDD2N 680 680

IDD3P 306 306

IDD3N 1190 1190

IDD4R 3270 3270

IDD4W 3510 3190

IDD5 5830 4870

IDD6 68 68

IDD7 6790 6390

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 11

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700) (Part 1 of 2)

6K 75B Unit Notes

Symbol Parameter

Min. Max. Min. Max.

tAC DQ output access time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4

tDQSCK DQS output access time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4

tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4

tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4

CL=2.5 6 12 7.5 12 ns 1-4

tCK Clock cycle time CL=2 7.5 12 10 12 ns 1-4

tDH DQ and DM input hold time 0.45 0.5 ns 1-4,

15, 16

tDS DQ and DM input setup time 0.45 0.5 ns 1-4,

15, 16

tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4

tHZ Data-out high-impedance time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4, 5

tLZ Data-out low-impedance time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4, 5

tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.45 0.5 ns 1-4

tHP Minimum half clk period for any given cycle; defined

by clk high (tCH) or clk low (tCL) time tCH or

tCL tCH or

tCL t

CK 1-4

tQH Data output hold time from DQS tHP -

tQHS tHP -

tQHS t

CK 1-4

tQHS Data hold Skew Factor 0.55 0.75 ns 1-4

tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 tCK 1-4

tDQSL,

tDQSH DQS input low (high) pulse width

(write cycle) 0.35 0.35 tCK 1-4

tDSS DQS falling edge to CK setup time

(write cycle) 0.2 0.2 tCK 1-4

tDSH DQS falling edge hold time from CK

(write cycle) 0.2 0.2 tCK 1-4

tMRD Mode register set command cycle time 2 2 tCK 1-4

tWPRES Write preamble setup time 0 0 ns 1-4, 7

tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 1-4, 6

tWPRE Write preamble 0.25 0.25 tCK 1-4

tIH Address and control input hold time

(fast slew rate) 0.75 0.9 ns

2-4, 9,

11, 12

tIS Address and control input setup time

(fast slew rate) 0.75 0.9 ns

2-4, 9,

11, 12

tIH Address and control input hold time

(slow slew rate) 0.8 1.0 ns

2-4,

10, 11,

12, 14

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 12

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700) (Part 2 of 2)

6K 75B Unit Notes

Symbol Parameter

Min. Max. Min. Max.

tAC DQ output access time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4

tDQSCK DQS output access time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4

tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4

tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4

CL=2.5 6 12 7.5 12 ns 1-4

tCK Clock cycle time CL=2 7.5 12 10 12 ns 1-4

tDH DQ and DM input hold time 0.45 0.5 ns 1-4,

15, 16

tDS DQ and DM input setup time 0.45 0.5 ns 1-4,

15, 16

tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4

tHZ Data-out high-impedance time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4, 5

tLZ Data-out low-impedance time from CK/

-0.7 +0.7 -0.75 +0.75 ns 1-4, 5

tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.45 0.5 ns 1-4

tHP Minimum half clk period for any given cycle; defined

by clk high (tCH) or clk low (tCL) time tCH or

tCL tCH or

tCL t

CK 1-4

tQH Data output hold time from DQS tHP -

tQHS tHP -

tQHS t

CK 1-4

tQHS Data hold Skew Factor 0.55 0.75 ns 1-4

tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 tCK 1-4

tDQSL,

tDQSH DQS input low (high) pulse width

(write cycle) 0.35 0.35 tCK 1-4

tDSS DQS falling edge to CK setup time

(write cycle) 0.2 0.2 tCK 1-4

tDSH DQS falling edge hold time from CK

(write cycle) 0.2 0.2 tCK 1-4

tMRD Mode register set command cycle time 2 2 tCK 1-4

tWPRES Write preamble setup time 0 0 ns 1-4, 7

tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 1-4, 6

tWPRE Write preamble 0.25 0.25 tCK 1-4

tIH Address and control input hold time

(fast slew rate) 0.75 0.9 ns

2-4, 9,

11, 12

tIS Address and control input setup time

(fast slew rate) 0.75 0.9 ns

2-4, 9,

11, 12

tIH Address and control input hold time

(slow slew rate) 0.8 1.0 ns

2-4,

10, 11,

12, 14

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 13

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

AC Timing Specification Notes

1. Input slew rate = 1V/ns.

2. The CK/

input reference level (for timing reference to CK/

) is the point at which CK and

cross: the input reference level for

signals other than CK/

is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific

voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition

is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the

bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from

high to low at this time, depending on tDQSS.

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

11. CK/

slew rates are >= 1.0 V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design

or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock

cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate Delta (tIS) Delta (tIH) Unit Note

0.5 V/ns 0 0 ps 1, 2

0.4 V/ns +50 0 ps 1, 2

0.3 V/ns +100 0 ps 1, 2

1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate Delta (tDS) Delta (tDH) Unit Note

0.5 V/ns 0 0 ps 1, 2

0.4 V/ns +75 +75 ps 1, 2

0.3 V/ns +150 +150 ps 1, 2

1. I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note

0.0 ns/V 0 0 ps 1-4

0.25 ns/V +50 +50 ps 1-4

0.5 ns/V +100 +100 ps 1-4

1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising

transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V

Using the table above, this would result in an increase in tDS and tDH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 14

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

Package Dimensions

Non-ECC, 16 BGA devices

Note: Device packaging not drawn to scale. Placed only for references

FRONT

Detail A Detail B

Θ 2.5

10.0

0.394

133.35

131.35

128.95

17.80

2.3

25.4

(2X) 4.00

Detail A

1.27 Pitch

Detail B

1.00 Width

3.80

1.80

6.35

4.00

Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated.

Units: Millimeters

BACK SIDE

(Front)

1.27 +/- 0.10

4.00

NT1GD64S8HA0F

1GB

Unbuffered DDR DIMM

REV 2.1 15

Mar 16, 2004

NANYA reserves the right to change products and specifications without notice.

Revision Log

Rev Date Modification

1.0 Dec 12,2003 Release

1.2 Dec 19,2003 Updated IDD with values calculated from devices..

2.0 Mar 12, 2004

Document reorganized by order of die generation / size and DIMM format.

Die: A, 512Mb

DIMM: unbuffered DIMM

Speed grades: 6K, 75B

Module: NT1GD64S8HA0F

2.1 Mar 16, 2004 Updated module drawings.

Updated SPD information.

Nanya Technology Corporation

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Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

Please visit our home page for more information: www.nanya.com

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its products for any particular purpose. Nanya assumes no liability arising ou t of the application or use of its products. All parameters can and do vary in its application and must

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