NT1GD64S8HA0F 1GB PC2700 and PC2100 Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM Based on DDR333/266 512M bit A Die device Features * 184 Dual In-Line Memory Module (DIMM) * DRAM DLL aligns DQ and DQS transitions with clock transitions * Unbuffered DDR DIMM based on 512M bit die A device, * Address and control signals are fully synchronous to positive organized as either 64Mbx8 clock edge * Performance: * Programmable Operation: - DIMM CAS Latency: 2, 2.5 PC2700 PC2100 Speed Sort fCK tCK 6K 75B DIMM CAS Latency 2.5 2.5 Clock Frequency 166 133 Clock Cycle fDQ DQ Burst Frequency - Burst Type: Sequential or Interleave Unit - Burst Length: 2, 4, 8 - Operation: Burst Read and Write MHz 6 7.5 ns 333 266 MHz * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * Intended for 133 and 166 MHz applications * 7.8 s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-2 compatible * Serial Presence Detect EEPROM * VDD = VDDQ = 2.5V 0.2V * Gold contacts * SDRAMs have 4 internal banks for concurrent operation * SDRAMs are packaged in BGA packages * Differential clock inputs * Data is read or written on both clock edges Description NT1GD64S8HA0F is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM). NT1GD64S8HA0F is organized as two ranks of 64Mbx64 high-speed memory array and uses sixteen 64Mbx8 DDR SDRAMs BGA packages. Depending on the speed grade, these DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC and the remaining are available for use by the customer. REV 2.1 Mar 16, 2004 Preliminary 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Ordering Information Part Number Organization NT1GBD64S8HA0F-6K 128Mx64 Speed Power Leads 2.5V Gold PC2700 166MHz (6ns @ CL = 2.5) DDR333 2.5-3-3 133MHz (7.5ns @ CL = 2) NT1GBD64S8HA0F-75B PC2100 133MHz (7.5ns @ CL = 2.5) 128Mx64 DDR266B 2.5-3-3 100MHz (10ns @ CL = 2) For the closest sales office or information, please visit: www.nanya.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 REV 2.1 Mar 16, 2004 Preliminary 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Pin Description CK0, CK1, CK2, CK0, CK1, CK2 Differential Clock Inputs. DQ0-DQ63 Data input/output CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes Row Address Strobe DM0-DM7 Input Data Mask RAS CAS WE S0, S1 Column Address Strobe VDD Power Write Enable VDDQ Supply voltage for DQs Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 93 VSS 32 A5 124 VSS 62 VDDQ 154 2 DQ0 94 DQ4 33 DQ24 125 A6 63 WE RAS 155 DQ45 3 VSS 95 DQ5 34 VSS 126 DQ28 64 DQ41 156 VDDQ 4 DQ1 96 VDDQ 35 DQ25 127 DQ29 65 CAS 157 5 DQS0 97 DM0/DQS9 36 DQS3 128 VDDQ 66 VSS 158 S0 S1 6 DQ2 98 DQ6 37 A4 129 DM3/DQS12 67 DQS5 159 DM5/DQS14 7 VDD 99 DQ7 38 VDD 130 A3 68 DQ42 160 VSS 8 DQ3 100 VSS 39 DQ26 131 DQ30 69 DQ43 161 DQ46 9 NC 101 NC 40 DQ27 132 VSS 70 VDD 162 DQ47 10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC 11 VSS 103 NC 42 VSS 134 NC 72 DQ48 164 VDDQ 12 DQ8 104 VDDQ 43 A1 135 NC 73 DQ49 165 DQ52 13 DQ9 105 DQ12 44 NC 136 VDDQ 74 VSS 166 DQ53 14 DQS1 106 DQ13 45 NC 137 CK0 75 167 NC VDDQ 107 DM1/DQS10 46 VDD 138 CK0 CK2 15 76 CK2 168 VDD 16 CK1 108 VDD 47 NC 139 VSS 77 VDDQ 169 DM6/DQS15 17 CK1 109 DQ14 48 A0 140 NC 78 DQS6 170 DQ54 18 VSS 110 DQ15 49 NC 141 A10 79 DQ50 171 DQ55 19 DQ10 111 CKE1 50 VSS 142 NC 80 DQ51 172 VDDQ 20 DQ11 112 VDDQ 51 NC 143 VDDQ 81 VSS 173 NC 21 CKE0 113 NC 52 BA1 144 NC 82 VDDID 174 DQ60 22 VDDQ 114 DQ20 83 DQ56 175 DQ61 KEY KEY 23 DQ16 115 A12 53 DQ32 145 VSS 84 DQ57 176 VSS 24 DQ17 116 VSS 54 VDDQ 146 DQ36 85 VDD 177 DM7/DQS16 25 DQS2 117 DQ21 55 DQ33 147 DQ37 86 DQS7 178 DQ62 26 VSS 118 A11 56 DQS4 148 VDD 87 DQ58 179 DQ63 27 A9 119 DM2/DQS11 57 DQ34 149 DM4/DQS13 88 DQ59 180 VDDQ 28 DQ18 120 VDD 58 VSS 150 DQ38 89 VSS 181 SA0 29 A7 121 DQ22 59 BA0 151 DQ39 90 WP 182 SA1 30 VDDQ 122 A8 60 DQ35 152 VSS 91 SDA 183 SA2 31 DQ19 123 DQ23 61 DQ40 153 DQ44 92 SCL 184 VDDSPD Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 2.1 Mar 16, 2004 Preliminary 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2, CK0, CK1, CK2 (SSTL) CKE0, CKE1 (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the (SSTL) Active Low RAS, CAS, WE (SSTL) Active Low VREF Supply VDDQ Supply BA0, BA1 (SSTL) S0, S1 command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP A11, A12 (SSTL) - invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS7, DQS9 - DQS16 (SSTL) Active High CB0 - CB7 (SSTL) - DM0 - DM8 Input Active High VDD, VSS Supply SA0 - SA2 - SDA - SCL - VDDSPD REV 2.1 Mar 16, 2004 Preliminary Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Functional Block Diagram 2 Ranks, 16 devices, 64Mx8 DDR SDRAMs S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS D0 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 CS DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 BA0-BA1 : SDRAMs D0-D15 A0-A13 A0-A13 : SDRAMs D0-D15 RAS CAS RAS : SDRAMs D0-D15 CAS : SDRAMs D0-D15 CKE0 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 SPD D0-D15 D0-D15 D0-D15 VDDSPD VDD/VDDQ VREF VSS VDDID Strap: see Note 4 CKE : SDRAMs D0-D7 CKE : SDRAMs D8-D15 CKE1 WE Notes : 1. 2. 3. 4. DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 WE : SDRAMs D0-D15 CS D7 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 * Clock Wiring Clock Input SDRAMs *CK0/CK0 4 SDRAMs 6 SDRAMs *CK1/CK1 6 SDRAMs *CK2/CK2 * Wire per Clock Loading Table/ Wiring Diagrams Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 2.1 Mar 16, 2004 Preliminary 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Serial Presence Detect SPD Description Byte 0 Description Number of Serial PD Bytes Written during Production Byte 26 Description Maximum Data Access Time from Clock at CL=1 1 Total Number of Bytes in Serial PD device 27 Minimum Row Precharge Time (tRP) 2 Fundamental Memory Type 28 Minimum Row Active to Row Active delay (tRRD) 3 Number of Row Addresses on Assembly 29 Minimum RAS to CAS delay (tRCD) 4 Number of Column Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS) 5 Number of DIMM Rank 31 Module Bank Density 6 Data Width of Assembly 32 Address and Command Setup Time Before Clock 7 Data Width of Assembly (cont') 33 Address and Command Hold Time After Clock 8 Voltage Interface Level of this Assembly 34 Data Input Setup Time Before Clock 35 Data Input Hold Time After Clock 9 10 11 DDR SDRAM Device Cycle Time CL=2.5 DDR SDRAM Device Access Time from Clock 36-40 CL=2.5 DIMM Configuration Type 41 Reserved Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period 12 Refresh Rate/Type 42 13 Primary DDR SDRAM Width 43 Max Cycle Time (tCK max) Error Checking DDR SDRAM Device Width 44 Maximum DQS-DQ Skew Time (tDQSQ) 45 Maximum Read Data Hold Skew Factor (tQHS) 14 15 16 17 18 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length 46-61 Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported (tRFC) Reserved 62 SPD Revision 63 Checksum Data 19 DDR SDRAM Device Attributes: CS Latency 64-71 Manufacturer's JEDEC ID Code 20 DDR SDRAM Device Attributes: WE Latency 72 Module Manufacturing Location 21 DDR SDRAM Device Attributes: 73-90 22 DDR SDRAM Device Attributes: General 91-92 Module Part number Module Revision Code Module Manufacturing Data 23 yy= Binary coded decimal year code, 0-99(Decimal), Minimum Clock Cycle 93-94 CL=2.5 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 24 25 Maximum Data Access Time from Clock at 95-98 Module Serial Number 99-127 Reserved CL=2 Minimum Clock Cycle Time at CL=1 REV 2.1 Mar 16, 2004 Preliminary 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM SPD Values for NT1GD64S8HA0F PC2700 (6K) PC2100 (75B) Byte Value Hex Byte Value 0 128 80 128 80 1 256 08 256 08 2 SDRAM DDR 07 SDRAM DDR 07 3 13 0D 13 0D 4 11 0B 11 0B 5 2 02 2 02 6 x64 40 x64 40 7 x64 00 x64 00 8 SSTL 2.5V 04 SSTL 2.5V 04 9 6.0ns 60 7.5ns 75 10 7.0ns 70 7.5ns 75 11 Non-Parity 00 Non-Parity 00 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 x8 08 x8 08 14 N/A 00 N/A 00 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2/2.5 0C 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Differential Clock 20 Differential Clock 20 22 0.2V Tolerance 00 0.2V Tolerance 00 23 7.5ns 75 10ns A0 24 0.70ns 70 0.75ns 75 25 N/A 00 N/A 00 26 N/A 00 N/A 00 27 18ns 48 20ns 50 28 12ns 30 15ns 3C 29 18ns 48 20ns 50 30 42ns 2A 45ns 2D 31 512MB 80 512MB 80 32 0.75ns 75 0.90ns 90 33 0.75ns 75 0.90ns 90 34 0.45ns 45 0.50ns 50 35 0.45ns 45 0.50ns 50 36-40 Reserved 00 Reserved 00 41 60ns 3C 65ns 41 42 72ns 48 75ns 4B 43 12ns 30 12ns 30 44 0.4ns 28 0.5ns 32 45 0.55ns 55 0.75ns 75 46-61 Reserved 00 Reserved 00 62 Initial 00 Initial 00 63 Checksum 7D Checksum 64-71 NANYA 7F7F7F0B NANYA 00000000 64 7F7F7F0B 00000000 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 2.1 Mar 16, 2004 Preliminary 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation (per device component) 1 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA= 0C ~ 70C; VDDQ= VDD= 2.5V0.2V(PC2100,PC2700) Symbol VDD VDDQ VSS, VSSQ Parameter Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V VREF Supply Voltage, I/O Supply Voltage I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 -10 10 A 1 -10 10 A 1 -16.8 - mA 1 16.8 - mA 1 Input Leakage Current II Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current IOZ (DQs are disabled; 0V Vout VDDQ Output High Current IOH (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current IOL (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 2.1 Mar 16, 2004 Preliminary 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max VREF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 2.1 Mar 16, 2004 Preliminary 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W Parameter/Condition clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Notes Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level. NT1GD64S8HA0F PC2700 PC2100 (mA) (6K) (75B) IDD0 2630 2070 mA IDD1 2790 2470 mA IDD2P 255 255 mA IDD2N 680 680 mA IDD3P 306 306 mA IDD3N 1190 1190 mA IDD4R 3270 3270 mA IDD4W 3510 3190 mA IDD5 5830 4870 mA IDD6 68 68 mA IDD7 6790 6390 mA Symbol REV 2.1 Mar 16, 2004 Preliminary 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) (Part 1 of 2) Symbol tAC 6K Parameter DQ output access time from CK/CK 75B Min. Max. Min. Max. Unit Notes -0.7 +0.7 -0.75 +0.75 ns 1-4 DQS output access time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4 tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4 6 12 7.5 12 ns 1-4 7.5 12 10 12 ns 1-4 tDQSCK CL=2.5 tCK Clock cycle time tDH DQ and DM input hold time 0.45 0.5 ns tDS DQ and DM input setup time 0.45 0.5 ns tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tCK 1-4 tCK 1-4 0.75 ns 1-4 1.25 tCK 1-4 tDQSQ tHP CL=2 DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQH Data output hold time from DQS tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition tDQSL, DQS input low (high) pulse width tDQSH (write cycle) tDSS tDSH tMRD tWPRES 0.45 tCH or tCH or tCL tCL tHP - tHP - tQHS tQHS 0.55 0.75 1.25 0.75 1-4, 15, 16 1-4, 15, 16 0.35 0.35 tCK 1-4 0.2 0.2 tCK 1-4 0.2 0.2 tCK 1-4 Mode register set command cycle time 2 2 tCK 1-4 Write preamble setup time 0 0 ns 1-4, 7 DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 tCK 1-4 0.75 0.9 ns 0.75 0.9 ns 0.8 1.0 ns tIH tIS tIH REV 2.1 Mar 16, 2004 Preliminary Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) 0.60 0.40 0.60 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, Address and control input hold time (slow slew rate) 10, 11, 12, 14 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) (Part 2 of 2) Symbol tAC 6K Parameter DQ output access time from CK/CK 75B Min. Max. Min. Max. Unit Notes -0.7 +0.7 -0.75 +0.75 ns 1-4 DQS output access time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4 tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4 6 12 7.5 12 ns 1-4 7.5 12 10 12 ns 1-4 tDQSCK CL=2.5 tCK Clock cycle time tDH DQ and DM input hold time 0.45 0.5 ns tDS DQ and DM input setup time 0.45 0.5 ns tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tCK 1-4 tCK 1-4 0.75 ns 1-4 1.25 tCK 1-4 tDQSQ tHP CL=2 DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQH Data output hold time from DQS tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition tDQSL, DQS input low (high) pulse width tDQSH (write cycle) tDSS tDSH tMRD tWPRES 0.45 tCH or tCH or tCL tCL tHP - tHP - tQHS tQHS 0.55 0.75 1.25 0.75 1-4, 15, 16 1-4, 15, 16 0.35 0.35 tCK 1-4 0.2 0.2 tCK 1-4 0.2 0.2 tCK 1-4 Mode register set command cycle time 2 2 tCK 1-4 Write preamble setup time 0 0 ns 1-4, 7 DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 tCK 1-4 0.75 0.9 ns 0.75 0.9 ns 0.8 1.0 ns tIH tIS tIH REV 2.1 Mar 16, 2004 Preliminary Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) 0.60 0.40 0.60 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, Address and control input hold time (slow slew rate) 10, 11, 12, 14 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 1. 2. Delta (tIS) Delta (tIH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. 1. 2. Input Slew Rate Delta (tDS) Delta (tDH) Unit 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 Note I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. 1. 2. 3. 4. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in tDS and tDH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 2.1 Mar 16, 2004 Preliminary 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Package Dimensions Non-ECC, 16 BGA devices FRONT 133.35 131.35 Detail B 25.4 17.80 Detail A 2.5 2.3 (2X) 4.00 10.0 0.394 128.95 BACK SIDE 4.00 (Front) 1.27 +/- 0.10 Detail B 3.80 4.00 Detail A 1.00 Width 6.35 1.27 Pitch 1.80 Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters Note: Device packaging not drawn to scale. Placed only for references REV 2.1 Mar 16, 2004 Preliminary 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GD64S8HA0F 1GB Unbuffered DDR DIMM Revision Log Rev Date Modification 1.0 Dec 12,2003 Release 1.2 Dec 19,2003 Updated IDD with values calculated from devices.. Document reorganized by order of die generation / size and DIMM format. Die: A, 512Mb 2.0 Mar 12, 2004 DIMM: unbuffered DIMM Speed grades: 6K, 75B Module: NT1GD64S8HA0F Updated module drawings. 2.1 Mar 16, 2004 Updated SPD information. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must be validated for each customer application by the customer's technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation. Printed in Taiwan (c)2004 REV 2.1 Mar 16, 2004 Preliminary 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.