RT8287ZQW - Richtek - Product.Network

RT8287

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Pin Configurations

(TOP VIEW)

3A, 21V 500kHz Synchronous Step-Down Converter

General Description

The RT8287 is a synchronous step-down regulator with

a n internal power MOSFET. It a chieves 3A of continuous

output current over a wide input supply range with excellent

load and line regulation. Current mode operation provides

fast tran sient response a nd eases loop stabilization.

Fault condition protection includes cycle-by-cycle current

limiting and thermal shutdown. An adjustable soft-start

reduces the stress on the input source at startup.

The RT8287 requires a minimal number of readily available

external components, providing a compa ct solution.

Features

z3A Output Current

zAdjustable Soft-Start

z120mΩΩ

ΩΩ

Ω/40mΩΩ

ΩΩ

Ω Internal Power MOSFET Switch

zInternal Compensation Minimizes External Parts

Count

zFixed 500kHz Frequency

zThermal Shutdown Protection

zCycle-by-Cycle Over Current Protection

zWide 4.5V to 21V Operating Input Range

zAdjustable Output from 0.808V to 15V

zSmall 14-Lead WDFN Package

zRoHS Compliant and Halogen Free

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

WDFN-14L 4x3

Applications

zDistributive Power Systems

zBattery Charger

zDSL Modems

zPre-Regulator for Linear Regulators

VIN

AGND

GND

VCC

BOOT PGOOD

EN FB

GND

Package Type

QW : WDFN-14L 4x3 (W-Type)

RT8287

Lead Plating System

Z : ECO (Ecological Element with

Halogen Free and Pb free)

Marking Information

A8 YM

DNN

A8 : Product Code

YMDNN : Date Code

RT8287

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Function Pin Description

Pin No. Pin Name Pin Function

1 VIN Supply Input. VIN supplies the power to the IC, as well as the step-down

converter switches. Drive VIN with a 4.5V to 21V power source. Bypass VIN to

GND with a suitably lar ge capacitor to eliminate noise on the input to the IC.

2, 3, 4, 5 SW Switch Node. SW is the switching node that supplies power to the output.

Connect the output LC filter from SW to the output load. Note that a capacitor is

required from SW to BOOT to power the high side switch.

6 BOOT

High Side Gate Drive Boost Input. BOOT supplies the drive for the high side

N-MOSFET switch. C onnect a 100nF or greater capacitor from SW to BOOT to

power the high side switch.

7 EN Chip Enable (Active High). For automatic start-up, connect the EN pin to VIN with

a 100kΩ resistor .

8 FB Feedbac k Input. FB senses the output voltage to regulate said voltage. Drive FB

with a resis tive voltage divider from the output voltage. The feedback threshold is

0.808V.

9 PGOOD

Pow e r G ood Out put . Th e output o f th is pi n is open-drain . Powe r g ood threshol d i s

90% low to high and 70% high to low of regulation value.

10 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor

from SS to GND to set the soft-start period.

11 VCC Bias Supply. Decouple with 0.1μF to 0.22μF capacitor. The capacitance should

be no more than 0.22μF.

12, 13

15 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

14 AGND Analog G round. Connect this pin to the system ground in PCB layout.

Typical Application Circuit

Table 1. Recommended Components Selection

VOUT (V) R1 (kΩ) R2 (kΩ) RT (kΩ) L (μH) COUT (μF)

5 75 14 .46 0 4.7 22 x 2

3 .3 75 24 .32 0 3.6 22 x 2

2 .5 75 35 .82 0 3.6 22 x 2

1.8 5 4.07 30 2 22 x 2

1.5 5 5.84 39 2 22 x 2

1 .2 5 10 .31 47 2 22 x 2

1. 05 5 16 .69 47 1.5 22 x 2

1.2V/3A

VIN

PGOOD

VCC

BOOT

2, 3, 4, 5

0.1µF

VOUT

22µF

VIN RT8287

CBOOT

COUT

CIN

SS 10

CSS

47nF

GND

12, 13, 15 (Exposed Pad)

AGND

PGOOD R3

100k

0.1µF

ON/OFF

RT8287

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Function Block Diagram

Driver

Current Sense

Amplifier

PWM

Comparator

Oscillator

500kHz

Ramp

Generator

Regulator

Reference

Error

Amplifier

BOOT

VIN

GND

10µA

PGOOD

VCC

VAVA

400k

30pF

1pF

1.2V

1.7V

1µA

Lockout

Comparator

Shutdown

Comparator

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Absolute Maximum Ratings (Note 1)

zSupply Input V oltage, VIN ---------------------------------------------------------------------------------- −0.3V to 26V

zSwitch Voltage, SW ----------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)

zBoot Voltage, BOOT----------------------------------------------------------------------------------------- (SW − 0.3V) to (SW + 6V)

zOther Pins------------------------------------------------------------------------------------------------------ −0.3V to 6V

zPower Dissipation, PD @ TA = 25°C

WDFN-14L 4x3------------------------------------------------------------------------------------------------ 1.667W

zPa ckage Thermal Re sistance (Note 2)

W DF N-14L 4x3, θJA ------------------------------------------------------------------------------------------ 60°C/W

WDFN-14L 4x3, θJC ------------------------------------------------------------------------------------------ 7°C/W

zJunction T emperature---------------------------------------------------------------------------------------- 150°C

zLead T emperature (Soldering, 10 sec.)------------------------------------------------------------------ 26 0°C

zStorage T emperature Range ------------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

zSupply Input V oltage, VIN ---------------------------------------------------------------------------------- 4.5V to 21V

zJunction T emperature Range------------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

Shutdown Current ISHDN V

EN = 0 -- 0 1 μA

Quiescent Current IQ V

EN = 2 V, V FB = 1V -- 0.7 -- mA

Upper Switch On Resistance RDS(ON)1 -- 120 -- mΩ

Lower Switch On Resistance RDS(ON)2 -- 40 -- mΩ

S witch Leakage ILEAK V

EN = 0 V, V SW = 0V or 12V -- 0 10 μA

Current Limit ILIMIT V

BOOT − VSW = 4.8V 5.4 6.5 -- A

O scillato r Freque ncy fSW V

FB = 0.75V 425 500 575 kHz

Short Circuit Frequency VFB = 0V -- 150 -- kHz

Maximum Duty Cycle DMAX V

FB = 0.8V -- 90 -- %

M in i mum On T ime tON -- 100 -- ns

Fe edb ack Vol tag e VFB 4.5V ≤ VIN ≤ 21V 0.796 0.808 0.82 V

Fe edb ack Cu rre nt IFB -- 10 50 nA

Logic-High VIH 2 -- 5.5

EN Th resh old

Voltage Logic-Low VIL -- -- 0.4

EN = 2V -- 1 --

Enable Current V

EN = 0V -- 0 -- μA

(VIN = 12V, TA = 25°C unless otherwise specified)

RT8287

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Parameter Symbol Test Conditions Min Typ Max Unit

Power Good Rising Threshold -- 90 -- %

Power Good Falling Threshold -- 70 -- %

Power Good Delay -- 20 -- μs

Power Good Sink Current

Capability Sink 4mA -- -- 0.4 V

Power Good Leakage Current -- 10 -- nA

Under Voltage Lockout

Threshold VUVLO V

IN Rising 3.8 4 4.2 V

Under Voltage Lockout

Threshold Hysteresis ΔVUVLO -- 400 -- mV

VCC Regulator -- 5 -- V

VCC Load Regulation ICC = 5mA -- 5 -- %

Soft -Start Period tSS C

SS = 47nF -- 4.7 -- ms

Thermal Shutdown TSD -- 150 -- °C

Thermal Shutdown Hysteresis ΔTSD -- 30 -- °C

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.bsolute maximum rating conditions for extended periods may remain possibility to affect device

reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

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Output Vo ltage vs. Output Current

1.210

1.212

1.214

1.216

1.218

1.220

1.222

1.224

1.226

0 0.5 1 1.5 2 2.5 3

Output Current (A)

Output Vol tage (V)

VIN = 12V, VOUT = 1.22V, IOUT = 0A to 3A

Reference Voltage vs. Temperature

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

-50 -25 0 25 50 75 100 125

Temperatur e (°C)

Reference Vol tage (V)

Typical Operating Characteristics

Switching Frequency vs. Input Voltage

350

375

400

425

450

475

500

525

550

4 6 8 10 12 14 16 18 20 22

Input Vo ltage (V)

Switchi ng Frequency (kH z) 1

VOUT = 1.22V, IOUT = 0.8A

Switching Frequency vs. Tem pe rature

350

375

400

425

450

475

500

525

550

-50-25 0 25 50 75100125

Temperatu re (°C )

Switchi ng Frequency (kH z) 1

VIN = 12V, VOUT = 1.22V, IOUT = 1A

Efficiency vs. Output Current

100

0 0.5 1 1.5 2 2.5 3

Output Current (A)

Effi ciency (% )

VOUT = 1.22V, IOUT = 0A to 3A

VIN = 12V

VIN = 21V

Reference Voltage v s. Input Voltage

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

0.830

4 6 8 10 12 14 16 18 20 22

In put Voltage (V)

Reference Volt age(V)

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Current Lim it vs. Input Voltage

4 6 8 10 12 14 16 18 20 22

In put Voltage (V)

Cur rent Limit (A)

Current Lim it vs. Tem perature

-50-25 0 25 50 75100125

Temperatur e (°C)

Current Li m it (A)

VIN = 12V, VOUT = 1.22V

VIN = 12V, VOUT = 1.22V, IOUT = 0A to 3A

Load Transient Response

Time (100μs/Div)

IOUT

(2A/Div)

VOUT

(200mV/Div)

Output Voltage Ripple

Time (1μs/Div)

(2A/Div)

VSW

(10V/Div)

VIN = 12V, IOUT = 1A

VOUT

(50mV/Div) VOUT

(50mV/Div)

Output Voltage Ripple

Time (1μs/Div)

(2A/Div)

VSW

(10V/Div)

VIN = 12V, IOUT = 3A

VIN = 12V, VOUT = 1.22V, IOUT = 1A to 3A

Load Transient Response

Time (100μs/Div)

IOUT

(2A/Div)

VOUT

(200mV/Div)

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Power On from VIN

Time (5ms/Div)

(5A/Div)

VOUT

(1V/Div)

VIN

(10V/Div)

VIN = 12V, VOUT = 1.22V, IOUT = 3A

VPGOOD

(5V/Div)

Power On from EN

Time (2.5ms/Div)

(5A/Div)

VOUT

(1V/Div)

VEN

(5V/Div)

VIN = 12V, VOUT = 1.22V, IOUT = 3A

VPGOOD

(5V/Div)

Power Off from EN

Time (50μs/Div)

(5A/Div)

VOUT

(1V/Div)

VEN

(5V/Div)

VIN = 12V, VOUT = 1.22V, IOUT = 3A

VPGOOD

(5V/Div)

Power Off from VIN

Time (50ms/Div)

(5A/Div)

VOUT

(1V/Div)

VIN

(10V/Div)

VIN = 12V, VOUT = 1.22V, IOUT = 3A

VPGOOD

(5V/Div)

RT8287

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Application Information

The IC is a synchronous high voltage buck converter that

can support the input voltage range from 4.5V to 21V and

the output current ca n be up to 3A.

Output Voltage Setting

The output voltage is set by a n extern al resistive divider

a ccording to the following equation :

⎛⎞

⎜⎟

⎝⎠

OUT FB R1

V = V1

RT8287

GND

VOUT

Figure 1. Output Voltage Setting

Figure 2. External Bootstra p Diode

where VFB is the feedback reference voltage 0.808V (typ.).

The resistive divider allows the FB pin to sense a fra ction

of the output voltage a s shown in Figure 1.

External Bootstrap Diode

Connect a 100nF low ESR ceramic capacitor between

the BOOT pin and SW pin as shown in Figure 2. This

ca pacitor provides the gate driver voltage for the high side

MOSFET. It is recommended to add an external bootstra p

diode between an external 5V and BOOT pin for efficiency

improvement when input voltage is lower than 5.5V or duty

ratio is higher than 65% .The bootstrap diode can be a

low cost one such as IN4148 or BA T54. The external 5V

ca n be a 5V fixed input from system or a 5V output of the

IC. Note that the external boot voltage must be lower tha n

5.5V.

Soft-Start

The IC contains an external soft-start cla mp that gradually

raises the output voltage. The soft-start timing is

programmed by the external capacitor between SS pin

and GND. The chip provides an internal 10μA charge current

for the extern al ca pa citor . If 47nF ca pa citor is used to set

the soft-start, the period will be 4.7ms (typ.).

Under Voltage Lockout Threshold

The IC includes an input Under V oltage Lockout Protection

(UVLO). If the input voltage exceeds the UVLO rising

threshold voltage (4.2V), the converter resets and prepares

the PWM for operation. If the input voltage falls below the

UVLO falling threshold voltage (3.8V) during normal

operation, the device stops switching. The UVLO rising

and falling threshold voltage includes a hysteresis to

prevent noise caused reset.

Chip Enable Operation

The EN pin is the chip enable input. Pulling the EN pin

low (<0.4V) will shut down the device. During shutdown

mode, the IC quiescent current drops to lower tha n 1μA.

Driving the EN pin high (>2V, < 5.5V) will turn on the

device again. For external timing control (e.g.RC), the EN

pin can also be externally pulled high by adding a REN*

resistor and CEN* capacitor from the VIN pin, as can be

seen from the Figure 5.

An external MOSFET can be added to implement digital

control on the EN pin when front age system voltage below

2.5V is available, as shown in Figure 3. In this case, a

100kΩ pull-up resistor, REN, is connected between VIN

and the EN pin. MOSFET Q1 will be under logic control to

pull down the EN pin.

To prevent enabling circuit when VIN is smaller than the

VOUT target value, a resistive voltage divider can be placed

between the input voltage a nd ground and connected to

the EN pin to adjust IC lockout threshold, as shown in

Figure 4. For exa mple, if an 8V output voltage is regulated

from a 12V input voltage, the resistor REN2 can be selected

to set input lockout threshold larger than 8V.

BOOT

100nF

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Figure 3. Ena ble Control Circuit for Logic Control with Low Voltage

Figure 4. The Resistors ca n be Selected to Set IC Lockout Threshold

OUT OUT

LIN

I = 1

fL V

⎡⎤⎡ ⎤

Δ×−

⎢⎥⎢ ⎥

⎣⎦⎣ ⎦

OUT OUT

L(MAX) IN(MAX)

L = 1

fI V

⎡⎤⎡ ⎤

×−

⎢⎥⎢ ⎥

×Δ

⎣⎦⎣ ⎦

Power Good Output

The power good output is an open-drain output and requires

a pull up resistor . When the output voltage is 70% below

its set voltage, PGOOD will be pulled low. It is held low

until the output voltage returns to within the allowed

tolerances once more. During soft-start, PGOOD is actively

held low and only allowed to transition high after soft-start

is over and the output voltage ha s rea ched 90% of its set

voltage.

Under Output Voltage Protection-Hiccup Mode

For the IC, Hiccup Mode of Under V oltage Protection (UVP)

is provided. When the FB voltage drops below half of the

feedback reference voltage, VFB, the UVP function will be

triggered and the IC will shut down for a period of time and

then recover automatically . The Hiccup Mode of UVP ca n

reduce input current in short-circuit conditions.

Having a lower ripple current reduces not only the ESR

losses in the output ca pacitors but also the output voltage

ripple. Highest efficiency operation is achieved by reducing

ripple current at low frequency, but it requires a large

inductor to attain this goal.

For the ripple current selection, the value of ΔIL = 0.24(IMAX)

will be a rea sonable starting point. The largest ripple current

occurs at the highest VIN. To guarantee that the ripple

current stays below a specified maximum, the inductor

value should be chosen according to the following

equation :

VIN

PGOOD

VCC

BOOT

2, 3, 4, 5

VOUT

VIN

RT8287

CBOOT

COUT

CIN

SS 10

CSS

PGOOD R3

REN

100k

Chip Enable

100k

GND

12, 13, 15 (Exposed Pad)

AGND

47nF

VIN

PGOOD

VCC

BOOT

2, 3, 4, 5

VOUT

VIN

RT8287

CBOOT

COUT

CIN

SS 10

CSS

PGOOD R3

REN

100k

REN2

GND

12, 13, 15 (Exposed Pad)

AGND

47nF

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ΔIL increa ses with higher VIN and decreases

with higher inductance.

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The inductor's current rating (caused a 40°C temperature

rising from 25°C ambient) should be greater than the

maximum load current and its saturation current should

be greater than the short circuit peak current limit. Plea se

see Table 2 for the inductor selection reference and it is

highly recommended to keep inductor value as close as

possible to the recommended inductor values for each

VOUT as shown in Table 1.

Compo nent S uppl ier Series Dimensions (mm)

TDK V LF10045 10 x 9.7 x 4. 5

TDK S LF12565 12. 5 x 12 .5 x 6.5

TA IYO YUDEN N R8040 8 x 8 x 4

Table 2. Suggested Inductors for Typical

Application Circuit

OUT IN

RMS OUT(MAX) IN OUT

I = I 1

−

This formula ha s a maximum at VIN = 2VOUT, where IRMS =

IOUT / 2. This simple worst case condition is commonly

used for design because even significant deviations do

not offer much relief.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design.

For the input capacitor, one 22μF low ESR ceramic

capacitors are recommended. For the recommended

ca p a citor , plea se refer to ta ble 3 for more detail.

Table 3. Suggested Capacitors for CIN and COUT

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

Loop stability can be checked by viewing the load transient

response.

The output ripple, ΔVOUT, is determined by :

OUT L OUT

VIESR

8fC

⎡⎤

Δ≤Δ +

⎢⎥

⎣⎦

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However , care must

be taken when these capacitors are used at input and

output. When a ceramic capacitor is used at the input

a nd the power is supplied by a wall ada pter through long

wires, a load step at the output can induce ringing at the

input, VIN. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

cause a voltage spike at VIN large enough to da mage the

part.

Thermal Shutdown

Thermal shutdown is implemented to prevent the chip from

operating at excessively high temperatures. When the

junction temperature is higher than 150°C, the chip will

shut down the switching operation. The chip will

automatically resume switching, once the junction

temperature cools down by a pproxi mately 30°C.

Input and Output Capacitors Selection

The input capacitance, CIN, is needed to filter the

trapezoidal current at the source of the high side MOSFET .

To prevent large ripple current, a low ESR input ca pacitor

sized for the maximum RMS current should be used. The

RMS current is given by :

Location Component Supplier Part No. Capacitanc e (μF) C ase Size

CIN MURATA GRM32ER71C226M 22 1210

CIN TDK C3225X5R1C226M 22 1210

COUT MURATA GRM31CR60J476M 47 1206

COUT TDK C3225X5R0J476M 47 1210

COUT MURATA GRM32ER71C226M 22 1210

COUT TDK C3225X5R1C226M 22 1210

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EMI Consideration

Since para sitic inductance and capacitance effects in PCB

circuitry would cause a spike voltage on SW pin when

high side MOSFET is turned-on/off, this spike voltage on

SW may impact on EMI performance in the system. In

order to enhance EMI performance, there are two methods

to suppress the spike voltage. One way is by pla cing an

R-C snubber (RS*, CS*) between SW and GND and locating

them as close as possible to the SW pin, as shown in

Figure 5. Reference Circuit with Snubber and Enable Timing Control

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction to a mbient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

a mbient thermal resistance, θJA, is layout dependent. For

WDFN-14L 4x3 package, the thermal resistance, θJA, is

60°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25°C can

be calculated by the following formula :

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for

W DF N-14L 4x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. The derating curve in Figure 6 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 6. Derating Curve of Maximum Power Dissipation

VIN

PGOOD

VCC

BOOT

2, 3, 4, 5

VOUT

VIN

RT8287

CBOOT

COUT

CIN

SS 10

CSS

PGOOD R3

REN*

100k

CEN*CS*

RS*

* : Optional

GND

12, 13, 15 (Exposed Pad)

AGND

47nF

Figure 5. Another method is by adding a resistor in series

with the bootstrap capacitor, CBOOT, but this method will

decrea se the driving ca pability to the high side MOSFET.

It is strongly recommended to reserve the R-C snubber

during PCB layout for EMI improvement. Moreover,

reducing the SW tra ce area a nd keeping the main power

in a small loop will be helpful on EMI performance. For

detailed PCB layout guide, please refer to the section

Layout Considerations.

0.00

0.30

0.60

0.90

1.20

1.50

1.80

0 255075100125

Ambient Tem peratur e (°C)

Maximum Power Di ssipation (W ) 1

Four-Layer PCB

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Layout Considerations

Follow the PCB layout guidelines for optimal performance

of the IC.

`Keep the tra ces of the main current paths as short a nd

wide as possible.

`Put the input ca pacitor as close a s possible to the device

pins (VIN and GND).

`SW node is with high frequency voltage swing and

should be kept at small area. Keep analog components

away from the SW node to prevent stray ca pacitive noise

pickup.

Figure 7. PCB Layout Guide

`Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the IC.

`Connect all analog grounds to a common node and then

connect the common node to the power ground behind

the output ca p a citors.

`An example of PCB layout guide is shown in Figure 7

for reference.

VIN

AGND

GND

VCC

BOOT PGOOD

EN FB

GND

CIN

CBOOT

VOUT COUT

GND

VOUT

CSS

RTR1

GND

Place the input and output

capacitors as close to the

IC as possible.

SW should be

connected to

inductor by wide

and short trace and

keep sensitive

components away

from this trace.

Place the

feedback as

close to the IC

as possible.

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Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Outline Dimension

W-Type 14L DFN 4x3 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options

Dime nsions In Millimet e rs Dimensions In In che s

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.900 4.100 0.154 0.161

D2 3.250 3.350 0.128 0.132

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018