Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 TPD4S214 USB OTG Companion Device with VBUS Over Voltage Protection, Over Current Protection, and Four Channel ESD Protection 1 Features 3 Description * * The TPD4S214 is a single-chip protection solution for USB On-the-Go (OTG) and other current limited USB applications. This device includes an integrated low RDS(ON) N-channel current limited switch for the OTG current supply to peripheral devices. TPD4S214 offers low capacitance transient voltage suppression (TVS) electrostatic discharge (ESD) clamping diodes for the D+, D-, and ID pins for both USB2.0 and USB3.0 applications. The VBUS pin can handle continuous voltage ranging from -7 V to 30 V. The over voltage lock-out (OVLO) at the VBUS pin ensures that if there is a fault condition at the VBUS line, TPD4S214 is able to isolate it and protect the internal circuitry from damage. Similarly, the under voltage lock out (UVLO) at the VOTG_IN pin ensures that there is no power drain from the internal OTG supply to external VBUS if VOTG_IN droops below a safe operating level. When EN is high, the OTG switch is activated and the FLT pin indicates whether there is a fault condition. The soft start feature waits 16 ms to turn on the OTG switch after all operating conditions are met. 1 * * * * * * * * * * * * * * * Input Voltage Protection at VBUS from -7 V to 30 V IEC61000-4-2 Level 4 ESD Protection - 15-kV Contact Discharge - 15-kV Air Gap Discharge IEC 61000-4-5 Surge Protection - 7.8 A (8/20 s) Low RDS(ON) N-CH FET Switch for High Efficiency Compliant with USB2.0 and USB3.0 OTG spec User Adjustable Current Limit From 250 mA to Beyond 1.2 A Built-in Soft-start Reverse Current Blocking Over Voltage Lock Out for VBUS Under Voltage Lock Out for VOTG_IN Thermal Shutdown and Short Circuit Protection Auto Retry on any Fault; No Latching Off States Integrated VBUS Detection Circuit Low Capacitance TVS ESD Clamp for USB2.0 High Speed Data Rate Internal 16ms Startup Delay Space Saving WCSP (12-YFF) Package UL Listed and CB File No. E169910 Device Information(1) PART NUMBER TPD4S214 PACKAGE WCSP (12) BODY SIZE (MAX) 1.39 mm x 1.69 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 2 Applications * * * * Cell Phones Tablet, eBook Portable Media Players Digital Camera 4 Simplified Schematic OTG 5 V Source COTG* System Side Supply (1.8 V to 3.6 V) VOTG_IN ADJ USB Connector VBUS VBUS TPD4S214 USB Controller D+ D+ D- D- ID ID DET FLT EN GND CBUS* 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Thermal Shutdown .................................................... 5 Electrical Characteristics for EN, FLT, DET, D+, D-, VBUS, ID Pins ............................................................. 5 7.7 Electrical characteristics for UVLO / OVLO .............. 6 7.8 Electrical Characteristics for DET Circuits ................ 6 7.9 Electrical Characteristics for OTG Switch ................. 6 7.10 Electrical Characteristics for Current Limit and Short Circuit Protection........................................................ 7 7.11 Supply Current Consumption.................................. 7 7.12 Typical Characteristics ............................................ 8 8 Detailed Description ............................................ 11 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 17 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application ................................................. 18 10 Power Supply Recommendations ..................... 22 11 Layout................................................................... 22 11.1 Layout Guidelines ................................................. 22 11.2 Layout Example .................................................... 22 12 Device and Documentation Support ................. 23 12.1 12.2 12.3 12.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 23 5 Revision History Changes from Revision E (January 2015) to Revision F * Added UL and CB certifications. ........................................................................................................................................... 1 Changes from Revision D (October 2014) to Revision E * 2 Page Changed the device From: Product Preview To: Production data ......................................................................................... 1 Changes from Revision B (February 2013) to Revision C * Page Changed the Product Preview data sheet.............................................................................................................................. 1 Changes from Revision A (February 2013) to Revision B * Page Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Original (January 2013) to Revision A * Page Added RLOAD TEST CONDITIONS to IOCP in the Electrical Characteristics for Current Limit and Short Circuit Protection table. ..................................................................................................................................................................... 7 Changes from Revision C (August 2013) to Revision D * Page Page YFF PACKAGE Changed the YFF package dimensions ....................................................................................................... 3 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 6 Pin Configuration and Functions TPD4S214 WCSP (YFF) PIN MAPPING (TOP SIDE/SEE-THROUGH VIEW) 2 3 A VOTG_N DET VBUS B VOTG_IN FLT VBUS C EN GND ID D ADJ D- D+ 1.69 mm 1 1.39 mm Pin Functions NAME PIN TYPE D- D2 I/O USB data- DESCRIPTION D+ D3 I/O USB data+ ID C3 I/O USB ID signal FLT B2 O Open-Drain Output. Connect a pull-up resistor from FLT to the supply voltage of the host system. ADJ D1 I Attach external resistor to adjust the current limit EN C1 I Enable Input. Drive EN high to enable the OTG switch. VBUS A3, B3 O USB Power Output VOTG_IN A1, B1 I USB OTG Supply Input DET A2 O Open-Drain Output. Connect a pull-up resistor from DET to the supply voltage of the host system. GND C2 Ground Connect to PCB ground plane Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 3 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Tstg Storage temperature range -40 85 C VOTG_IN, ADJ, EN Input voltage -0.5 7 V VBUS Output voltage to USB connector -7 30 V FLT, DET Output voltage -0.5 7 Input clamp current VI < 0 IOUT Continuous current through FLT and DET output IGND Continuous current through GND TJ(max) maximum junction temperature -65 UNIT V -50 mA 10 mA 100 mA 150 C D+, D-, ID, VBUS pins IEC 61000-4-2 Contact Discharge at 25C 15 kV D+, D-, ID, VBUS pins IEC 61000-4-2 Air-gap Discharge at 25C 15 kV D+, D-, ID pins Peak Pulse Current (tp = 8/20 s) at 25C 7.8 A D+, D-, ID pins Peak Pulse Power (tp = 8/20 s) at 25C 84 W (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) Electrostatic discharge IEC 61000-4-2 Contact Discharge (2) UNIT 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) IEC 61000-4-2 Air-gap Discharge (1) (1) V 500 D+, D-, ID, VBUS Pins 15000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TA Operating free-air temperature -40 VIH High-level input voltage EN 1.2 VIL Low-level input voltage EN tEN EN ramp rate for proper turn on Valid ramp rate is between 10 s and 100 ms, rising and falling tUVLO_SLEW VOTG_IN ramp rate for proper UVLO operation tOVLO_SLEW VBUS ramp rate for proper OVLO operation TA_VBUS_ATT Time to detect VBUS device attachment and turn on DET 4 TYP MAX 85 UNIT C V 0.4 V 0.01 100 ms Valid ramp rate is between 10 s and 100 ms, rising and falling 0.01 100 ms Valid ramp rate is between 10 s and 100 ms, rising and falling 0.01 100 ms 200 ms Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 7.4 Thermal Information TPD4S214 THERMAL METRIC (1) YFF UNIT 12 PINS RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance 0.5 RJB Junction-to-board thermal resistance 40.0 JT Junction-to-top characterization parameter 3.0 JB Junction-to-board characterization parameter 39.0 (1) 89.1 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Thermal Shutdown over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX UNIT TSHDN+ Shutdown temp rising 141 C TSHDN- Shutdown temp falling 125 C THYST Thermal-shutdown Hysteresis 16 C PMAX Maximum power dissipation TJMAX Junction Temp at max power dissipation VOTG_IN = 5 V, Rload = 5 , EN = 5 V, RADJ = 75 K 0.16 W 150 C MAX UNIT 7.6 Electrical Characteristics for EN, FLT, DET, D+, D-, VBUS, ID Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP IIL_EN EN pin input leakage current EN = 3.3 V 1 IOL FLT, DET pin output leakage current FLT, DET = 3.6 V 1 A VOL_FLT Low-level output voltage FLT VBUS or VOTG_IN = 5 V or 0 V IOL = 100 A 100 mV VOL_DET Low-level output voltage DET VBUS and VOTG_IN = 5 V or 0 V IOL = 100 A 100 mV CEN Enable capacitance VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple, VOTG_IN = 5 V VD Diode forward voltage D+, D-, ID pins; lower IO = 8 mA clamp diode 0.95 V IL_D Leakage current on D+, D-, ID Pins D+, D-, ID = 3.3 V 100 nA CIO Differential capacitance between the D+, D- lines VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple, VOTG_IN = 5 V 0.04 pF CIO VBR RDYN Capacitance to GND for the D+, D- lines Capacitance to GND for the ID lines 4.5 1.9 Breakdown voltage D+, D-, ID pins Ibr = 1 mA 6 Breakdown voltage on VBUS Ibr = 1 mA 33 Dynamic on resistance D+, D-, ID clamps pF 1.9 VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple, VOTG_IN = 5 V V Submit Documentation Feedback Product Folder Links: TPD4S214 pF V 1 Copyright (c) 2013-2015, Texas Instruments Incorporated A 5 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 7.7 Electrical characteristics for UVLO / OVLO over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT UNDER-VOLTAGE LOCKOUT VUVLO+ Under-voltage lock-out, input power detected threshold rising VOTG_IN increasing from 0 V to 5 V, No load on VBUS pin 3.4 3.6 3.8 V VUVLO- Under-voltage lock-out, input power detected threshold falling VOTG_IN decreasing from 5 V to 0 V, No load on VBUS pin 3.0 3.2 3.5 V VHYS-UVLO Hysteresis on UVLO of VUVLO+ and VUVLO- TRUVLO Recovery time from UVLO VOTG_IN increasing from 0V to 5V, No load on VBUS pin; time from VOTG_IN = VUVLO+ to FLT toggles high TRESP_UVLO Response time for UVLO VOTG_IN decreasing from 5V to 0V, No load on VBUS pin; time from VOTG_IN = VUVLO- to FLT toggles low 260 mV 18 ms 0.18 s OUTPUT OVERVOLTAGE LOCKOUT VOVP+ OVLO rising threshold Both VOTG_IN and VBUS increasing from 5 V to 7 V 5.55 6.15 6.45 VOVP- OVLO falling threshold Both VOTG_IN and VBUS decreasing from 7 V to 5 V 5.4 6 6.3 VHYS-OVP Hysteresis on OVLO of VUVLO+ and VUVLO- TROVLO Recovery time from OVLO TRESP_OVLO Response time for OVLO V V 100 mV Both VOTG_IN and VBUS decreasing from 7 V to 5 V, VOTG_IN = 5 V; time from VBUS = VOVP- to FLT toggles high 9 ms Both VOTG_IN and VBUS increasing from 5 V to 7 V, VOTG_IN = 5 V; time from VBUS = VOVP+ to FLT toggles low 17 s 7.8 Electrical Characteristics for DET Circuits over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VBUS_VALID- Valid VBUS voltage detect PARAMETER VBUS = 7 V to 0 V TEST CONDITIONS 2.7 2.9 3 UNIT V VBUS_VALID+ Valid VBUS voltage detect VBUS = 0 V to 7 V 5.3 5.4 5.6 V TDET_DELAY- VBUS detect propagation delay- VBUS 0 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID- MIN to DET toggles high 4.9 s TDET_DELAY+ VBUS detect propagation delay+ VBUS 6 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID+ MAX to DET toggles low 1.8 s 7.9 Electrical Characteristics for OTG Switch over operating free-air temperature range (unless otherwise noted) TYP MAX UNIT RDS_ON OTG switch resistance PARAMETER TA = 25 C, VBUS = 5 V, IOUT = 100 mA, RADJ = 75 k (1) 263 290 m VDROP OTG switch voltage drop VBUS = 5 V, IOUT = 100 mA, RADJ = 75 k 12.6 29 mV IOTG_OFF_30V Leakage current at 30V IOTG_OFF_2V Leakage current at-2V IOTG_OFF Standby Leakage current TEST CONDITIONS Measured at VOTG_IN MIN VBUS = 30 V, EN = 5 V, VOTG_IN = 5 V 6 VBUS = 30 V, EN = 5 V, VOTG_IN = 0 V 11 A nA VBUS = -2 V, EN = 5 V, VOTG_IN = 5 V 30 A VBUS = 0 V, EN = 0 V, VOTG_IN = 5 V 32 A VBUS = 5 V, EN = 0 V, VOTG_IN = 0 V 10 nA VBUS = 5 V, EN = 5 V, VOTG_IN = 0V 1 nA VBUS = 5.5 V, EN = 5 V, VOTG_IN = 5 V 6 A IBUS_REV Reverse Leakage current TON Turn-ON time RL = 100 , CL = 1 F, RADJ = 75 k 16 ms TOFF_EN Turn-OFF time RL = 100 , CL = 1 F, RADJ = 75 k, toggle EN 80 s TOFF_OTG Turn-OFF time RL = 100 , CL = 1 F, RADJ = 75 k, toggle VOTG_IN 0.5 s TRISE Output rise time RL = 100 , CL = 1 F, RADJ = 75 k 137 s TFALL Output fall time RL = 100 , CL = 1 F, RADJ = 75 k 1.6 s (1) 6 RDS(ON) is measured at 25C Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 7.10 Electrical Characteristics for Current Limit and Short Circuit Protection over operating free-air temperature range (unless otherwise noted) PARAMETER Current-limit threshold (maximum DC output current IOUT delivered to load) IOCP TEST CONDITIONS VOTG_IN = 5 V, RLOAD = 2.0 MIN TYP MAX RADJ = 226 k (1) 235 245 281 RADJ = 75 k (1) 735 792 830 RADJ = 62 k (1) 885 959 1005 (1) 1128 1200 1363 RADJ = 45 k TBLANK Blanking time after enable TDEGL TDET_SC ms Deglitch time while enabled 9.4 ms Response time to short circuit 10 s 13 ms 153 ms Short circuit regulation time TOCP Short circuit over current protection time VSHORT Short circuit threshold IINRUSH (1) mA 4 TREG Inrush current during a startup VOTG_IN = 5 V RL = 1 , CL = 1 F, RADJ = 75 k UNIT VOTG_IN = 5 V, RL = 100 , CL = 1 F, RADJ = 75 k, apply short to ground Hiccup pulse width; auto-retry time Hiccup pulse period 4 SeeFigure 23 under test configuration RL = 100 , CL = 22 F, RADJ = 75 k V 726 mA External resistor tolerance is 1% 7.11 Supply Current Consumption over operating free-air temperature range (unless otherwise noted) PARAMETER IVOTG_INON High-level VOTG_IN operating current consumption TEST CONDITIONS VOTG_IN = 5 V, No load on VBUS, EN = 5 V TYP MAX UNIT RADJ = 75 k 162 200 A RADJ = 226 k 150 200 A Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 7 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 7.12 Typical Characteristics 400 1.8 40C 1.6 250mA 350 25C 1.4 Switch Resistance (m 85C 1.0 0.8 0.6 0.4 250 200 150 100 50 0.2 0.0 0 50 100 150 200 250 300 350 40 400 RADJ (k ) 20 4.5 0.9 4.0 0.8 3.5 0.7 3.0 0.6 2.5 0.5 2.0 0.4 Voltage (V) 1.0 Current (A) Voltage (V) 5.0 0.3 1.5 1.0 0.2 Votgin Vbus Iotgin 0.5 0.0 15 30 45 60 75 90 105 0.1 0.0 2 20 40 60 80 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 2 4 6 8 10 12 14 16 Time (s) Voltage (V) Current (A) Voltage (V) C002 C004 Figure 4. 10 Load to Short, 2 s 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 100 Time (s) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 Votgin Vbus Iotgin 5 C005 Figure 5. 10 Load to Short, 20 s 8 0 C003 Votgin Vbus Iotgin 0 80 Votgin Vbus Iotgin Figure 3. Inrush, RADJ = 75 k 20 60 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 120 Time (s) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 40 Figure 2. RDSON vs. Temperature 1.1 0 20 Temperature (C) Figure 1. IOCP vs. RADJ 5.5 15 0 C001 Current (A) 0 Submit Documentation Feedback 0 5 10 15 Time (ms) Current (A) Current (A) 1.2 500mA 300 20 C006 Figure 6. 10 Load to Short, 5 ms Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 Votgin Vbus Iotgin 0 100 200 300 400 3 0 3 6 Gain (dB) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 100 Current (A) Voltage (V) Typical Characteristics (continued) 15 18 21 24 500 Time (ms) 9 12 27 1M C007 10M 100M 1G 10G Frequency (Hz) C008 Figure 7. 10 Load to Short, 100 ms Figure 8. Data Line Insertion Loss 70 ID D+ D 60 ID D+ D 10 50 0 40 10 Voltage (V) Voltage (V) 20 30 20 20 30 10 40 0 50 10 60 20 70 15 0 15 30 45 60 75 90 105 120 135 150 165 180 Time (ns) 15 0 Time (ns) Figure 9. +8 kV Contact, 1 GHz C010 Figure 10. -8 kV Contact, 1 GHz 2.4 7 VBUS EN FLT 2.2 6 2.0 1.8 5 1.6 Voltage (V) Capacitance (pF) 15 30 45 60 75 90 105 120 135 150 165 180 C009 1.4 1.2 1.0 0.8 4 3 2 0.6 0.4 1 0.2 0.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VBIAS (V) 4.5 5.0 5 Figure 11. CIO vs. VBIAS, f = 1 MHz 0 5 10 15 20 Time (ms) C011 25 C012 Figure 12. TPD4S214 Turn On Characteristics Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 9 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) 6 5 VBUS VOTG FLT 5 4 Voltage (V) Voltage (V) 6 VBUS EN FLT 3 4 3 2 2 1 1 0 0 25 0 25 50 75 100 125 150 175 200 Time (s) 225 0 10 20 8 60 70 80 C014 Figure 14. UVLO VBUS 8.0 DET 7.0 Voltage (V) 7 Voltage (V) 50 9.0 VBUS VOTG FLT 9 40 Time (ms) Figure 13. TPD4S214 Turn Off Characteristics 10 30 C013 6 5 4 6.0 5.0 4.0 3.0 3 2 2.0 1 1.0 0 0.0 0 25 50 75 100 125 150 Time (ms) 175 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Time (ms) C015 Figure 15. OVLO 4.0 4.5 C016 Figure 16. VBUS Valid Detect Upper 3.5 VBUS 3.0 DET Voltage (V) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time (ms) 4.5 C017 Figure 17. VBUS Valid Detect Lower 10 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 8 Detailed Description 8.1 Overview The TPD4S214 is a single-chip protection solution for USB On-the-Go and other current limited USB applications. This device includes an integrated low RDS(ON) N-channel current limited switch for OTG current supply to peripheral devices. TPD4S214 offers low capacitance TVS ESD clamps for the D+, D-, and ID pins for both USB2.0 and USB3.0 applications. The VBUS pin can handle continuous voltage ranging from -7 V to 30 V. The OVLO at the VBUS pin ensures that if there is a fault condition at the VBUS line, TPD4S214 is able to isolate it and protect the internal circuitry from damage. Similarly, the UVLO at the VOTG_IN pin ensures that there is no power drain from the internal OTG supply to external VBUS if VOTG_IN droops below a safe operating level. When EN is high, the OTG switch is activated and the FLT pin indicates whether there is a fault condition. The soft start feature waits 16 ms to turn on the OTG switch after all operating conditions are met. The FLT pin asserts low during any one of the following fault conditions: OVLO (VBUS > VOVLO), UVLO condition (VOTG_IN < VUVLO) over temperature, over current, short circuit condition, or reverse-current-condition (VBUS > VOTG_IN). The OTG switch is turned off during any fault condition. Once the switch is turned off, the IC periodically rechecks the faults internally. If the IC returns to normal operating conditions, the switch turns back on and FLT is reset to high. There is also a VBUS detection feature for facilitating USB communication between USB host and peripheral device. If this is not used, the DET pin can be either floating or connected to ground. 8.2 Functional Block Diagram DET OTG Switch VOTG_IN Current Limiting Internal Band Gap Referance VBUS UVLO VBUS Detection + OVLO ADJ FLT Control Logic + Charge Pump EN GND D+ D- ID Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 11 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 8.3 Feature Description 8.3.1 Input Voltage Protection at VBUS from -7 V to 30 V The VBUS pin can handle continuous voltage ranging from -7 V to 30 V. The OVLO at the VBUS pin ensures that if there is a fault condition at the VBUS line, TPD4S214 is able to isolate the fault and protect the internal circuitry from damage. 8.3.2 IEC 61000-4-2 Level 4 ESD Protection The I/O pins can withstand ESD events up to 15-kV contact and air gap. An ESD clamp diverts the current to ground. 8.3.3 Low RDS(ON) N-CH FET Switch for High Efficiency A Low RDS(ON) ensures there is minimal voltage loss when supplying high current to OTG devices. 8.3.4 Compliant with USB2.0 and USB3.0 OTG spec The capability of TPD4S214 to supply greater than 1.2 A of current on VBUS meets or exceeds the USB2.0 and USB3.0 OTG specification. 8.3.5 User Adjustable Current Limit From 250 mA to Beyond 1.2 A The designer can select the over current protection level by selecting the proper RADJ. 8.3.6 Built-in Soft-start The soft start feature waits 16 ms to turn on the OTG switch after all operating conditions are met. 8.3.7 Reverse Current Blocking If VBUS is greater than VOTG_IN by 50 mV, the OTG switch is disabled in 17.5 ms. 8.3.8 Over Voltage Lock Out for VBUS OVLO ensures that an over voltage condition on VBUS disables the OTG switch to protect the system. 8.3.9 Under Voltage Lock Out for VOTG_IN UVLO ensures that an under voltage condition on VBUS disables the OTG switch to protect the system. 8.3.10 Thermal Shutdown and Short Circuit Protection TPD4S214 has an over-temperature protection circuit to protect against system faults or improper use. The basic function of the thermal shutdown (TSD) circuit is to sense when the junction temperature has exceeded the absolute maximum rating and shut down the device until the junction temperature has cooled to a safe level. Short circuit protection prevents any damaging current demand from the system. 8.3.11 Auto Retry on any Fault; no Latching off States In any fault condition, TPD4S214 will reassess VBUS, VOTG_IN, and thermal conditions until a safe state is reached and then enable the OTG switch, eliminating any latched off states. 8.3.12 Integrated VBUS Detection Circuit TPD4S214 has a VBUS detection feature facilitating communication between the USB host and peripheral device. The use of this feature is optional. 8.3.13 Low Capacitance TVS ESD Clamp for USB2.0 High Speed Data Rate The High Speed data lines have a capacitance less than 2 pF, supporting a bandwidth greater than 3 GHz. This easily accommodates the 480-Mbps data rate defined in the USB2.0 specification. 12 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 Feature Description (continued) 8.3.14 Internal 16ms Startup Delay The built-in start up delay allows for voltages on VBUS to reach a steady state after which a 1-A trickle charge slowly turns on the main switch. During the inrush period, the peak inrush current will be limited to no more than the current limit set by the external resistor RADJ. 8.3.15 Space Saving WCSP (12-YFF) Package The 1.69 mm x 1.39 mm (Max) WCSP package is valuable in space constrained designs. 8.3.16 Inrush Current Protection As soon as TPD4S214 is enabled, its logic block detects the presence of any fault conditions highlighted in Table 2. In the absence of any fault condition, a counter waits for 16 ms, after which a 1-A trickle charge slowly turns on the main switch. During the inrush period, the peak inrush current will be limited to no more than the current limit set by the external resistor RADJ. 8.3.17 Input Capacitor (Optional) To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between VOTG_IN and GND. A 10-F ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. 8.3.18 Output Capacitor (Optional) Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD greater than CIN can cause VBUS to exceed VOTG_IN when the system supply is removed. A CIN to CLOAD ratio of 10 to 1 is recommended for minimizing VOTG_IN dip caused by inrush currents during startup. 8.3.19 Current Limit The TPD4S214 provides current limiting protection, which is set by an external resistor connected from the ADJ pin to ground shown in Figure 18. The current limiting threshold IOCP is set by the external resistor RADJ. Figure 19 shows the typical current limit for a corresponding RADJ value with 1% tolerance across the operating temperature range. ADJ RADJ TPD4S214 Figure 18. Current Limit Diagram R ADJ = 55.358 IOCP (1) Where: RADJ = external resistor used to set the current limit (k) IOCP = current limit set by the external RADJ resistor (A) RADJ is placed between the ADJ pin and ground, shown in Figure 18, providing a maximum current limit between 250 mA and 1.2 A. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 13 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com Feature Description (continued) 145 1.8 40C 1.6 5 yrs. at 100% Duty Cycle 25C 125 Junction Temperature (C) 1.4 85C Current (A) 1.2 1.0 0.8 0.6 0.4 105 85 65 45 0.2 0.0 0 50 100 150 200 250 300 RADJ (k ) 350 400 25 0 0.2 0.4 C001 Figure 19. IOCP versus RADJ 0.6 0.8 Current (A) 1 1.2 1.4 Figure 20. IBUS Temperature Derating Curve The temperature derating curve shown in Figure 20 graphs the line where TPD4S214 will have a Mean Time Before Failure (MTBF) of 5 years at a 100% duty cycle for a given junction temperature, Tj, and current on VBUS, or IBUS. MTBF of 5 years at a 100% duty cycle is equivalent to 7.5 years at a 75% duty cycle, or 10 years at a 50% duty cycle. See Equation 2 to calculate the junction temperature. If a current and junction temperature point lie below the curve on the graph then the MTBF will exceed 5 years at a 100% duty cycle, or its equivalent. If above the curve, the MTBF will be decreased. 8.3.20 Thermal Shutdown When the device is ON, current flowing through the device will cause the device to heat up. Overheating can lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into the device. Whenever the junction temperature exceeds 141C, the switch will turn off, thereby limiting the temperature. Once the device cools down to below 125C the switch will turn on if the EN is active and the VBUS voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kickin unless the die temperature reaches 141C, it is generally recommended that care is taken to keep the junction temperature below 125C. Operation of the device above 125C for extended periods of time can affect the longterm reliability of the part. The junction temperature of the device can be calculated using the below formula: Tj = TA + PDRJA (2) Where: Tj = Junction temperature TA = Ambient temperature RJA = Thermal resistance PD = Power Dissipated in device PD = I2RDS(ON) (3) I = Current through device RDS(ON) = Max on resistance of device Example At 0.5 A, the continuous current power dissipation is given by: PD = 0.52 x 0.3 = 0.075 W (4) If the ambient temperature is about 85 C the junction temperature will be: Tj = 85 + (0.075 x 89.1) = 91.7C 14 (5) Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 Feature Description (continued) This implies that, at an ambient temperature of 85C, TPD4S214 can pass a continuous 0.5 A without sustaining damage. Conversely, the above calculation can also be used to calculate the total continuous current the TPD4S214 can handle at any given temperature. The MTBF can be estimated by examining Figure 20. Locating 0.5 A and 91.7 C, the point is below the curve. This implies that the MTBF for this calculation is longer than 5 years at a 100% duty cycle. If the duty cycle is 50% then MTBF exceeds 10 years. 8.3.21 VBUS Detection There are several important protocols defined in [OTG and EH Supplement] that governs communication between Targeted Hosts (A-device) and USB peripherals (B-device). Communication between host and peripheral is usually done on the ID pin only. In the case when two OTG devices that could both act as either host or peripheral are connected, measuring voltage level on VBUS will aid in the handshaking process. If an embedded host instead of a USB peripheral is connected to the OTG device, OTG charging would not be required and the system's OTG source should remain off to conserve power. The TPD4S214 VBUS detection block aids power conservation and is powered from VBUS. See Functional Block Diagram. The DET pin is an open drain PMOS output with default state low. In the event when an A-plug is attached, the system detects ID pin as FALSE, in which case ID pin resistance to ground is less than 10 . For a B-plug, the system detects ID pin as TRUE and ID pin resistance to ground is greater than 100 k. For the system to power a USB device through OTG switch once it is connected, voltage on VBUS should remain below VBUS_VALID MIN within TA_VBUS_ATT of the ID pin becoming FALSE. After this event, the system confirms that the USB device requires power and enables both TPD4S214 and OTG source. However, if VBUS_VALID is detected on VBUS within TA_VBUS_ATT of the ID pin becoming FALSE, there is either a system error or the device connected does not require charging. OTG source remains switched off and the entire sequence would restart when the system detects another FALSE on the ID pin. Table 1. VBUS Detection scheme EN VOTG_IN (VBUS Detect Power) VBUS DET Condition X X VBUS_VALID- < VBUS < VBUS_VALID+ H VBUS within VBUS_VALID X X VBUS_VALID- > VBUS or VBUS > VBUS_VALID+ L VBUS outside of VBUS_VALID X = Don't Care, H = Signal High, and L = Signal Low Figure 21 and Figure 22 shows suggested system level timing diagrams for detecting VBUS according to [OTG and EH Supplement]. Figure 28 shows the application diagram. In Figure 21, DET pin remains low after ID pin becomes FALSE, indicating there is not an active voltage source on VBUS. The USB controller proceeds to turn on OTG 5-V source and the TPD4S214 respectively; this sequence is recommended because TPD4S214 is powered through the OTG source. After a period of tON, current starts to flow through the OTG switch and VBUS is ramped to the voltage level of VOTG_IN. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 15 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com TA_VBUS_ATT ID Pin HIGH TON LOW HIGH VBUS Pin LOW HIGH DET Pin OTG 5V Source LOW HIGH LOW HIGH TPD4S214 EN LOW Figure 21. Timing Diagram for Valid USB Device In Figure 22, DET pin toggles high after an active voltage is detected on VBUS within TA_VBUS_ATT. This indicates that the USB device attached is not suitable for OTG charging and both OTG 5-V source and TPD4S214 remain off. TA_VBUS_ATT ID Pin HIGH LOW HIGH VBUS Pin VBUS_VALID MIN LOW TDET_DELAY HIGH DET Pin LOW HIGH OTG 5V Source LOW HIGH TPD4S214 EN LOW Figure 22. System Level Timing Diagram for invalid USB Device 16 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 8.3.22 Test Configuration TPD4S214 VOTG_IN VBUS RLOAD CLOAD CIN ADJ EN 75 k Figure 23. Inrush Current Test Configuration. Enable is toggled from low to high. See the Application Information section for CIN and CLOAD value recommendations. 8.4 Device Functional Modes Table 2. Device Operation EN VOTG_IN VBUS OCP OTP OTG SW FLT X 0 0 F F OFF L FAULT CONDITION SW Disabled X X X X T OFF L Over Temperature H X X T X OFF L Over Current H VOTG_IN > VUVLO VBUS > VOTG_IN F F OFF L Reverse-current H X VBUS > VOVLO F F OFF L VBUS over-voltage H VOTG_IN < VUVLO X F F OFF L VOTG_IN under-voltage H VOTG_IN > VBUS and VOTG_IN > VUVLO VSHORT < VBUS < VOTG_IN and VSHORT < VBUS < VOVLO F F ON H Normal (SW Enabled) Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 17 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information A USB OTG device's one and only connector is the AB receptacle, which accepts either an A or B plug. When an A-plug is inserted, the OTG device is called the A-device and when a B-plug is inserted it is called the Bdevice. A-device is often times referred to as "Targeted Host" and B-device as "USB peripheral". TPD4S214 supports an OTG device when TPD4S214's system is acting as an A-device and powering the USB interface. The TPD4S214 may also be used in non-OTG applications where it resides on the current source side. 9.2 Typical Application The TPD4S214 is placed next to the USB connector to provide over voltage, over current, and ESD protection for the OTG 5-V source and USB Controller. 9.2.1 USB 2.0 Without Using On-chip VBUS Detect An example using TPD4S214 to protect an OTG 5-V source and USB 2.0 Controller is shown below. This USB Controller does not utilize VBUS detection with the DET pin, so DET is tied to GND. TPD4S214 is placed in the transmitter channel immediately adjacent to the USB connector. The D+, D-, ID pins on TPD4S214 are interchangeable so that each can protect either of the D+, D-, ID pins on the USB connector, the naming convention is just a suggestion. OTG 5 V Source COTG* System Side Supply (1.8 V to 3.6 V) VOTG_IN ADJ USB Connector VBUS VBUS TPD4S214 USB Controller + Detection D+ D+ D- D- ID ID DET FLT EN GND CBUS* Figure 24. USB2.0 Application Diagram Without Using On-chip VBUS Detect *COTG and CBUS have minimum recommended values of 1 F each 18 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 Typical Application (continued) 9.2.1.1 Design Requirements For this example, use the following table as input parameters: Design Parameters Example Value Signal range on VOTG_IN 3.8 V - 5.5 V Signal range on VBUS 0 V - 5.3 V nominal, withstand -7 V to 30 V IBUS_MAX 500 mA RADJ 100 k Drive EN low (disabled) 0 V - 0.4 V Drive EN high (enabled) 1.2 V - 5.5 V 9.2.1.2 Detailed Design Procedure To begin the design process, determine the maximum current expected under normal usage. In this example, the maximum expected current is 500 mA so an RADJ of 100 k was selected to begin current limiting at around 550 mA and protect the OTG system. Fault conditions are monitored by the USB controller by using the FLT Pin. DET is not used and is grounded and can optionally be left floating instead. 9.2.1.3 Application Curves Figure 25. Eye Diagram with no EVM and no IC, Full USB2.0 Speed at 480 Mbps Figure 26. Eye Diagram with TPD4S214EVM but no IC, Full USB2.0 Speed at 480 Mbps Figure 27. Eye Diagram with TPD4S214EVM and IC, Full USB2.0 Speed at 480 Mbps Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 19 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 9.2.2 USB 2.0 Using On-chip VBUS Detect An example using TPD4S214 to protect an OTG 5-V source and USB 2.0 Controller is shown below. This USB Controller monitors VBUS detection with the DET pin. This can be advantageous when a peripheral with an Embedded Host is attached. In this case, if there is a valid voltage present on VBUS there is no need to provide OTG power, so the USB Controller can be programmed to disable the OTG 5-V source, resulting in a power savings. The D+, D-, ID pins on TPD4S214 are interchangeable so that each can protect either of the D+, D-, ID pins on the USB connector, the naming convention is just a suggestion. OTG 5 V Source COTG* System Side Supply (1.8 V to 3.6 V) VOTG_IN ADJ USB Connector VBUS VBUS TPD4S214 D+ D+ D- D- ID ID DET USB Controller FLT EN GND CBUS* Figure 28. USB 2.0 Application Diagram Using On-chip VBUS Detect *COTG and CBUS each have minimum recommended values of 1 F 9.2.2.1 Design Requirements For this example, use the following table as input parameters: Design Parameters Example Value Signal range on VOTG_IN 3.8 V - 5.5 V Signal range on VBUS 0 V - 5.3 V nominal, withstand -7 V to 30 V IBUS_MAX 500 mA RADJ 100 k Drive EN low (disabled) 0 V - 0.4 V Drive EN high (enabled) 1.2 V - 5.5 V 9.2.2.2 Detailed Design Procedure To begin the design process, determine the maximum current expected under normal usage. In this example, the maximum expected current is 500 mA so an RADJ of 100 k was selected to begin current limiting at around 550 mA and protect the OTG system. Fault conditions are monitored by the USB controller by using the FLT Pin. DET Pin is used to facilitate detecting between a USB host and peripheral device on VBUS. 9.2.2.3 Application Curves Refer to Application Curves for related application curves. 20 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 9.2.3 USB 3.0 Without Using On-chip VBUS Detect An example using TPD4S214 to protect an OTG 5-V source and USB 3.0 Controller is shown below. This USB Controller does not utilize VBUS detection with the DET pin, so it is tied to GND. The D+, D-, ID pins on TPD4S214 are interchangeable so that each can protect either of the D+, D-, ID pins on the USB connector, the naming convention is just a suggestion. OTG 5 V Source COTG* System Side Supply (1.8 V to 3.6 V) VOTG_IN ADJ USB Connector TX+ VBUS VBUS TX- TPD4S214 D+ D- D- D+ GND USB Controller + Detection DET RX+ GND ID FLT EN RX- CBUS* *CBUS and COTG each have minimum recommended values of 1 F Figure 29. USB 3.0 Application Diagram Without Using On-chip VBUS Detect 9.2.3.1 Design Requirements For this example, use the following table as input parameters: Design Parameters Example Value Signal range on VOTG_IN 3.8 V - 5.5 V Signal range on VBUS 0 V - 5.3 V nominal, withstand -7 V to 30 V IBUS_MAX 900 mA RADJ 56 k Drive EN low (disabled) 0 V - 0.4 V Drive EN high (enabled) 1.2 V - 5.5 V 9.2.3.2 Detailed Design Procedure To begin the design process, determine the maximum current expected under normal usage. In this example, the maximum expected current is 900 mA so an RADJ of 56 k was selected to begin current limiting at around 1 A and protect the OTG system. Fault conditions are monitored by the USB controller by the FLT Pin. DET is not used and is grounded and can optionally be left floating instead. 9.2.3.3 Application Curves Refer to Application Curves for related application curves. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 21 TPD4S214 SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 www.ti.com 10 Power Supply Recommendations TPD4S214 Is designed to receive power from an OTG 5-V power source. It can operate normally (nFET ON) between 3.8 V and 5.55 V. Thus, the power supply (with a ripple of VRIPPLE) requirement for TPD4S214 to be able to switch the nFET ON is between 3.8 V + VRIPPLE and 5.55 V - VRIPPLE. 11 Layout 11.1 Layout Guidelines * The optimum placement is as close to the connector as possible. - EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. Therefore, the PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Avoid using VIAs between the connecter and an I/O protection pin on TPD4S214. Avoid 90 turns in traces. - Electric fields tend to build up on corners, increasing EMI coupling. Minimize impedance on the path to GND for maximum ESD dissipation. The capacitors on VBUS and VOTG_IN should be placed close to their respective pins on TDP4S214. * * * * * 11.2 Layout Example GND Plane Detail DET USB Connector Copper pour GND VIA: 0.254 mm (10 mil) pad, 0.152 mm (6 mil) drill. Epoxy filled and plated. FLT VOTG_IN A1 Legend VIA to GND Plane EN ID D+ DVBUS D- D+ ID 0.1 mm (4 mil) clearance VIA to copper Pin to GND Top Layer Bottom Layer VIA in SMD Figure 30. TPD4S214 Layout Example Successful dissipation of an ESD event is largely dependent on minimizing the impedance along the designated electrical path to ground. For this reason any TVS, including TPD4S214, needs to have the lowest possible impedance to GND. The BGA footprint of this device constrains the path to ground through a VIA in the GND pad of TPD4S214. Due to the "skin effect," maximizing the surface area of the VIA minimizes the impedance of the path to GND. For this reason make both the VIA pad diameter and the VIA drill diameter as large as possible, thus maximizing the surface area of the outside of the VIA surface and the inside of the VIA surface. The GND plane should not be broken in the vicinity of the GND VIA. If possible, attaching the GND VIA to a GND plane on multiple layers minimizes the impedance. The GND VIA should be filled with a non-conductive filler (like epoxy) as opposed to a conductive filler, in order to keep the surface area of the inside of the VIA created by the drill. The GND VIA should be plated over at the SMD pad. 22 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 TPD4S214 www.ti.com SLVSBR1F - JANUARY 2013 - REVISED JANUARY 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation OTG and EH Supplement: On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, July 14th, 2011. www.usb.org 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: TPD4S214 23 PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2015 PACKAGING INFORMATION Orderable Device Status (1) TPD4S214YFFR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFF 12 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 85 B3214 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2015 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD4S214YFFR Package Package Pins Type Drawing SPQ DSBGA 3000 YFF 12 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 1.48 B0 (mm) K0 (mm) P1 (mm) 1.78 0.69 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD4S214YFFR DSBGA YFF 12 3000 182.0 182.0 20.0 Pack Materials-Page 2 PACKAGE OUTLINE YFF0012 DSBGA - 0.625 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.625 MAX C SEATING PLANE BALL TYP 0.30 0.12 0.05 C 0.8 TYP 0.4 TYP D SYMM C 1.2 TYP B D: Max = 1.72 mm, Min = 1.66 mm E: Max = 1.42 mm, Min = 1.36 mm A 12X 0.015 0.3 0.2 C A 1 2 3 0.4 TYP SYMM B 4222191/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YFF0012 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 12X ( 0.23) 1 2 3 A (0.4) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE SCALE:30X 0.05 MAX ( 0.23) METAL METAL UNDER SOLDER MASK 0.05 MIN ( 0.23) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222191/A 07/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YFF0012 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 12X ( 0.25) (R0.05) TYP 1 2 3 A (0.4) TYP B SYMM METAL TYP C D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X 4222191/A 07/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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