MMA3204EG - Freescale Semiconductor

MMA3204KEG

Rev 0, 11/2009

Freescale Semiconductor

Technical Data

Surface Mount

Micromachined Accelerometer

The MMA3204 series of dual axis (X and Y) silicon capacitive,

micromachined accelerometers features signal conditioning, a 4-pol e low

pass filter and temperature compensation and separate outputs for the two

axes. Zero-g offset full scale span and filter cut-off are factory set and require

no external devices. A full system self-test capability verifies system

functionality.

Features

• Sensitivity in two separate axes: 100g X-axis and 30g Y-axis

• Integral Signal Conditioning

• Linear Output

• Ratiometric Performance

• 4th Order Bessel Filter Preserves Pulse Shape Integrity

• Calibrated Self-test

• Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status

• Transducer Hermetically Sealed at Wafer Level for Superior Reliability

• Robust Design, High Shocks Survivability

• Qualified AEC-Q100, Rev. F Grade 2 (-40°C/ +105°C)

Typical Applications

• Vibration Monitoring and Recording

• Impact Monitoring

• Appliance Control

• Mechanical Bearing Monitoring

• Computer Hard Drive Protection

• Computer Mouse and Joysti cks

• Virtual Reality Input Devices

• Sports Diagnostic Devices and Systems

ORDERING INFORMATION

Device Temperature Range Case No. Package

MMA3204EG –40 to +125°C 475A-02 SOIC-20

MMA3204EGR2 –40 to +125°C 475A-02 SOIC-20, Tape & Reel

MMA3204KEG* –40 to +125°C 475A-02 SOIC-20

MMA3204KEGR2* –40 to +125°C 475A-02 SOIC-20, Tape & Reel

*Part number sourced from a different facility.

MMA3204KEG

KEG SUFFIX (Pb-FREE)

20-LEAD SOIC

CASE 475A-02

MMA3204KEG: XY-AXIS SENSITIVITY

MICROMACHINED

ACCELEROMETER

±100/30g

Figure 1. Simplified Accelerometer Functional Block Diagram Figure 2. Pin Connections

N/C

XOUT

STATUS

VDD

GND

N/C

AVDD

N/C

YOUT

N/C

VSS

G-Cell

Sensor Integrator Gain Filter Temp

Self-Test Control Logic &

EPROM

Trim Circuits Clock

Gen.

Oscillator

VDD

XOUT

VSS

Status

AVDD

YOUT

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2Freescale Semiconductor

Table 1. Maximum Ratings

(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)

NOTES:

1. Dropped onto concrete surface from any ax is.

ELECTRO STATIC DISCHARGE (ESD)

WARNING: This device is sensitive to electrostatic

discharge.

Although the Freescale accele rometers contain internal

2kV ESD protection circuitry, extra precaution must be taken

by the user to protect the chip from ESD. A charge of over

2000 volts can accumulate on the human body or associated

test equipment. A charge of this magnitude can alter the

performance or cause failure of the chip. When handling the

accelerometer, proper ESD precautions should be followed

to avoid exposing the device to discharges which may be

detrimental to its performance.

Rating Symbol Value Unit

Powered Acceleration (all axes) Gpd 1500 g

Unpowered Acceleration (all axes) Gupd 2000 g

Supply Voltage VDD –0.3 to +7.0 V

Drop Test (1) Ddrop 1.2 m

Storage Temperature Range Tstg –40 to +125 °C

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Table 2. Operating Characteristics

(Unless otherwise noted: –40°C ≤ TA ≤ +105°C, 4.75 ≤ VDD ≤ 5.25, Acceleration = 0g, Load ed output.(1))

NOTES:

1. For a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 μF capac itor to ground.

2. These limits define the range of operation for which the part will meet specification.

3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits

the device may operate as a linear device but is not guaranteed to be in calibration.

4. The device can measure both + and – acceleration. With no input acceleration the output is at mid-supply. For positive acceleration the

output will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.

5. The device is calibrated at 20g.

6. At clock frequency ≅70 kHz.

7. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages.

8. Time for the output to reach 90% of its final value after a self-test is initiated.

9. Time for amplifiers to recover after an acceleration signal causing them to saturate.

10. Preserves phase margin (60°) to guarantee output amplifier stability.

11. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity.

12. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is

high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application.

13. The S tatus pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The

Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 μs, unless a fault condition continues to exist.

Characteristic Symbol Min Typ Max Unit

Operating Range (2)

Supply Voltage (3)

Supply Current

Operating Temperature Range

Acceleration Range X-axis

Acceleration Range Y-axis

VDD

IDD

gFS

4.75

–40

—

5.00

—

112.5

33.75

5.25

+125

—

°C

Output Signal

Zero g X-axis (TA = 25°C, VDD = 5.0 V)(4)

Zero g Y-axis (TA = 25°C, VDD = 5.0 V)(4)

Zero g X-axis

Zero g Y-axis

Sensitivity X-axis (TA = 25°C, VDD = 5.0 V)(5)

Sensitivity Y-axis (TA = 25°C, VDD = 5.0 V)(5)

Sensitivity X-axis

Sensitivity Y-axis

Bandwidth Response

Nonlinearity

VOFF

VOFF,V

f–3dB

NLOUT

2.35

2.25

0.46 VDD

0.44 VDD

63.33

3.72

12.40

360

–1.0

2.5

0.50 VDD

66.67

13.33

400

—

2.65

2.75

0.54 VDD

0.56 VDD

70.0

4.28

14.27

440

+1.0

mV/g

mV/g/V

% FSO

Noise

RMS (.01 Hz – 1 kHz)

Power Spectral Density

Clock Noise (without RC load on output)(6)

nRMS

nPSD

nCLK

—

110

2.0

3.5

—

mVrms

μV/(Hz1/2)

mVpk

Self-Test

Output Response

Input Low

Input High

Input Loading(7)

Response Time(8)

gST

VIL

VIH

IIN

tST

9.6

VSS

0.7 × VDD

–30

—

–100

2.0

14.4

0.3 × VDD

VDD

–300

–

μA

Status(12)(13)

Output Low (Iload = 100 μA)

Output High (Iload = 100 μA) VOL

VOH

—

VDD –0.8 —

—0.4

—V

Minimum Supply Voltage (LVD Trip) VLVD 2.7 3.25 4.0 V

Clock Monitor Fail Detection Frequency fmin 50 —260 kHz

Output Stage Performance

Electrical Saturation Recovery Time(9)

Full Scale Output Range (IOUT = 200 μA)

Capacitive Load Drive(10)

Output Impedance

tDELAY

VFSO

—

0.25

—

0.2

—

300

—

VDD–0.25

100

—

Mechanical Characteristics

Transverse Sensitivity(11)

Package Resonance VXZ,YZ

fPKG —

——

10 5.0

—% FSO

kHz

MMA3204KEG

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4Freescale Semiconductor

PRINCIPLE OF OPERATION

The Freescal e accelerometer is a surf ace-micromachined

integrated-circuit accelerometer.

The device consists of a surface micromachined

capacitive sensing cell (g-cell) and a CMOS signal

conditioning ASIC contained in a single integrated circuit

package. The sensing element is sealed hermetically at the

wafer level using a bulk micromachined “cap'' wafer.

The g-cell is a mechanical structure formed from

semiconductor materials (polysilicon) using semiconductor

processes (masking and etching). It can be modeled as a set

of beams attached to a movable central mass that move

between fixed beams. The movable beams can be deflected

from their rest position by subjecting the system to an

acceleration (Figure 2).

As the beams attached to the central mass move, the

distance from them to the fixed beams on one side will

increase by the same amount that the distance to the fixed

beams on the other side decreases. The change in distance

is a measure of acceleration.

The g-cell beams form two back-to-back capacitors

(Figure 2). As the central mass moves with acceleration, the

distance between the beams change and each capacitor's

value will change, (C = NAε/D). Where A is the area of the

facing side of the beam, ε is the dielectric constant, D is the

distance between the beams, and N is the number of beams.

The X-Y device contains two structures at right angles to

each othe r.

The CMOS ASIC uses switched capacitor techniques to

measure the g - cel l capacitors and extract the accele ra ti on

data from the difference between the two capacitors. The

ASIC also signal conditio ns and filters (switched capacitor)

the signal, providing a high level output voltage that is

ratiometric and proportional to acceleratio n.

Figure 2. Simplified Tr ansducer Physical Model

SPECIAL FEATURES

Filtering

The Freescale accelerometers contain an onboard 4-pole

switched capacitor filter. A Bessel implementation is used

because it provides a maximally flat delay response (linear

phase) thus preserving pulse shape integrity. Because the

filter is realized using switched capacitor techniques, there is

no requirement for external passive components (resistors

and capacitors) to set the cut-off frequency.

Self-Test

The sensor provides a self-test feature that allows the

verification of the mechanical and electrical integrity of th e

accelerometer at any time before or after installation. This

feature is critical in applications such as automotive airbag

systems where system integrity must be ensured over the life

of the vehicle. A fourth “plate'' is used in the g-cell as a self-

test plate. When the user applies a logic high input to the self-

test pin, a calibrated potenti al is applied across the self-test

plate and the moveabl e plate. The resulting electrostatic

force (Fe = 1/2AV2/d2) causes the center plate to deflect. The

resultant deflection is measured by the accelerometer's

control ASIC and a proportional outp ut voltage results. This

procedure assures that both the mechanical (g-cell) and

electronic sections of the accelerometer are fu nctioning.

Ratiometricity

Ratiometricity simply means that the output offset voltage

and sensitivity will scale linearly with applied supply voltage.

That is, as you increase supply voltage the sensitivity and

offset increase linearly; as supply voltage decreases, offset

and sensitivity decrease linearly. This is a key feature when

interfacing to a microcontroller or an A/D converter because

it provides system level cancellation of supply induced errors

in the analog to digital conversion process.

Status

Freescale accelerometers include fault detection circuitry

and a fault latch. The Status pin is an ou tput from the fault

latch, OR'd with self-test, and is set high whenever one (or

more) of the following events occur:

• Supply voltage falls below the Low Voltage

Detect (LVD) voltage threshold

• Clock oscillator falls below the clock monitor

minimum freq ue n c y

• Parity of the EPROM bit s becomes odd in

number.

The fault latch can be reset by a rising edge on the self-test

input pin, unless one (or more) of the fault conditions

continues to exist.

Acceleration

MMA3204KEG

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Freescale Semiconductor 5

BASIC CONNECTIONS

Pinout Description

Figure 3. SOIC Accelerometer with Recommended

Connection Diagram

PCB Layout

Figure 4. Recommended PCB Layout for Interfacing

Accelerometer to Microcontroller

NOTES:

• Use a 0.1 μF capacitor on VDD to decouple the power

source.

• Physical coupling distance of the accelerometer to the

microcontro l l er shou l d be mini ma l .

• Place a ground plane beneath the accelerometer to

reduce noise, the ground plane should be attached to all

of the open ended termi nals shown in Figure 4.

• Use an RC filter of 1 kΩ and 0.01 μF on the output of the

accelerometer to minimize clock noise (from the switched

capacitor filter circuit).

• PCB layout of power and ground should not couple power

supply noise.

• Accelerometer and microcontroller should not be a high

current path.

• A/D sampling rate and any external power supply

switching frequency should be selected such that they do

not interfere with the internal accelerometer sampling

frequency. This will prevent aliasing errors.

Pin No. Pin Name Description

1 thru 3 — Leave unconnected.

4 — No internal connection. Leave

unconnected.

5 ST Logic input pin used to initiate

self-test.

OUT Output voltage of the

accelerometer. X Direction.

7 STATUS Logic output pin to indicate

fault.

SS The power supply ground.

DD The power supply input.

10 AVDD Power supply input (Analog).

11 YOUT Output voltage of the

accelerometer. Y Direction.

12 thru 16 — Used for factory trim. Leave

unconnected.

17 thru 19 — No internal connection. Leave

unconnected.

20 GND Ground.

N/C

XOUT

STATUS

VDD

GND

N/C

VSS

AVDD

N/C

YOUT

N/C

XOUT

YOUT

MMA3204KEG

VDD

VSS

1 kΩ

0.01 μF

Logic

Input

VDD

0.1 μF

0.01 μF

1 kΩ

AVDD

Status

X Output

Signal

Y Output

Signal

A/D In

VRH

VSS

VDD

YOUT

VSS

VDD

0.01 μF

1 kΩ

0.1 μF

Power Supply

0.1 μF

STATUS

A/D In

XOUT R0.01 μF

1 kΩ

Microcontroller

Accelerometer

MMA3204KEG

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6Freescale Semiconductor

−X

N/C

XOUT

STATUS

VDD

GND

N/C

VSS

AVDD

N/C

YOUT

N/C

Direction of Earth’s gravity field.*

* When positioned as shown, the Earth’s gravity will result in a positive 1g output in the X channel.

Front View Side View

Top View

Static Acceleration Sensing Direction

Dynamic Acceleration Sensing Direction

Acceleration of the

package in the +X and

+Y direction (center plates

move in the −X and −Y

direction) will result in an

increase in the X and Y

outputs.

20-Pin SOIC Package

N/C pins are recommended to be left FLOATING

−Y

11 12 13 14 15 16 17 18 19 20

10 9 8 7 6 5 4 3 2 1

Activation of Self test moves

the center plates in the −X

and −Y direction, resulting in

an increase in the X and Y

outputs.

MMA3204KEG

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Freescale Semiconductor 7

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the surface mount packages must be

the correct size to ensure proper solder connection interface

between the board and the package. With the correct

footprint, the packages will self-align when subjected to a

solder reflow process. It is always recommended to design

boards with a solder mask layer to avoid bridgi ng and

shorting between solder pads.

Figure 5. Footprint SOIC-20 (Case 475A -02)

0.380 in.

9.65 mm

0.050 in.

1.27 mm

0.024 in.

0.610 mm

0.080 in.

2.03 mm

PACKAGE DIMENSIONS

PAGE 1 OF 2

CASE 475A-02

ISSUE C

20-LEAD SOIC

MMA3204KEG

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PACKAGE DIMENSIONS

CASE 475A-0 2

ISSUE C

20-LEAD SOIC

PAGE 2 OF 2

Sensors

Freescale Semiconductor 9

MMA3204D

MMA3204KEG

Rev. 0

11/2009

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