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P/N:PM0858 REV. 0.4, JUN. 07, 2002
MX28F320J3/640J3/128J3
32M/64M/128M [x8/x16] SINGLE 3V PAGE MODE FLASH MEMORY
ADVANCED INFORMATION
FEATURES
• 2.7V to 3.6V operation voltage
• Block Structure
- 32 x 128Kbyte Erase Blocks (32M)
- 64 x 128Kbyte Erase Blocks (64M)
- 128 x 128Kbyte Erase Blocks (128M)
• F ast random / page mode access time
- 120/25 ns Read Access Time (32M)
- 120/25 ns Read Access Time (64M)
- 150/25 ns Read Access Time (128M)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 32-Byte Write Buffer
- 6 us/byte Effectiv e Prog ramming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
Performance
• Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
- Deep power-down current: 5uA
• High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using W rite to
Buffer Command)
• Program/Erase Endurance cycles:
five grades-- "C1" stands for 10 cycles
"C2" stands for 100 cycles
"C3" stands for 1,000 cycles
"C4" stands for 10,000 cycles
"C5" stands for 100,000 cycles
(please refer to Ordering Information of page 47)
Software Feature
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Automation Suspend Options
- Block Erase Suspend to Read
- Block Erase Suspend to Program
- Program Suspend to Read
Hardware Feature(Not for 48-TSOP/48-RTSOP)
• A0 pin
- Select low byte address when device is in byte mode.
Not used in word mode.
• STS pin
- Indicates the status of the internal state machine.
• VPEN pin
- For Erase /Program/ Block Lock enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
Packaging
- 48-Lead TSOP (for MX28F128J3)
- 48-Lead RTSOP (for MX28F128J3)
- 56-Lead TSOP
- 48-ball Flip Chip CSP (for MX28F320J3/640J3)
- 64-ball CSP
Technology
- MX28F128J3 using Nbit (0.25u) Flash T echnology
- MX28F320J3/640J3 using Nbit (0.35u) Flash Tech-
nology
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P/N:PM0858 REV. 0.4, JUN. 07, 2002
MX28F320J3/640J3/128J3
GENERAL DESCRIPTION
The MXIC's MX28F320J3/640J3/128J3 series Flash use
the most advance 2 bits/cell Nbit technology, double the
storage capacity of memory cell. The device provide the
high density Flash memory solution with reliable perfor-
mance and most cost-effective.
The device organized as by 8 bits or by 16 bits of output
bus. The device is packaged in 48-Lead TSOP, 48-Lead
RTSOP, 56-Lead TSOP, 48-ball Flip Chip CSP and 64-
ball CSP. It is designed to be reprogrammed and erased
in system or in standard EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
To eliminate bus contention, the device has separate chip
enable (CE0, CE1, CE2) and output enable (OE) con-
trols. The de vice augment EPROM functionality with in-
circuit electrical erasure and programming. The device
uses a command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO la yer .
The de vice uses a 2.7V to 3.6V VCC supply to perf orm
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
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P/N:PM0858 REV. 0.4, JUN. 07, 2002
MX28F320J3/640J3/128J3
PIN CONFIGURATION
48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only)
48-RTSOP (12mm x 20mm) (for MX28F128J3 word mode only)
WE
A17
A16
A15
A14
A13
A12
A11
A10
A9
A20
A22
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
A23
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
RESET(*)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F128J3 (x16 only)
Normal Type
(* RESET pin : high enable)
WE
A17
A16
A15
A14
A13
A12
A11
A10
A9
A20
A22
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
A23
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
RESET(*)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F128J3 (x16 only)
Rev erse Type
(* RESET pin : high enable)
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MX28F320J3/640J3/128J3
48 Flip Chip CSP (for MX28F320J3/640J3)
A14
A
B
C
D
E
F
1 2345678
A15
A16
A17
VCCQ
GND
A12
A11
A13
Q14
Q15
Q7
A9
WE
A10
Q5
Q6
Q13
VPEN
RESET
A22
Q11
Q12
Q4
8mm
VCC
A19
A21
Q2
Q3
VCC
A20 A8
A18
A7
Q8
Q9
Q10
A6
A4
CEO
Q0
Q1
A5
A3
A2
13 mm
A1
GND
OE
56 TSOP (14mm x 20mm)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RESET
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
WE
OE
STS
Q15
Q7
Q14
Q6
GND
Q13
Q5
Q12
Q4
VCCQ
GND
Q11
Q3
Q10
Q2
VCC
Q9
Q1
Q8
Q0
A0
BYTE
A23
CE2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Notes:
1. A22 exists on 64M, 128M densities. On 32M densities this pin is a no connect (NC).
2. A23 exists on 128M densities. On 32M and 64M densities this pin is a no connect (NC).
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MX28F320J3/640J3/128J3
SYMBOL PIN NAME
A0 Byte Select Address
A1~A23 Address Input (32M:A0~A21,
64M:A0~A22, 128M:A0~A23)
Q0~Q15 Data Inputs/Outputs
CE0, CE1, CE2 Chip Enable Input
WE Write Enable Input
OE Output Enable Input
RESET Reset/Deep Power Down mode
(low enable for 56-TSOP & 64-CSP)
RESET Reset/Deep Power Down mode
(high enable for 48-TSOP &
48-RTSOP)
PIN DESCRIPTION
64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch)
Notes:
1. Address A22 is only valid on 64M and 128M densities. Otherwise, it is a no connect (NC).
2. Address A23 is only valid on 128M densities. Otherwise, it is a no connect (NC).
3. Don't Use (DU) pins refer to pins that should not be connected.
A1
A
B
C
D
E
F
G
H
1 2345678
A2
A3
A4
Q8
BYTE
A6
GND
A7
A5
Q1
Q0
A8
A9
A10
A11
Q9
Q10
VPEN
CE0
A12
RESET
Q3
Q11
10mm
A13
A14
A15
DU
Q4
Q12
VCC A18
DU
DU
DU
DU
DU
A19
A20
A16
Q15
DU
A22
CE1
A21
13 mm
A17
STS
OE
A23
CE2
A0
DU
Q2
VCC
VCCQ
GND
Q5
Q13
Q6
GND
Q14
Q7
WE
NC
SYMBOL PIN NAME
STS STATUS Pin
BYTE Byte Mode Enable
VPEN ERASE/PROGRAM/BLOCK Lock
Enable
VCCQ Output Buffer P ower Supply
VCC Device P ower Supply
GND Device Ground
N C Pin Not Connected Internally
D U Don't Use
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MX28F320J3/640J3/128J3
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTA GE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15
A0-A23
CE0
CE1
CE2
OE
WE
RESET(*)
* : RESET pin for 56-TSOP & 64-CSP; RESET pin f or 48-TSOP & 48-R TSOP.
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MX28F320J3/640J3/128J3
Figure 1. Block Architecture
Flash memory reads erases and writes in-system via the local CPU. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Table 1. Chip Enable Truth Table
CE2 CE1 CE0 DEVICE
VIL VIL VIL Enabled
VIL VIL VIH Disabled
VIL VIH VIL Disabled
VIL VIH VIH Disabled
VIH VIL VIL Enabled
VIH VIL VIH Enabled
VIH VIH VIL Enabled
VIH VIH VIH Disabled
NO TE: F or Single-chip applications, CE2 and CE1 can
be strapped to GND .
32 Mbit
01FFFF
010000
00FFFF
000000
64-Kword Block
.
.
.
1
1FFFFF
1F0000 64-Kword Block 31
.
.
.
3FFFFF
3F0000 64-Kword Block 63
64-Kword Block
Word Mode (x16)
03FFFF
020000
01FFFF
000000
.
.
.
3FFFFF
3E0000
.
.
.
7FFFFF
A[23-0]: 128Mbit
A[22-0]: 64Mbit
A[21-0]: 32Mbit
A[23-1]: 128Mbit
A[22-1]: 64Mbit
A[21-1]: 32Mbit
7E0000
FFFFFF
FE0000
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
Byte Mode (x8)
0
1
31
63
.
.
.
7FFFFF
7F0000 64-Kword Block
.
.
.
128-Kbyte Block 127 127
0
64 Mbit
128 Mbit
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MX28F320J3/640J3/128J3
NOTES:
1. See Ta ble 1 on page 7 f or valid CE configurations .
2. OE and WE should ne ver be enab led simultaneously.
3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high.
4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered.
5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH f or VPEN . See DC Characteristics for
VPENLK and VPENH voltages.
6. In default mode, STS is V OL when the WSM is e xecuting internal bloc k erase, progr am, or lock-bit configur ation
algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive),
program suspend mode, or reset/deep power-down mode.
7. High Z will be VOH with an external pull-up resistor .
8. See Section , "Read Identifier Codes" for read identifier code data.
9 . See Section , "Read Query Mode Command" for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=
VPENH and VCC is within specification.
11 .Ref er to Table 3 on page 10 f or valid DIN during a write operation.
12 .RESET mode of 48-TSOP & 48-RTSOP types is high enabled to entering deep power down mode.
Table 2. Bus Operations
Command Read Output Standby RESET Read ID Read Read Read Write
Sequence Array Disable Mode/ Query Status Status
Deep (WSM off) (WSM on)
Power
Down
Mode
Notes 4,5,6 6,10,11
RESET (12) VIH VIH VIH VIL VIH VIH VIH VIH VIH
(12)
CE0,CE1,CE2(1) Enabled Enabled Disabled X Enabled Enabled Enabled Enabled Enabled
OE (2) VIL VIH X X VIL VIL VIL VIL VIH
WE (2) VIH VIH X X VIH VIH VIH VIH VIL
Address X X X X See See X X X
Figure 2 T able 6
VPEN X X X X X X X X VPENH
Q (3) Data out High Z High Z High Z Note 8 Note 9 Data out Q7=Data out Data in
Q15-8=High Z
Q6-0=High Z
STS High Z X X High Z High Z High Z X
(default mode) (7) (7) (7) (7)
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MX28F320J3/640J3/128J3
FUNCTION
The device includes on-chip program/erase control cir-
cuitr y. The Write State Machine (WSM) controls block
erase and byte/word/page program operations. Opera-
tional modes are selected by the commands written to
the Command User Interface (CUI). The Status Register
indicates the status of the WSM and when the WSM
successfully completes the desired program or block
erase operation.
A Deep P ow erdown mode is enabled when the RESET
pin of 56-TSOP & 64-CSP types is at GND or RESET
pin of 48-TSOP & 48-RTSOP is at VIH, minimizing power
consumption.
READ
The device has three read modes, which accesses to
the memory array, the Device Identifier or the Status
Register independent of the VPEN voltage . The appro-
priate read command are required to be written to the
CUI. Upon initial device powerup or after exit from deep
powerdown, the device automatically resets to read ar-
ray mode. In the read array mode, low level input to CE0,
CE1, CE2 and OE, high level input to WE and RESET or
low level input to RESET, and address signals to the
address inputs (A23-A0) output the data of the addressed
location to the data input/output (Q15~Q0).
When reading information in read array mode, the de-
vice defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer. A2:0 addresses data in the page buffer. The page
size is 4 words or 8 bytes. Asynchronous word/byte mode
is supported with no additional commands required.
WRITE
Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register and when VPEN=VPENH block erasure pro-
gram and lock-bit configuration. The CUI is written when
the device is enable, WE is active and OE is at high
level. Address and data are latched on the earlier rising
edge of WE and CE. Standard micro-processor write tim-
ings are used.
OUTPUT DISABLE
When OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
STANDBY
When CE0, CE1 and CE2 disable the device (see table1)
and place it in standby mode. The power consumption of
this device is reduced. Data input/output are in a high-
impedance(High-Z) state. If the memory is deselected
during block erase, program or lock-bit configuration, the
internal control circuits remain active and the device con-
sume normal active power until the operation completes.
DEEP POWER-DOWN
When RESET pin of 56-TSOP & 64-CSP types is at VIL
or RESET pin of 48-TSOP & 48-RTSOP types is at VIH,
the device is in the deep power-down mode and its power
consumption is substantially low around 5uA. During read
modes, the memory is deselected and the data input/
output are in a high-impedance(High-Z) state. To return
from deep power down mode requires RESET pin of 56-
TSOP & 64-CSP types at VIH or RESET pin of 48-
RTSOP & 48-RTSOP types at VIL. After return from
powerdown, the CUI is reset to Read Array , and the
Status Register is set to value 80H.
During block erase program or lock-bit configuration
modes, RESET pin of 56-TSOP & 64-CSP types at VIL
or RESET pin of 48-TSOP & 48-RTSOP types at VIH
will abort either operation. Memory array data of the block
being altered become invalid.
In default mode, STS transitions low and remains low
for a maximum time of tPLPH+tPHRH until the reset
operation is complete. Memory contents being altered
are no longer v alid; the data ma y be partially corrupted
after a program or partially altered after an erase or lock-
bit configuration. Time tPHWL is required after RESET
goes to logic-high (VIH) or RESET goes to VIL before
another command can be written.
READ QUERY
The read query operation outputs block status informa-
tion, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.
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MX28F320J3/640J3/128J3
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid
register command sequences.
When VPEN<VPENLK only read operations from the status register, query, indentifier code or b loc ks are enab led.
When VPEN=VPENH enables block erase program and lock-bit configuration operations.
Table 3. Command Definitions
Command Read Read Read Read Clear Write to W ord/byte Sector
Sequence Array ID Query Status Status Buffer Program Erase
Register Register
Notes 5 6 7,8,9 10,11 9,10
Bus Write Cycles Req'd 1 > 2 > 2 2 1 > 2 2 2
First Bus Operation(2) Write Write Write Write Write Write Write Write
Write Cycles Address(3) X X X X X BA X BA
Data(4,5) FFH 90H 98H 70H 50H E8H 40H/10H 20H
Second Bus Operation(2) Read Read Read Write Write Write
Read Query Address(3) IA QA X BA P A BA
Data(4,5) ID QD SRD N PD D0H
Command Sector Sector Configur- Set Sector Clear Protection
Sequence Erase, Erase, ation Lock-Bit Sector Program
Program Program Lock-Bit
Suspend Resume
Notes 10,12 10 13
Bus Write Cycles Req'd 1 1 2 2 2 2
First Bus Operation(2) Write Write Write Write Write Write
Write Cycle Address(3) X X X X X X
Data(4,5) B0H D0H B8H 60H 60H C0H
Second Bus Operation(2) Write Write Write Write
Write Cycle Address(3) X BA X PA
Data(4,5) CC 01H D0H PD
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MX28F320J3/640J3/128J3
NOTES:
1 . Bus operations are defined in Table 2.
2. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 2 and Tab le 14.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A 16-1 ; all other
address inputs are ignored.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register . See Table 15 f or a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
CC = Configuration Code.
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See Section 4.3 for read identifier code data.
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is av ailable for writing.
8. The n umber of bytes/words to be written to the Write Buffer = N + 1, where N = b yte/word count argument.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH.
The third and consecutive b us cycles , as determined by N, are f or writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence abor ts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional
information.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block.
11 .Either 40H or 10H are recognized by the WSM as the byte/word program setup .
12.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is initiated.
13 .The clear block lock-bits operation simultaneously clears all block lock-bits.
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MX28F320J3/640J3/128J3
Figure 2. Device Identifier Code Memory Map
NOTE: A0 is not used in either x8 or x16 mode when obtaining these identifier codes. Data is always given on the low
byte in x16 mode (upper byte contains 00h).
3FFFFF
3F0003
3F0002
3F0000
3EFFFF
Block 63
Reserved for Future
Implementation
Reserved for Future
Implementation
(Block 32 through 62)
Block 63 Lock Configuration
7FFFFF
Word
Address
A[23-1]:128 Mbit
A[22-1]:64 Mbit
A[21-1]:32 Mbit
7F0003
7F0002
7F0000
7EFFFF
Block 127
Reserved for Future
Implementation
Reserved for Future
Implementation
(Block 64 through 126)
Block 127 Lock Configuration
1F0003
32 Mbit
1F0002
1F0000
1EFFFF
01FFFF
Block 31
Reserved for Future
Implementation
Reserved for Future
Implementation
(Block 2 through 30)
Block 31 Lock Configuration
010003
010002
010000
000003
000002
000001
000000
Block 1
Reserved for Future
Implementation
00FFFF
000004
Block 0
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 1 Lock Configuration
Block 0 Lock Configuration
Device Code
Manufacturer Code
64 Mbit
128 Mbit
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MX28F320J3/640J3/128J3
Read Array Command
The device is in Read Array mode on initial device power
up and after exit from deep power down, or by writing
FFH to the Command User Interface. The read configu-
ration register defaults to asynchronous read page mode.
The device remains enabled for reads until another com-
mand is written. The Read Array command functions in-
dependently of the VPEN voltage.
Read Query Mode Command
This section defines the data structure or "Database"
returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure
to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this informa-
tion has been obtained, the software will know which
command sets to use to enable flash writes, block
erases, and otherwise control the flash component.
Query Structure Output
The Query Database allows system software to gain in-
f ormation for controlling the flash component. This sec-
tion describes the device CFI-compliant interface that
allows the host system to access Query data.
Query data are always presented on the lowest-order
data outputs (DQ 0-7) only. The numerical offset value is
the address relative to the maximum bus width supported
by the device. On this family of devices, the Query table
device starting address is a 10h, which is a word ad-
dress for x16 devices.
For a word-wide (x16) device, the first two bytes of the
Query structure, "Q" and "R" in ASCII, appear on the
low byte at word addresses 10h and 11h. This CFI-com-
pliant device outputs 00H data on upper bytes. Thus, the
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and
00h in the high byte (DQ 8-15 ).
At Query addresses containing two or more bytes of in-
formation, the least significant data byte is presented at
the lower address, and the most significant data byte is
presented at the higher address.
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Word Ad dressing Byte Addressing
Offset Hex Code V alue Offset Hex Code V alue
A15-A0 D15 - D0 A7-A0 D7 - D0
0010h 0051 "Q" 20h 51 "Q"
0011h 0052 "R" 21h 51 "Q"
0012h 0059 "Y" 22h 52 "R"
0013h P_IDLO PrVendor 23h 52 "R"
0014h P_IDHI ID# 24h 59 "Y"
0015h PLO PrVendor 25h 59 "Y"
0016h PHI TblAdr 26h P_IDLO PrVendor
0017h A_IDLO AltVendor 27h P_IDLO ID#
0018h A_IDHI ID# 28h P_IDHI ID#
... ... ... ... ... ...
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped. In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.
Device Query start location in Query data with maximum Query data with byte
Type/Mode maximum device bus device bus width addressing addressing
width addresses Hex Hex ASCII Hex Hex ASCII
Offset Code Value Offset Code Value
x16 device 1 0 : 0051 "Q" 20: 51 "Q"
x16 mode 10h 11: 0052 "R" 21: 00 "Null"
12: 0059 "Y" 22: 52 "R"
x16 device 20 : 5 1 "Q"
x8 mode N/A (1) N/A (1) 21: 5 1 "Q"
22: 52 "R"
Table 4. Summary of Quer y Structure Output as a Function of Device and Mode
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device
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Offset Sub-Section Name Description
00h Manufacturer Code
01h Device Code
(BA+2)h (2) Block Status Register Block-Specific Information
04-0Fh Reserved
Reserved for Vendor-Specific Information
1 0h CFI Query Identification String
Reserved for Vendor-Specific Information
1B h System Interface Information Command Set ID and V endor Data Offset
27h Device Geometry Definition Flash Device Layout
P
(3) Primary MXIC-Specific Extended V endor-Defined Additional Information Specific to the
Query Table Primary Vendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128
Kbyte).
3. Offset 15 defines "P" which points to the
Primary Intel-Specific Extended Query
Table.
Table 6. Query Structure (1)
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is
locked or can be accessed for flash program/erase operations.
Offset Length Description Address Value
(BA+2)h (1) 1 Block Lock Status Register BA+2: --00 or --01
BSR.0 Block Lock Status
0 = Unlocked BA+2: (bit 0): 0 or 1
1 = Locked
BSR 1-7:
Reserved for Future Use
BA+2: (bit 1-7): 0
NOTE:
1 . BA = The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word
mode).
Table 7. Block Status Register
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or
"database". The structure sub-sections and address locations are summarized below .
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Offset Length Description Add. Hex Value
Code
10h 3 Query-unique ASCII string "QR Y" 1 0 --51 "Q"
11: --52 "R"
12: --59 "Y"
1 3h 2 Primary vendor command set and control interface ID code. 13 : --01
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query T able primary algorithm address 1 5: --31
16: --00
1 7h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query T able address. 19: --00
0000h means none exists 1A: --00
Table 8. CFI Identification
Offset Length Description Add. Hex Value
Code
1Bh 1 VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV 1B: --27 2.7 V
bits 4-7 BCD volts
1 Ch 1 VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV 1C : --36 3.6 V
bits 4-7 BCD volts
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV 1D : --00 0.0V
bits 4-7 HEX volts
1Eh 1 VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV 1E: --00 0.0V
bits 4-7 HEX volts
1 F h 1 "n" such that typical single word program time-out = 2us 1F: --07 128us
20 h 1 "n" such that typical max. buffer write time-out = 2us 20 : --07 128us
21h 1 "n" such that typical block erase time-out = 2ms 21: --0A 1s
22h 1 "n" such that typical full chip erase time-out = 2ms 22: --00 NA
2 3h 1 "n" such that maximum word program time-out = 2 times typical 2 3: --04 2ms
24 h 1 "n" such that maximum buffer write time-out = 2 times typical 2 4: --04 2ms
25 h 1 "n" such that maximum block erase time-out = 2 times typical 25: --04 16s
26 h 1 "n" such that maximum chip erase time-out = 2 times typical 26: --00 NA
System Interface Information
The following device information can optimize system interface software.
Table 9. System Interface Information
CFI Query Identification String
The CFI Query Identification String provides v erification that the component supports the Common Flash Interface
specification. It also indicates the specification v ersion and supported vendor-specified command set(s).
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Address 32M 64M 128M
27: --16 --17 --18
28: --02 --02 --02
29: --00 --00 --00
2A: --05 --05 --05
2B: --00 --00 --00
2C: --01 --01 --01
2D : --1F --3F --7F
2E: --00 --00 --00
2F: --00 --00 --00
30: --02 --02 --02
Device Geometry Definition
This field provides critical details of the flash device geometry.
Offset Length Description Code See Table
Below
27h 1 "n" such that device size = 2n in number of bytes 27:
28h 2 Flash device interface: x8 async(28:00,29:00), 28: --02 x8/x16
x16 async(28:01,29:00), x8/x16 async(28:02,29:00) 29: --00
2Ah 2 "n" such that maximum number of bytes in write buffer = 2n2A: --05 32
2B: --00
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in "bulk"
2. x specifies the n umber of device or partition regions with one or
2 Ch 1 more contiguous same-size erase blocks 2C: --01 1
3. Symmetrically b lock ed partitions hav e one bloc king region
4. Partition size = (total blocks) x (individual block size)
2 Dh 4 Erase Block Region 1 Information 2D :
bits 0-15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16-31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
Table 10. Device Geometry Definition
Device Geometry Definition
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Offset(1) Length Description Add. Hex Value
P=31h (Optional Flash Features and Commands) Code
(P+0)h 3 Primary extended query table 31: --50 "P"
(P+1)h Unique ASCII string "PRI" 32 : --52 "R"
(P+2)h 33: --49 "I"
(P+3)h 1 Major version number, ASCII 34: --31 "1"
(P+4)h 1 Minor version number, ASCII 35: --31 "1"
(P+5)h Optional feature and command support (1=yes, 0=no) 36: --0A
(P+6)h bits 9-31 are reserved; undefined bits are "0". If bit 31 is 37 : --00
(P+7)h "1" then another 31 bit field of optional features follows at 38 : --00
(P+8)h the end of the bit-30 field. 39 : --00
bit 0 Chip erase supported bit 0 = 0 No
4 bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 1(1) Yes(1)
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant Individual block locking suppor ted bit 5 = 0 No
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Page-mode read supported bit 7 = 1 Yes
bit 8 Synchronous read suppor ted bit 8 = 0 No
(P+9)h 1 Supported functions after suspend: read Array, Status,Query
Other supported operations are: 3A: --01
bits 1-7 reserved; undefined bits are "0"
bit 0 Program suppor ted after erase suspend bit 0 = 1 Yes
(P+A)h Block status register mask 3B: --01
(P+B)h 2 bits 2-15 are Reserved; undefined bits are "0" 3C: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 0 No
(P+C)h 1 VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV 3 D: --33 3.3V
bits 4-7 BCD value in volts
(P+D)h 1 VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV 3E: --00 0.0V
bits 4-7 HEX value in volts
Primary-Vendor Specific Extended Quer y Table
Certain flash features and commands are optional. The
Primary V endor-Specific Extended Query
table specifies this
and other similar information.
NOTE:
1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0".
Table 11. Primary Vendor-Specific Extended Query
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Offset(1) Length Description Add. Hex Value
P=31h (Optional Flash Features and Commands) Code
(P+E)h 1 Number of Protection register fields in JEDEC ID space. 3F: --01 01
"00h," indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) protection register bytes. Some are pre-programmed
(P+F)h with device-unique serial numbers. Others are user-programmable.
(P+10)h Bits 0-15 point to the protection register lock 40 : --00 00h
(P+11)h byte, the section's first byte. The following bytes are factory
(P+12)h pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = "n" such that 2 n = factory pre-programmed bytes
bits 24-31 = "n" such that 2 n = user-programmable bytes
NOTE:
1. The v a riable P is a pointer which is defined at CFI offset 15h.
Table 12. Protection Register Information
Offset(1) Length Description Add. Hex Value
P=31h (Optional Flash Features and Commands) Code
Page Mode Read capability
bits 0-7 = "n" such that 2n HEX value represents the number
(P+13)h 1 of read-page bytes. See offset 28h for device word width to 44: --03 8 byte
determine page-mode data output width. 00h indicates no
read page buffer.
(P+14)h 1 Number of synchronous mode read configuration fields that 45: --00 0
follo w . 00h indicates no b urst capability.
(P+15)h Reserved for future use 46:
NOTE:
1. The v ariable P is a pointer which is defined at CFI offset 15h.
Table 13. Page Read Information
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* Outputs C2H at protected sector address, 00H at unprotected sector address.
** Only the top and the bottom sectors have protect-bit feature. Sector address = (A20, A19, A18,A17,A16) =
00000B or 11111B
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
To activate this mode, the two cycle "Silicon ID Read"
command is requested. (The command sequence is il-
lustrated in Table 14.
During the "Silicon ID Read" Mode, manufacturer's code
(MXIC=C2H) can be read out by setting A0=VIL and
device identifier can be read out by setting A0=VIH.
To terminate the operation, it is necessary to write the
read command. The "Silicon ID Read" command func-
tions independently of the VPEN voltage. This command
is valid only when the WSM is off or the device is sus-
pended.
Table 14. MX28F320J3/640J3/128J3 Silicon ID Codes and V erify Sector Protect Code
T ype Address (1) Code (HEX) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Manufacture Code 00000 C2H 1 1 0 0 0 0 1 0
32M 00001 (00) 72H 0 1 1 1 0 0 1 0
Device Code 64M 00001 (00) 73H 0 1 1 1 0 0 1 1
128M 00001 (00) 74H 0 1 1 1 0 1 0 0
Block Lock Configuration X0002 (2)
- Block is Unlocked DQ0=0
- Block is Locked DQ0=1
- Reserved for Future Use DQ1-7
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High Z Definition
Symbol When Status Notes
Busy? " 1" "0"
SR.7 No WRITE STATE MACHINE STATUS Ready Busy 1
SR.6 Yes ERASE SUSPEND STATUS Block Erase Suspended Block Erase in
Progress/Completed
SR.5 Yes ERASE AND CLEAR LOCK-BITS Error in Block Erasure or Successful Block 2
STATUS Clear Lock-Bits Erase or Clear
Lock-Bits
SR.4 Yes PROGRAM AND SET LOCK-BIT Error in Setting Lock-Bit Successful Set Block
STATUS Lock Bit
SR.3 Y es PROGRAMMING VOLT AGE Low Programming Voltage Programming Voltage 3
STA TUS Detected, Operation OK
Aborted
SR.2 Yes PROGRAM SUSPEND STATUS Program suspended Program in progress/
completed
SR.1 Yes DEVICE PRO TECT ST ATUS Block Lock-Bit Detected, Unlock 4
Operation Abort
SR.0 Yes RESERVED 5
Table 15. Status Register Definitions
Notes
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not
driven while SR.7 = 0
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-
quence was entered.
3 . SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-
mand sequences.
4. SR.1 does not provide a continuous indication of b lock loc k-bit v alues. The WSM interrogates the b lock loc k-bits
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.
5. SR.0 is reserved f or future use and should be masked when polling the status register .
High Z Definition
Symbol When Status Notes
Busy? "1" " 0"
XSR.7 N o WRITE BUFFER STATUS Write buffer available Write buffer not available 1
XSR.6- Yes RESERVED 2
XSR.0
Table 16 . Extended Status Register Definitions
Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is a v ailab le .
2. XSR.6-XSR.0 are reserved f or future use and should be masked when polling the status register .
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BLOCK ERASE COMMAND
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm com-
mand of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled in-
ternally by the WSM (invisib le to the system). The CPU
can detect block erase completion by analyzing the out-
put of the STS pin or status register bit SR.7. Toggle OE,
CE0 , CE1 , or CE2 to update the status register. The
CUI remains in read status register mode until a new
command is issued. Also, reliable block erasure can only
occur when VCC is valid and VPEN = V PENH .
BLOCK ERASE SUSPEND COMMAND
This command only has meaning while the WSM is e x-
ecuting Block erase operation, and therefore will only be
responded to during Block erase operation. After this com-
mand has been e xecuted, the WSM suspend the erase
operations, and then return to Read Status Register
mode. The WSM will set the Q6 bit to a "1". Once the
WSM has reached the Suspend state, the WSM will set
WRITE TO BUFFER COMMAND
To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the
flash device. First, the W r ite to Buffer Setup command
is issued along with the Block Address (see Figure ,
Write to Buffer Flowchart” on page ). After the com-
mand is issued, the extended Status Register (XSR) can
be read when CE is VIL. XSR.7 indicates if the Write
Buffer is available.
If the buffer is available, the number of words/bytes to
be program is written to the device. Next, the start ad-
dress is given along with the write buffer data. Subse-
quent writes provide additional device addresses and
data, depending on the count. After the last buffer data
is given, a Write Confirm command must be issued. The
WSM beginning cop y the buff er data to the flash arra y.
If an error occurs while writing, the device will stop writ-
ing, and status register bit SR.4 will be set to a "1" to
indicate a program f ailure. The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
the Q7 bit to a "1". In default mode, STS will also transi-
tion to V OH.
At this time, A read array/program command sequence
can also be issued during erase suspend to read or pro-
gram data in other blocks. During a program operation
with block erase suspended, status register bit SR.7 will
return to "0" and STS output (in default mode) will transi-
tion to VOL The WSM will continue to r un, idling in the
SUSPEND state, regardless of the state of all input con-
trol pins.
The only other valid commands while block erase is sus-
pended are Read Query, Read Status Register, Clear
Status Register, Configure, and Block Erase Resume.
After a Block Erase Resume command is written to the
flash memory, the WSM will continue the block erase
process. Status register bits SR.6 and SR.7 will auto-
matically clear and STS (in default mode) will return to
VOL. VPEN must remain at VPENH (the same VPEN
level used for block erase) while block erase is suspended.
Block erase cannot resume until program operations ini-
tiated during block erase suspend have completed.
READ STATUS REGISTER COMMAND
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Inter-
face. Also, after star ting the inter nal operation the de-
vice is set to the Read Status Register mode automati-
cally.
The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE0, CE1, CE2
that enables the de vice OE must be toggle to VIH or the
device must be disable before further reads to update
the status register latch. The Read Status Register com-
mand functions independently of the VPEN v oltage.
CLEAR STATUS REGISTER COMMAND
The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Ma-
chine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.
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device will not accept any more Write to Buffer com-
mands. Reliable buffered writes can only occur when VCC
is valid and VPEN = VPENH. Also , successful program-
ming requires that the corresponding block lock-bit be
reset.
BYTE/WORD PROGRAM COMMANDS
Byte/Word program is executed by a two-command se-
quence. The Byte/Word Program Setup command of 40H
is written to the Command Interface, followed by a sec-
ond write specifying the address and data to be written.
The WSM controls the program pulse application and
v erify operation. The CPU can detect the completion of
the program event by analyzing the STS pin or status
register bit SR.7.
If a byte/word program is attempted while VPEN_V
PENLK, status register bits SR.4 and SR.3 will be set to
"1". Successful byte/word programs require that the cor-
responding block lock-bit be cleared. If a byte/ word pro-
gram is attempted when the corresponding block lock-
bit is set, SR.1 and SR.4 will be set to "1".
SUSPEND/RESUME COMMAND
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows
read out from another block of memory . Writing the Sus-
pend command of B0H during program operation inter-
rupts the program operation and allows read out from
another block of memory. The Block address is required
when writing the Suspend/Resume Command. The de-
vice continues to output Status Register data when read,
after the Suspend command is written to it. Polling the
WSM Status and Suspend Status bits will determine when
the erase operation or program operation has been sus-
pended. When SR.7 = 1, SR.2 should also be set to "1",
indicating that the device is in the program suspend mode.
STS in le v el RY/BY mode will also transition to VOH.
At this time, writing of the Read Array command to the
CUI enables reading data from blocks other than that
which is suspended. The only other valid commands while
programming is suspended are Read Query , Read Sta-
tus Register, Clear Status Register, Configure, and Pro-
gr am Resume. When the Resume command of D0H is
written to the CUI, the WSM will continue with the erase
or program processes. Status register bits SR.2 and SR.7
will automatically clear and STS in R Y/BY mode will re-
turn to VOL.
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Read Configuration
The device will support both asynchronous page mode and standard word/byte reads . No configuration is required.
Status register and identifier only support standard word/byte single read operations.
Table 17. Read Configuration Register Definition
RM R R R R R R R
16(A16) 15 14 13 12 11 10 9
RR R R R R R R
87 6 5 4 3 2 1
Notes
RCR.16 = READ MODE (RM) Read mode configuration effects reads from the flash
0 = Standard Word/Byte Reads Enabled (Def ault) arra y .
1 = Page-Mode Reads Enabled Status register, query , and identifier reads support
standard word/byte read cycles.
RCR.15-1= RESERVED FOR FUTURE These bits are reserved for future use. Set these
ENHANCEMENTS (R) bits to "0".
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has
been configured, it remains in that configuration until another configuration command is issued or RP is asserted low .
Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY
high indicates that the state machine is ready for a new operation or suspended. Table 19, "Configuration Coding
Definitions" on page 28 displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired
configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described
below . F or these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete
interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the
default RY/BY level mode. The possible configurations and their usage are descr ibed in Table 19, "Configuration
Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4
and SR.5 being set to "1".” When configured in one of the pulse modes , the STS pin pulses low with a typical pulse
width of 250 ns.
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Q7 - Q2 = Reserved
Q1 - Q0 = STS Pin Configuration Codes
00 = def ault, level mode RY/BY
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high when
the operation indicated by the given configuration is
completed.
Configuration Command Sequences for STS pin
configuration (masking bits Q7- Q 2 to 00h) are as
follows:
Def ault RY/BY le vel mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
Table 18. Configuration Coding Definitions
NOTE: 1. When the de vice is configured in one of the pulse modes , the STS pin pulses low with a typical pulse
width of 250 ns.
Reserved Pulse on Pulse on
Program Erase
Complete (1) Compete (1)
bits7-2 bit 1 bit 0
Q7 - Q2 are reserved for future use.
def ault (Q1-Q 0 = 00) R Y/BY, le vel mode
- used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
configuration 01 ER INT, pulse mode
- used to generate a system interrupt pulse when any
flash device in an array has completed a Block Erase.
Helpful for reformatting blocks after file system free
space reclamation or "cleanup"
configuration 10 PR INT, pulse mode
-used to generate a system interrupt pulse when any
flash device in an array has complete a Program op-
eration. Provides highest performance for servicing
continuous buffer write operations.
configuration 11 ER/PR INT, pulse mode
-used to generate system interrupts to trigger servic-
ing of flash arrays when either erase or program opera-
tions are completed when a common interrupt service
routine is desired.
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Set Block Lock-Bit Commands
This device provided the block lock-bits, to lock and
unlock the individual b lock. To set the bloc k lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running or the
device is suspended. Writing the set bloc k lock-bit com-
mand of 60H followed by confirm command and an ap-
propriate block address. After the command is written,
the device automatically outputs status register data when
read. The CPU can detect the completion of the set lock-
bit event by analyzing the STS pin output or status reg-
ister bit SR.7. Also , reliab le operations occur only when
VCC and V PEN are va lid. With VPEN _VPENLK , loc k-
bit contents are protected against alteration.
Clear Block Lock-Bits Command
All set block lock-bits can clear by the Clear Block Lock-
Bits command. This command is in valid while the WSM
is running or the device is suspended. To Clear the block
lock-bits, tw o cycle command is requested . The de vice
automatically outputs status register data when read. The
CPU can detect completion of the clear block lock-bits
event by analyzing the STS pin output or status register
bit SR.7. If a clear block lock-bits operation is abor ted
due to V PEN or V CC transitioning out of valid range,
block lock-bit values are left in an undetermined state. A
repeat of clear block lock-bits is required to initialize block
lock-bit contents to known values.
Protection Register Program Command
The device offer a 128-bit protection register to increase
the security of a system design. The 128-bits protection
register are divided into two 64-bit segments. One is pro-
grammed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.
Reading the Protection Register
The protection register is read in the identification read
mode. The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-
tion. To return to read arra y mode, write the Read Arra y
command (FFH).
Programming the Protection Register
The protection register bits are programmed using the
two-cycle Protection Program command. The 64-bit num-
ber is programmed 16 bits at a time f or word-wide parts
and eight bits at a time for byte-wide parts. First write
the Protection Program Setup command, C0H. The next
write to the device will latch in address and data and
program the specified location.
Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error . Attempting to program a
locked protection register segment will result in a status
register error.
Locking the Protection Register
The user-programmable segment of the protection regis-
ter is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the Intel factory to protect the unique device number . Bit
1 is set using the Protection Program command to pro-
gram "FFFD" to the PR-LOCK location. After these bits
have been programmed, no further changes can be made
to the values stored in the protection register . Protection
Program commands to a locked section will result in a
status register error. Protection register lockout state is
not reversible.
27
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Figure 3. Protection Register Memory Map
NOTE: A 0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing).
F or x8 mode A 0 is used (See Table 21 f or x8 addressing).
88H
Word
Address
85H
4 Words
User Programmed
A[22 -1]: 64 Mbit
A[23 -1]: 128 Mbit
A[21 -1]: 32 Mbit
84H
81H
80H
4 Words
Factory Programmed
1 Word Lock
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Table 20. Word-Wide Protection Register Addressing
Word Use A8 A7 A6 A5 A4 A3 A2 A1
LOCK Both 1 0 0 0 0 0 0 0
0 Factory 1 0 0 0 0 0 0 1
1 Factory 1 0 0 0 0 0 1 0
2 Factory 1 0 0 0 0 0 1 1
3 Factory 1 0 0 0 0 1 0 0
4 User 1 0 0 0 0 1 0 1
5 User 1 0 0 0 0 1 1 0
6 User 1 0 0 0 0 1 1 1
7 User 1 0 0 0 1 0 0 0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A23-A9 = 0.
Table 21. Byte-Wide Protection Register Addressing
Word Use A8 A7 A6 A5 A4 A3 A2 A1
LOCK Both 1 0 0 0 0 0 0 0
LOCK Both 1 0 0 0 0 0 0 0
0 Factory 1 0 0 0 0 0 0 1
1 Factory 1 0 0 0 0 0 0 1
2 Factory 1 0 0 0 0 0 1 0
3 Factory 1 0 0 0 0 0 1 0
4 Factory 1 0 0 0 0 0 1 1
5 Factory 1 0 0 0 0 0 1 1
6 Factory 1 0 0 0 0 1 0 0
7 Factory 1 0 0 0 0 1 0 0
8 User 1 0 0 0 0 1 0 1
9 User 1 0 0 0 0 1 0 1
A User 1 0 0 0 0 1 1 0
B User 1 0 0 0 0 1 1 0
C User 1 0 0 0 0 1 1 1
D User 1 0 0 0 0 1 1 1
E User 1 0 0 0 1 0 0 0
F User 1 0 0 0 1 0 0 0
NOTE: 1. All address lines not specified in the abov e tab le must be 0 when accessing the Protection Register ,
i.e., A23-A9 = 0.
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Figure 4. Write to Buffer Flowchart
Start
Set Time-Out
Write Buffer Data,
Start Address
X = 0
Write to Another
Block Address
Write to Buffer
Failed
Issue Read
Status Command
Write Word or Byte
Count to Block Address
Write E8H to Block Address
Read Extended Status Register
NO
NO
YES
YES
YES
YES
YES
NO
NO
NO
YES
XSR.7=1 ?
Check
X=N ?
Abort Write to
Buffer Command?
Another Write
to Buffer ?
Write to Buffer
Time-Out ?
Write Next Buffer Data,
Device Address
X = X+1
Program Buffer to Flash
Confirm D0H
Read Status Register
SR.7=1?
Full Status Check if Desired
Programming Complete
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Figure 5. Program Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
Write FFH
NO
NO
YES
SR.7=1 ?
YES
SR.2=1 ?
Write D0H
YES
Programming Resumed
Write FFH
Read Array Data
Read Array Data
Programming Completed
NO
Done Reading
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Figure 6. Byte/Word Programming Flowchart Bus Command Comments
Operation
Write Setup Byte/ Data=40H
Word Program Addr=Location to Be
Programmed
Write Byte/Word Data=Data to Be
Program Programmed
Addr=Location to Be
Programmed
Read Status Register Data
(Note 1)
Standby Check SR.7
1=WSM Ready
0=WSM Busy
1. Toggling OE (low to high to low) updates the status
register . This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
SR full status check can be done after each program
operation, or after a sequence of programming opera-
tions.
Write FFH after the last program operation to place
device in read array mode.
Bus Command Comments
Operation
Standby Check SR.3
1=Programming to V oltage
Error Detect
Standby Check SR.1
1=Device Protect Detect
RP=VIH, Block Lock-Bit is
Set Only required for
systems
Standby Check SR.4
1=Programming Error
Toggling OE (low to high to low) updates the status
register . This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple lo-
cation are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Start
Write 40H,
Address
Write Data
and Address
Full Status Check if Desired
Byte/Word Program Complete
Read
Status Register
0
1
SR.7=
Read Status Register
Data (See Above)
FULL STATUS CHECK PROCEDURE
Byte/Word Program Successful
SR.3=
0
0
0
VPP Range Error
1
Programming Error
1Device Protect Error
1
SR.1=
SR.4=
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Figure 7. Block Erase Flowchart
Start
Write 20H to Block Address
Erase Flash
Block(s) Completed
Full Status Check
If Desired
Write Confirm D0H to Block Address
Read
Status Register
NO NO
YES
Suspend Loop
Write D0H
SR.7=1 ? Write B0H?
YES
YES
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Figure 8. Block Erase Suspend/Resume Flowchart
Start
Block Erase Resumed
Erase Completed
Write B0H
Read
Status Register
0
0
1
Write D0H
SR.7=
1
SR.6=
Read or Program? ProgramRead
Read Array
Data Program
Loop
Yes
No
Done ?
Read Array Data
Write FFH
Bus Command Comments
Operation
Write Erase Data=B0H
Suspend Addr=X
Read Status Register Data
Addr=X
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Standby Check SR.6
1=Block Erase Suspend
0=Block Erase Completed
Write Erase Data=D0H
Resume Addr=X
34
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Figure 9. Set Block Lock-Bit Flowchart
Start
Write 60H, Block Address
Set Lock-Bit Completed
Full Status Check
If Desired
Write 01H, Block Address
Read
Status Register
NO
YES
SR.7=1 ?
Read Status Register
Data (See Above)
FULL STATUS CHECK PROCEDURE
Set Lock-Bit Successful
SR.3=0 ?
YES
NO
YES
Voltage Range Error
NO
Command Sequence Error
YES
Set Lock-Bit Error
NO
SR.4,5=1 ?
SR.4=0 ?
35
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Figure 10. Clear Lock-Bit Flowchart
Start
Write 60H
Set Lock-Bit Completed
Full Status Check
If Desired
Write D0H
Read
Status Register
NO
YES
SR.7=1 ?
Read Status Register
Data (See Above)
FULL STATUS CHECK PROCEDURE
Clear Block Lock-Bit Successful
SR.3=0 ?
YES
NO
YES
Voltage Range Error
NO
Command Sequence Error
YES
Clear Block Lock-Bits Error
NO
SR.4,5=1 ?
SR.5=0 ?
36
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Figure 11. Protection Register Programming Flowchart
Start
Write C0H (Protection Reg.
Program Setup)
Program Completed
Full Status Check
If Desired
Write Protect. Register
Address/Data
Read
Status Register
NO
YES
SR.7=1 ?
Read Status Register
Data (See Above)
FULL STATUS CHECK PROCEDURE
Program Successful
SR.3, SR.4=
YES
VPEN Range Error
1,1
1,1
Protection Register
Programming Error
0,1
Attempted Program to Locked
Register-Aborted
SR.1, SR.4=
SR.1, SR.4=
37
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ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
V oltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE, and
RESET or RESET(Note 2) . . . . . . . . .-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC v oltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE, and RE-
SET or RESET is -0.5 V. Dur ing voltage transitions,
A9, OE, and RESET or RESET may overshoot VSS
to -2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC input voltage on pin A9 is +12.5 V which
ma y o v ershoot to 14.0 V f or periods up to 20 ns.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Rat-ings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ) . . . . . . . . . . . . 0 °C to +70°C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
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Symbol Parameter Notes Typ Max Unit Test Conditions
ILI Input and V PEN Load Current 1 ±1 uA VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
ILO Output Leakage Current 1 ±10 uA VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
CMOS Inputs, VCC = VCC Max,
ICC1 VCC Standby Current 1,2,3 2 5 80 uA Device is disabled (see table 2)
RESET=VCCQ±0.2V or RESET=VIL
0.71 2 mA TTL Inputs, VCC=VCC max,
Device is disable (see table 2),
RESET=VIH or RESET=VIL
ICC2 VCC Power-Down Current 2 5 uA RESET=GND±0.2V, or RESET=VIH
IOUT(STS)=0mA
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
1 5 2 0 mA Device is enabled (see Table 2)
ICC3 VCC Page Mode Read Current 1,3 f=5MHz, IOUT=0mA
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
2 4 2 9 mA Device is enabled (see Table 2)
f=33MHz, IOUT=0mA
CMOS Inputs, VCC=VCC Max,
ICC4 VCC Word Mode Read Current 1,3 4 0 50 mA VCCQ=VCCQ Max
Device is enabled (see Table 2)
f=5MHz, IOUT=0MA
ICC5 VCC Program or Set Lock-Bit 1,4 3 5 6 0 mA CMOS Inputs, VPEN=VCC
Current 40 70 mA TTL Inputs, VPEN=VCC
ICC6 VCC Block Erase or Clear 1, 4 35 7 0 mA CMOS Inputs, VPEN=VCC
Block Lock-Bits Current 4 0 8 0 mA TTL Inputs, VPEN=VCC
ICC7 VCC Program Suspend or Block 1,5 1 0 mA Device is disabled (see Table 2)
Erase Suspend Current
DC Characteristics
39
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Symbol Parameter Notes Min Max Unit Test Conditions
VIL Input Low V oltage 4 -0.5 0.8 V
VIH Input High V oltage 4 2.0 VCCQ+0.5 V
0.4 V VCCQ=VCCQ2/3 Min
IOL=2mA
V OL Output Low V oltage 2,4 0.2 V VCCQ=VCCQ2/3 Min
IOL=100uA
0.85 x V VCCQ=VCCQ Min
VCCQ IOH=-2.5mA
V OH Output High V oltage 2,4 VCCQ-0.2 V VCCQ=VCCQ Min
IOH=-100uA
VPENLK VPEN Lockout during Program, 4,6,7 2.2 V
Erase and Lock-Bit Operations
VPENH VPEN during Block Erase, 6, 7 2. 7 3. 6 V
Program, or Lock-Bit Operations
VLK O VCC Lockout V oltage 8 2.2 V
DC Characteristics, Continued
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid f or all product versions (packages and
speeds).
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH .
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device de-selected. If the device is read or written while in erase suspend
mode, the device's current draw is I CCR or I CCW .
6. Block erases, programming, and lock-bit configurations are inhibited when V PEN ˆ V PENLK , and not guaranteed
in the range between VPENLK (max) and VPENH (min), and above VPENH (max).
7. Typically, VPEN is connected to VCC (2.7 V - 3.6 V).
8. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the
range between VLK O (min) and VCC (min), and above VCC (max).
40
P/N:PM0858 REV. 0.4, JUN. 07, 2002
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Figure 12. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V or VCCQ=2.7V-3.6 V
TEST POINTS VCCQ/2 Output
Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0".
Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ).
Input rise and fall times (10% tp 90%)<5ns.
VCCQ
0.0
Input VCCQ/2
Figure 13. Transient Equivalent Testing Load Circuit
NOTE: CL Includes Jig Capacitance
T est Configuration C L (pF)
VCCQ = VCC = 3.0 V-3.6 V 3 0
VCCQ = VCC = 2.7 V-3.6 V 3 0
Device
Under Test
CL
Out
RL=3.3K ohm
1.3V
1N914
41
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Versions VCC 3.0V-3.6V(3) 2.7V-3.6V(3)
(All units in ns unless otherwise noted) VCCQ 3.0V-3.6V(3) 2.7V-3.6V(3)
Sym Parameter Notes Min Max Min Max
tAVAV Read/Write Cycle Time 32M 120 120
64M 7 120 120
128M 150 150
tA VQV Address to Output Delay 32 M 1 2 0 1 2 0
64M 120 120
128M 150 150
tELQV CEX to Output Delay 32 M 2 1 2 0 1 2 0
64M 2, 7 120 120
128M 2 150 150
tGLQV OE to Non-Array Output Delay 2, 4 5 0 5 0
tPHQV RESET High to Output Delay 32M 1 8 0 1 8 0
64M 180 180
128M 8 210 210
tELQX CEX to Output in Low Z 5 0 0
tGLQX OE to Output in Low Z 5 0 0
tEHQZ CEX High to Output in High Z 5 35 35
tGHQZ OE High to Output in High Z 5 1 5 15
t OH Output Hold from Address, CEX, or OE 5 0 0
Change, Whichever Occurs First
tELFL/tELFH CEX Low to BYTE High or Low 5 1 0 10
tFLQV/tFHQV BYTE to Output Delay 1000 1000
tFLQZ BYTE to Output in High Z 5 1000 1000
tEH EL CEx High to CEx Low 5 0 0
tAPA Page Address Access Time 5, 6 2 5 30
tGLQV OE to Array Output Delay 4 2 5 30
AC Characteristics --Read-Only Operations (1,2)
NO TES:CEX lo w is defined as the first edge of CE0 , CE1 , or CE2 that enab les the de vice . CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the de vice (see Ta ble 2).
1. See A C Input/Output Reference W a vef orms f or the maximum allowa ble input slew r ate.
2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE0, CE1, or CE2 that enables the device (see
Ta ble 2) without impact on t ELQV .
3 . See Figures 14-16, T ransient Input/Output Reference Waveform for VCCQ = 3.0V - 3.6V or VCCQ = 2.7V -3.6 V, and
Transient Equiv alent Testing Load Circuit f or testing characteristics.
4. When reading the flash arra y a f aster tGLQV (R16) applies. Non-arra y reads ref er to status register reads , query
reads, or device identifier reads.
5. Sampled, not 100% tested.
6. For devices configured to standard w ord/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
7. The performance of 64Mb depends on 120ns speed grade or 150ns speed grades.
8. tPHQV is RESET low to output delay for 48-TSOP & 48-RTSOP package types.
42
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Figure 14. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations (for 56-
TSOP & 64-CSP)
NOTE:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the de vice (see Tab le 2).
2. For standard word/byte read operations, tAPA will equal tAVQV.
3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,
or device identifier reads.
tAVQV
tAVAV
tAPA
tGLQX
tELQX
tEHQZ
tEHEL
tGHQZ
tOH
tELFL/tELFH tFLQV/tFHQV tFLQZ
tELQV
tGLQV
High Z
tPHQV
Valid Address Valid Address
Valid
Output
Valid
Output
Valid Address Valid Address
Valid
Output Valid
Output High Z
Address
(A23-A3)
VIH
VIL
VIH
VIL
VIH
Disable
Enable VIL
VIH
VIL
Address
(A2-A0)
CEx[E]
OE [G]
VIH
VIL
WE [W]
VIH
VIL
VCC
VIH
VIL
RESET[P]
VIH
VIL
BYTE [F]
VOH
VOL
DATA[D/Q]
Q0- Q15
43
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Figure 15. AC Waveform for Both Pag e-Mode and Standard Word Read Operations (for 48-TSOP
& 48-RTSOP)
NOTE:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the de vice (see Table 2).
2. F or standard word/byte read operations, tAPA will equal tA VQV.
3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,
or device identifier reads.
4. For 48-TSOP & 48-RTSOP the RESET pin is high enable.
tAVQV
tAVAV
tAPA
tGLQX
tELQX
tEHQZ
tEHEL
tGHQZ
tOH
tELQV
tGLQV
High Z
tPHQV
Valid Address Valid Address
Valid
Output
Valid
Output
Valid Address Valid Address
Valid
Output Valid
Output High Z
Address
(A23-A3)
VIH
VIL
VIH
VIL
VIH
Disable
Enable VIL
VIH
VIL
Address
(A2-A0)
CEx[E]
OE [G]
VIH
VIL
WE [W]
VIH
VIL
VCC
VIH
VIL
RESET[P]
(Note 4)
VOH
VOL
DATA[D/Q]
Q0- Q15
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AC Characteristics--Write Operations (1,2)
Versions Valid for All
Speeds Unit
Symbol Parameter Notes Min Max
tPHWL (tPHEL ) RESET High Recovery to WE(CEX) Going Low 3,10 2 us
tEL WL (tWLEL ) CEX (WE) Low to WE(CEX) Going Low 4 0 ns
tWP Write Pulse Width 4 7 0 ns
tD VWH (tD VEH ) Data Setup to WE(CEX) Going High 5 5 0 ns
tA VWH (tA VEH ) Address Setup to WE(CEX) Going High 5 5 5 ns
tWHEH (tEHWH) CEX (WE) Hold from WE(CEX) High 0 ns
tWHDX (tEHDX) Data Hold from WE(CEX) High 0 ns
tWHAX (tEHAX) Address Hold from WE(CEX) High 0 ns
tWPH Write Pulse Width High 6 30 ns
tVPWH (tVPEH) VPEN Setup to WE(CEX) Going High 3 0 ns
tWHGL (tEHGL) Write Recovery before Read 7 3 5 ns
tWHRL (tEHRL) WE(CEX) High to STS Going Low 8 50 0 ns
tQVVL VPEN Hold from V alid SRD, STS Going High 3,8,9 0 ns
tWHQV5 (tEHQV5) Set Lock-Bit Time 4, 9 6 4 75/85 us
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time 4 0 .5 0.70 sec
tWHRH1 (tEHRH1) Program Suspend Latency Time to Read 9 2 5 75/90 us
tWHRH (tEHRH) Erase Suspend Latency Time to Read 9 2 6 35/40 us
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the de vice (see Ta ble 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4 . Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high
(whiche v er goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Ref er to Table 4 for valid A IN and D IN for bloc k erase, prog ram, or loc k-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whiche v er goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. F or array access, tAVQV is required in addition to tWHGL f or an y accesses after a write.
8. STS timings are based on STS configured in its RY/BY default mode .
9. VPEN should be held at VPENH until deter mination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
10 .F or 48-TSOP & 48-RTSOP, the RESET pin is high enab le.
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Figure 16. AC Waveform for Write Operations (for 56-TSOP & 64-CSP)
NOTES:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the de vice (see Tab le 2).
STS is shown in its def ault mode (RY/BY).
a. VCC power-up and standby .
b . Write block er ase, write buff er, or program setup .
c. Write bloc k erase or write buffer confirm, or valid address and data.
d. A utomated erase dela y.
e. Read status register or query data.
f. Write Read Arra y command.
tVPWH
(tVPEH)
tWHRL
(tEHRL)
tQVVL
tWHQZ/tWHRH
tWPH
tAVWH
(tAVEH)
tPHWL
(tPHEL)
tWP
tWHDX
(tEHDX)
tWHEH
(tEHWH)
tWHAX
(tEHAX)
tELWL
(tWLEL)
tOVWH
(tDVEH)
tWHGL
(tEHGL)
DIN
Address
(A)
AB CD E F
VIH
VIL
OE
VIH
VIL
VIH
Disable
Enable VIL
CEx,(WE)[E(W)]
VIH
Disable
Enable VIL
WE,(CEx)[W(E)]
VIH
VIL
DATA[D/Q]
VOH
VOL
STS[R]
VIH
VIL
VPENH
VPENLK
VIL
RESET [P]
VPEN[V]
DIN
AIN AIN
DIN
Valid
SRD
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Figure 17. AC Waveform for Write Operations (for 48-TSOP & 48-RSOP)
NOTES:
1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the de vice (see Table 2).
STS is shown in its def ault mode (RY/BY).
a. VCC power-up and standby .
b . Write block er ase, write buff er, or program setup .
c. Write bloc k erase or write buffer confirm, or valid address and data.
d. A utomated erase dela y.
e. Read status register or query data.
f. Write Read Arra y command.
2. F or 48-TSOP & 48-R TSOP, the RESET pin is high enab le.
tWHQZ/tWHRH
tWPH
tAVWH
(tAVEH)
tPHWL
(tPHEL)
tWP
tWHDX
(tEHDX)
tWHEH
(tEHWH)
tWHAX
(tEHAX)
tELWL
(tWLEL)
tOVWH
(tDVEH)
tWHGL
(tEHGL)
DIN
Address
(A)
AB CD E F
VIH
VIL
OE
VIH
VIL
VIH
Disable
Enable VIL
CEx,(WE)[E(W)]
VIH
Disable
Enable VIL
WE,(CEx)[W(E)]
VIH
VIL
DATA[D/Q]
VIH
VIL
RESET [P]
(Note 2)
DIN
AIN AIN
DIN
Valid
SRD
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Figure 18. AC Waveform for Reset Operation (for 56-TSOP & 64-CSP)
NOTE:
1. STS is shown in its def ault mode (RY/BY).
Sym Parameter Notes Min Max Unit
tPLPH RESET Pulse Low Time 2 3 5 us
(If RESET is tied to VCC , this specification is not applicable)
(for 48-TSOP & 48-RST OP, the tPLPH indicates the RESET
Pulse High Time)
tPHRH RESET High to Reset during Block Erase, Program, or 3 2 us
Lock-Bit Configuration
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RESET is asserted while a block erase, progr am, or loc k-bit configur ation oper ation is not executing then the
minimum required RESET Pulse Low Time is 100ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are
valid.
Reset Specifications (1)
Figure 19. AC Waveform for Reset Operation (for 48-TSOP & 48-RTSOP)
tPHRH
tPLPH
VIH
VIL
STS (R)
VIH
VIL
RESET (P)
NOTE:
1. STS is shown in its def ault mode (RY/BY).
2. F or 48-TSOP & 48-RTSOP, the RESET pin is high enab le.
tPLPH
VIH
VIL
RESET (P)
(Note 2)
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MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
LIMITS
PARAMETER MIN. TYP.(2) MAX. UNITS
Block Erase Time 2.0 15.0 sec
Write Buffer Byte Program Time 2 1 8 6 5 4 us
(Time to Program 32 bytes/16 words)
Byte Program Time (Using Word/Byte Program Command) 210 630 us
Block Program Time (Using Write to Buffer Command) 0. 8 2.4 sec
Block Erase/Program Cycles C 1 1 0 Cycles
C2 100
C3 1,000
C4 10,000
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE(1)
Note: 1.Not 100% Tested, Excludes external system le vel o v er head.
2.Typical values measured at 25°C,3.3V. Additionally programming typically assume checkerboard pattern.
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN Input Capacitance VIN=0 6 8 pF
COUT Output Capacitance VOUT=0 8 1 2 pF
CAPACITANCE TA=0°°
°°
°C to 70°°
°°
°C, VCC=2.7V~3.6V
Notes:
1. Sampled, not 100% tested.
2. T est conditions T A=25°C , f=1.0MHz
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150 1 0 Years
125 20 Years
DATA RETENTION
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ORDERING INFORMATION
PLASTIC PACKAGE
Part NO. Access Time Package type Cycles
(ns)
MX28F128J3TBC-15C1 150/25 48-TSOP 10
MX28F128J3RBC-15C1 150/25 48-RTSOP 10
MX28F128J3TC-15C3 150/25 56-TSOP 1,000
MX28F128J3TBC-15C3 150/25 48-TSOP 1,000
MX28F128J3RBC-15C3 150/25 48-RTSOP 1,000
MX28F128J3XCC-15C3 150/25 64-CSP 1,000
MX28F128J3TC-15C4 150/25 56-TSOP 10,000
MX28F128J3TBC-15C4 150/25 48-TSOP 10,000
MX28F128J3RBC-15C4 150/25 48-RTSOP 10,000
MX28F128J3XCC-15C1 150/25 64-CSP 10
MX28F128J3XCC-15C4 150/25 64-CSP 10,000
MX28F640J3TC-12C3 120/25 56-TSOP 1,000
MX28F640J3IAC-12C3 120/25 48-FCCSP 1,000
MX28F640J3XCC-12C3 120/25 64-CSP 1,000
MX28F640J3TC-15C4 150/25 56-TSOP 10,000
MX28F640J3IAC-15C4 150/25 48-FCCSP 10,000
MX28F640J3XCC-15C4 150/25 64-CSP 10,000
MX28F320J3TC-12C3 120/25 56-TSOP 1,000
MX28F320J3IAC-12C3 120/25 48-FCCSP 1,000
MX28F320J3XCC-12C3 120/25 64-CSP 1,000
MX28F320J3TC-12C4 120/25 56-TSOP 10,000
MX28F320J3IAC-12C4 120/25 48-FCCSP 10,000
MX28F320J3XCC-12C4 120/25 64-CSP 10,000
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PACKAGE INFORMATION
48-Ball Flip Chip CSP
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56 TSOP
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64 CSP
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48 TSOP
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48 TSOP (Reverse )
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REVISION HISTORY
Revision No. Description Page Date
0.1 1. To add 32M/128M information All JAN/17/2002
2. To modify the CSP package size from 13x10mm to 10x13mm P3
0. 2 1. Add 48-TSOP P1 APR/04/2002
2. Technology name is changed from MXVAND to Nbit P 1
3. 48-ball CSP name is added "Flip Chip" wording P1
4. 64-ball CSP naming is changed P1,4
5. Mis-tying : removing verify sector
5-1 Protection code from Table 14 P8,19
5-2 Correct Program Suspend/Resume flowchart P30
5-3 Correct Block Erase Suspend/Resume flowchart P31
0.3 1. Added 48-RTSOP P1,3,47 MAY/28/2002
2. Added deep power-down spec:5uA(max.) P1,9,11,38
3. Changed standby current from 120uA(max.) to 80uA(max.) P38
4. Added "Cx" on part number to distinguish different program P1,3,46,47
5. Changed spec of tPHWL(tPHEL) from 1us to 2us P4 3
6. Changed spec of tPHRH from 100ns to 2us P 45
7. Changed speed spec of 32Mb from 110ns-->120ns P1,41,47
0. 4 Deep power down mode is entering by RESET pin at VIH of P3,5,6,8,9,20, JUN/07/2002
48-TSOP & 48-RTSOP types. 64-CSP & 56-TSOP is still kept P37,38,41~47
RESET=VIL for entering deep power down mode.
Removed reset command P10,11
MX28F320J3/640J3/128J3
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