1. Product profile
1.1 General description
135 W LDMOS power transistor for base station applications at frequencies from
700 MHz to 1000 MHz.
[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier; carrier
spacing 5 MHz.
1.2 Features
Typical 2-carrier W-CDMA performance at freque ncies of 869 MHz and 894 MHz, a
supply voltage of 28 V and an IDq of 950 mA:
Average output power = 26.5 W
Power gain = 21.0 dB
Efficiency = 28.0 %
ACPR = −39 dBc
Easy power control
Integrated ESD protection
Enhanced ruggedness
High efficiency
Excellent thermal stability
Designed for broadband operation (700 MHz to 1000 MHz)
Internally matched for ease of use
Compliant to Directive 2002/95/EC, rega rd in g re str icti on of hazardous substances
(RoHS)
BLF6G10-135RN;
BLF6G10LS-135RN
Power LDMOS transistor
Rev. 02 — 21 January 2010 Product data sheet
Table 1. Typical perf ormance
Ty pical RF performance at Tcase = 25
°
C in a class-AB production test circuit.
Mode of operation f VDS PL(AV) GpηDACPR
(MHz) (V) (W) (dB) (%) (dBc)
2-carrier W-CDMA 869 to 894 28 26.5 21.0 28.0 −39[1]
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 2 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
1.3 Applications
RF power amplifiers for GSM, GSM EDGE, W-CDMA and CDMA base stations and
multi carrier applications in the 700 MHz to 1000 MHz frequency range
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF6G10-135RN (SOT502A)
1drain
2gate
3source [1]
BLF6G10LS-135RN (SOT 502B)
1drain
2gate
3source [1]
3
2
1
sym11
2
1
3
2
3
2
1
sym11
2
1
3
2
Table 3. Ordering informati on
Type number Package
Name Description Version
BLF6G10-135RN - flanged LDMOST ceramic package; 2 mounting holes;
2 leads SOT502A
BLF6G10LS-135RN - earless flanged LDMOST ce ramic package; 2 leads SOT502B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage −0.5 +13 V
IDdrain current - 32 A
Tstg storage temperature −65 +150 °C
Tjjunction temperature - 225 °C
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 3 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
5. Thermal characteristics
6. Characteristics
7. Application information
7.1 Ruggedness in class-AB operation
The BLF6G10-135RN and BLF6G10LS-135RN are capable of withstanding a load
mismatch corr es po nd in g to VSWR = 10 : 1 through all phas es und er the follo win g
conditions: VDS =28V; I
Dq =950mA; P
L=135 W; f=894MHz.
Table 5. Thermal characteristics
Symbol Parameter Conditions Type Typ Unit
Rth(j-case) thermal resistance from
junction to case Tcase =80°C; PL= 25 W BLF6G10-135RN 0.68 K/W
BLF6G10LS-135RN 0.56 K/W
Table 6. Characteristics
Tj = 25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source brea kdown voltage VGS =0V; I
D=0.8mA 65 - - V
VGS(th) gate-source threshold voltage VDS = 10 V; ID= 180 mA 1.4 1.9 2.4 V
VGSq gate-source quiescent voltage VDS = 28 V; ID= 950 mA 1.6 2.1 2.6 V
IDSS drain leakage current VGS =0V; V
DS =28V - - 3 μA
IDSX drain cut-off current VGS =V
GS(th) + 3.75 V;
VDS =10V 24 32 - A
IGSS gate leakage current VGS =11V; V
DS = 0 V - - 300 nA
gfs forward transconductance VDS =10V; I
D=9A 7 13 - S
RDS(on) drain-source on-state resistance VGS =V
GS(th) + 3.75 V;
ID=6.3A -0.1- Ω
Crs feedback capacitance VGS =0V; V
DS =28V;
f=1MHz -2.0- pF
Table 7. Application information
Mode of operation: 2-carrier W-CDMA; PAR 7.5 dB at 0.01 % probability on CCDF; 3GPP test
model 1; 1-64 PDPCH; f1= 871.5 MHz; f2= 876.5 MHz; f3= 886.5 MHz; f4= 891.5 MHz;
RF performance at VDS =28V; I
Dq = 950 mA; Tcase =25
°
C; unless otherwise specified; in a
class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
PL(AV) average output power - 26.5 - W
Gppower gain PL(AV) = 26.5 W 20.0 21.0 - dB
RLin input return loss PL(AV) = 26.5 W - −10.0 −6.5 dB
ηDdrain efficiency PL(AV) = 26.5 W 26.0 28.0 - %
ACPR adjacent channel power ratio PL(AV) = 26.5 W - −39 −36.5 dBc
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 4 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
VDS =28V; I
Dq = 950 mA; f = 881 MHz.
Fig 1. One-tone CW power gain and drain efficiency as function of load power;
typical values
PL (W)
0 16012040 80
001aah864
21
22
20
23
24
Gp
(dB)
ηD
(%)
19
30
45
15
60
75
0
Gp
ηD
VDS =28V; I
Dq = 950 mA; f1= 881 MHz (±100 kHz). VDS =28V; I
Dq = 950 mA; f1= 881 MHz (±100 kHz).
Fig 2. Two-tone CW power gain and drain efficiency
as function of peak envelop e load power;
typical valu e s
Fig 3. Two-tone CW intermodulation distortion as a
function of peak envelop e load power;
typical values
PL(PEP) (W)
0 1007525 50
001aah865
21
20
22
23
Gp
(dB)
ηD
(%)
19
30
15
45
60
0
Gp
ηD
PL(PEP) (W)
0 1007525 50
001aah866
−40
−50
−30
−20
IMD
(dBc)
−60
IMD3
IMD5
IMD7
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 5 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
8. Test information
VDS =28V; I
Dq = 950 mA; f1= 881 MHz; f2=886MHz;
carrier spacing 5 MHz. VDS =28V; I
Dq = 950 mA; f1= 881 MHz; f2= 886 MHz;
carrier spacing 5 MHz.
Fig 4. 2-carrier W-CDMA power gain and drain
efficiency as function of average load power;
typical valu e s
Fig 5. 2-carrier W-CDMA adjacent power channel
ratio as a function of average load power;
typical values
PL(AV) (W)
0604824 3612
001aah867
21
22
20
23
24
Gp
(dB)
ηD
(%)
19
20
30
10
40
50
0
Gp
ηD
PL(AV) (W)
0604020
001aah868
−40
−30
−20
ACPR
(dBc)
−50
The drawing is not to scale.
Fig 6. Test circuit for opera tio n at 800 MHz
001aah86
9
input
50 Ω
output
50 Ω
VGG
C2
C1
C16
C5
C4
C7
C6
C3
R2
VDD
C20
C15 C19
C18C11
C14C13C12
C17
L1
R3
R1 C10C9C8
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 6 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
[1] American Technical Ceramics type 100B or capacitor of same quality.
[2] TDK or capacitor of same quality.
The striplines are on a double copper-clad Taconic RF35 Printed-Circuit Board (PCB) with εr= 3.5 and thickness = 0.76 mm.
See Table 8 for list of components.
The drawing is not to scale.
Fig 7. Component layout
001aah87
0
OUT
800 -1000 MHz
V1.0
C8
IN
800 -1000 MHz
V1.0
C9
C10 C11
C18
C20
C6
C4
C5
Q1
C7 C19 C16
C17
R3
L1
C15
C14
C13C12
R2
C2C1
C3
R1
Table 8. List of components
See Figure 6 and Figure 7.
Component Description Value Remarks
C1, C3, C10, C14, C17 multilayer ceramic chip capacitor 68 pF [1] solder vertically
C2, C4, C5 multilayer ceramic chip capacitor 8.2 pF [1] solder vertically
C6, C7 multilayer ceramic chip capacitor 10 pF [1] solder vertically
C8, C9, C12, C13 electrolytic capacitor 100 nF Vishay or capacitor of same quality.
C11, C15 mu lti l aye r ceramic chip capacitor 4.7 μF; 50 V [2]
C16 multilayer ceramic chip capacitor 3.0 pF [1] solder vertically
C18, C19, C20 electrolytic capacitor 220 μF; 63 V
L1 ferrite SMD bead Ferroxcube BDS 3/3/4.6-4S2 or equivalent
Q1 BLF6G10LS-135RN
R1, R2, R3 SMD resistor 9.1 Ω; 0.1 W
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 7 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
9. Package outline
Fig 8. Package outline SOT502A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 99-12-28
03-01-10
0 5 10 mm
scale
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502
A
p
L
A
F
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57
0.15
0.08
20.02
19.61
9.53
9.25
19.94
18.92
9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495
0.006
0.003
0.788
0.772
D1
19.96
19.66
0.786
0.774
0.375
0.364
0.785
0.745
0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035
1.345
1.335
0.210
0.170
0.133
0.123
0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 8 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
Fig 9. Package outline SOT502B
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502B 03-01-10
07-05-09
0 5 10 mm
scale
Earless flanged LDMOST ceramic package; 2 leads SOT502
B
A
F
b
D
U2
L
H
Q
c
1
3
2
D1
E
D
U1
D
E1
M M
w2
UNIT A
mm
Db
12.83
12.57
0.15
0.08
20.02
19.61
9.53
9.25
19.94
18.92
9.91
9.65
4.72
3.43
cU2
0.25
w2
F
1.14
0.89
U1
20.70
20.45
L
5.33
4.32
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495
0.006
0.003
0.788
0.772
D1
19.96
19.66
0.786
0.774
0.375
0.364
0.785
0.745
0.390
0.380
0.186
0.135 0.010
0.045
0.035
0.815
0.805
0.210
0.170
0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 9 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
10. Abbreviations
11. Revision history
Table 9. Abbreviations
Acronym Description
3GPP Third Generation Partnership Project
CCDF Complementary Cumulative Distribution Function
CDMA Code Division Multiple Access
CW Continuous Wave
DPCH Dedicated Physical CHannel
EDGE Enhanced Data rates for GSM Evolution
GSM Global System for Mobile communications
LDMOS Laterally Diffused Metal-Oxide Semiconductor
LDMOST Laterally Diffused Metal-Oxide Semiconductor T ransistor
PAR Pea k-to-Average power Ratio
PDPCH transmission Power of the Dedicated Physical CHannel
RF Radio Frequency
SMD Surface Mounted Device
VSWR Voltage Standing-Wave Ratio
W-CDMA Wideband Code Division Multiple Access
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLF6G10-135RN_10LS-135RN_2 20100121 Product data sheet - BLF6G10-135RN_10LS-135RN_1
Modifications •Section 1.1 “General description” lower frequency range extended to 700 MHz
from 800 MHz.
•Section 1.2 “Features” lower frequency range extended to 700 MHz from 800 MHz.
•Section 1.3 “Applications” lower frequency range extended to 700 MHz from
800 MHz.
•Section 12 “ Legal information” export control disclaimer added.
BLF6G10-135RN_10LS-135RN_1 20090210 Product data sheet - -
BLF6G10-135RN_10LS-135RN_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 21 January 2010 10 of 11
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
12.3 Disclaimers
General — In formation in this document is believed to be accurate and
reliable. However, NXP Semiconduct ors does not give any repr esentatio ns or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or application s and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ra tings System of IEC 60134) may cause permane nt
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercia l sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warr anty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
12.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data fro m the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors BLF6G10(LS)-135RN
Power LDMOS transistor
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 January 2010
Document identifier: BLF6G1 0-135RN_10LS-135RN_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Application information. . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Contact information. . . . . . . . . . . . . . . . . . . . . 10
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
