AS1154
Dual LVDS Driver
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Datasheet
1 General Description
The AS1154 is a dual Flow-Through LVDS (Low-Voltage Differential
Signaling) Line Driver which accepts and converts LVTTL/LVCMOS
input levels into LVDS output signals. The device is perfect for low-
power low-noise applications requiring high signaling rates and
reduced EMI emissions.
The device is guaranteed to transmit data at speeds up to 800Mbps
(400MHz) over controlled impedance media of approximately 100Ω.
Supported transmission media are PCB traces, backplanes, and
cables.
Outputs conform to the ANSI TIA/EIA-644 LVDS standards. Flow-
through pinout simplifies PC board layout and reduces crosstalk by
separating the LVTTL/LVCMOS inputs and LVDS outputs.
The AS1154 operates from a single +3.3V supply and is specified for
operation from -40°C to +85°C.
Figure 1. AS1154 - Block Diagram
2 Key Features
Flow-Through Pinout
Guaranteed 800Mbps Data Rate
250ps Pulse Skew (Max)
Conforms to ANSI TIA/EIA-644 LVDS Standards
Single +3.3V Supply
Operating Temperature Range: -40°C to +85°C
8-Pin SOIC Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/
Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/
Routers, Backplane Interconnect, Clock Distribution Computers,
Intelligent Instruments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Battery-Powered
Equipment.
AS1154
VCC
IN1
IN2
GND
OUT1-
OUT1+
OUT2+
OUT2-
Tx
Tx
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AS1154
Datasheet - Pinout
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top Vie w)
Pin Descriptions
Table 1. Pin Descriptions
Pin Number Pin Name Description
1VCC
Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
2IN1
LVTTL/LVCMOS Driver Input
3IN2
LVTTL/LVCMOS Driver Input
4GND
Ground
5OUT2-
Inverting LVDS Driver Output
6OUT2+
Noninverting LVDS Driver Output
7OUT1+
Noninverting LVDS Driver Output
8OUT1-
Inverting LVDS Driver Output
OUT1-
OUT1+
OUT2+
OUT2-
VCC
IN1
IN2
GND
AS1154
1
2
3
4
8
7
6
5
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AS1154
Datashee t - A b s o l u t e M a x i mu m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Min Max Units Comments
Electrical Parameters
VCC to GND -0.3 5.0 V
INx to GND -0.3 Vcc + 0.3 V
OUTx+, OUTx- to GND -0.3 5.0 V
Short Circuit Duration (OUTx+, OUTx-) Continuous
Electrostatic Discharge
Electrostatic Discharge HBM +/- 4 kV Norm: MIL 883 E method 3015, INx, OUTx+, OUTx-
Continous Power Dissipation (TA = +70°C)
Continous Power Dissipation 755 mW PT1 for 8-pin SOIC Package
1. Depending on actual PCB layout and PCB used.
Continous Power Dissipation Derating Factor 9.4 mW / °C PDERATE2
2. PDERATE derating factor changes the total continuous power dissipation (PT) if the ambient temperature is not 70ºC. Therefore for e.g.
TA=85ºC calculate PT at 85ºC = PT - PDERATE x (85ºC - 70ºC)
Temperature Ranges and Storage Conditions
Junction Temperature +150 ºC
Storage Temperature Range -55 +125 ºC
Package Body Temperature +260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Humidity non-condensing 5 85 %
Moisture Sensitive Level 1 Represents a max. floor life time of unlimited
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AS1154
Datasheet - Electrical Characteristics
6 Electrical Characteristics
DC Electrical Characteristics
VCC = +3.0V to +3.6V, TA = -40°C to +85°C, RL = 100Ω ±1%, (Typical values are at VCC = +3.3V, TA = +25°C) unless otherwise specified; 1
Notes:
1. Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD.
2. Guaranteed by correlation data.
3. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality
Control) methods.
Table 3. DC Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
Operating Temperature Range TA -40 +85 °C
LVDS Output (OUtx+, OUTx-)
Differential Outp ut Voltage VOD Figure 21 on page 12 250 355 450 mV
Change in Magnitude of VOD Between
Complem en ta ry Outp ut States ΔVOD Figure 21 on page 12 1 35 mV
Offset Voltage VOS Figure 21 on page 12 1.125 1.25 1.375 V
Change in Magnitude of VOS Between
Complem en ta ry Outp ut States ΔVOS Figure 21 on page 12 4 25 mV
Output High Voltage VOH 1.6 V
Output Low Voltage VOL 0.90 V
Differential Output Short-Circuit
Current 2IOSD VOD = 0V -9 mA
Output Short-Circuit Current IOS OUTx+ = 0V at INx = VCC or
OUTx- = 0V at INx = 0V -3.7 -9 mA
Power-Off Output Current IOFF VCC = 0V or open, OUTx+ = 0V or 3.6V
OUTx- = 0V or 3.6V, RL = -20 20 µA
Inputs (INx)
High-Level Input Voltage VIH 2.0 VCC V
Low-Level Input Voltage VIL GND 0.8 V
Input Current IIN INx = 0V or VCC -20 20 µA
Supply Current
No-Load Supply Current ICC RL = , INx = VCC or 0V for all channels 2 3.5 mA
Loaded Supply Current ICCL RL = 100Ω, INx = VCC or 0V for all channels 5.5 7.5 mA
RL = 100Ω, INx = VCC or 0V for all channels 8.5 12 mA
∞
∞
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AS1154
Datasheet - Electrical Characteristics
Switching Characteristics
VCC = +3.0V to +3.6V, RL = 100 Ω ±1%, CL = 2.5pF (differentia l), TA = -40°C to +85°C, (Typical values are at VCC = +3.3V, TA = +25ºC) unless otherwise
specified; 1, 2, 3, 10
Notes:
1. Parameters are guaranteed by design and characterization.
2. CL includes probe and jig capacitance.
3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 2.4V, f = 100MHz, 50% duty cycle, RO = 50Ω,
tR ≤ 1ns, tF ≤ 1ns (0 to 100%).
4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|.
5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device.
6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other.
7. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and tempera-
ture ranges.
8. fMAX signal generator conditions: VOL = 0, VOH = 2.4V, 50% duty cycle, RO = 50Ω,
tR ≤ 1ns, tF ≤ 1ns (0 to 100%).
9. Transmitter output criteria: duty cycle = 45 to 55%, VOD ³ 250mV.
10. For optimum performance matched circuits should be used.
Table 4. Switching Characteristics
Parameter Symbol Conditions Min Typ Max Unit
Differential Propagation Delay,
High-to-Low tPHLD Figure 20 on page 11 and
Figure 21 on page 12 1.1 1.268 1.5 ns
Differential Propagation Delay,
Low-to-High tPLHD Figure 20 on page 11 and
Figure 21 on page 12 1.1 1.267 1.5 ns
Differential Pulse Skew 4 tSKD1 Figure 20 on page 11 and
Figure 21 on page 12 90 200 ps
Differential Channel-to-Channel Skew 5tSKD2 Figure 20 on page 11 and
Figure 21 on page 12 110 250 ps
Differ ential Part-to-Part Skew 6tSKD3 Figure 20 on page 11 and
Figure 21 on page 12 750 ps
Differ ential Part-to-Part Skew 7tSKD4 Figure 20 on page 11 and
Figure 21 on page 12 900 ps
Rise Time tTLH Figure 20 on page 11 and
Figure 21 on page 12 200 356 800 ps
Fall Time tTHL Figure 20 on page 11 and
Figure 21 on page 12 200 352 800 ps
Maximum Operating Frequency 8, 9 fMAX 400 MHz
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AS1154
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
VCC = +3.3V, CLOAD = 2.5pF (differential), Freq = 20MHz, Tamb = +25ºC, unless otherwise specified;
Figure 3. Transition Time vs. VCC Figure 4. Transition Time vs. Temperature
Figure 5. Differential Pulse Skew vs. VCC Figure 6. Pulse Skew vs. Temperature
Figure 7. Differential Propagation Delay vs. VCC; Figure 8. Differential Propagation Delay vs. Temp.
0
50
100
150
200
250
300
350
-50 -30 -10 10 30 50 70 90
Ambient T emperature( ° C)
T r ans ition T im e (ps ) .
230
240
250
260
270
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age( V)
T r ans ition T im e (ps ) .
tTLH
tTHL
tTLH
tTHL
0
5
10
15
20
25
30
35
-50-30-101030507090
Ambient Temperat ur e( °C)
Pulse Skew (ps) .
0
10
20
30
40
50
60
70
80
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age( V)
Dif fer ential Puls e S k ew (ps) .
0.95
0.97
0.99
1.01
1.03
1.05
3 3.1 3.2 3.3 3.4 3.5 3.6
S upply Voltage(V)
Dif f. Pr opagat ion Delay ( ns) .
tPLHD
tPHLD
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
-50 -30 -10 10 30 50 70 90
Ambient T emperature( ° C)
Dif f. Pr opagat ion Delay ( ns) .
tPLHD
tPHLD
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AS1154
Datasheet - Typical Operating Characteristics
Figure 9. Differential Output Voltage vs. VCC Figure 10. Differential Output Voltage vs. Frequency
Figure 11. Offset Voltage vs. VCC Figure 12. Offset Voltage vs. Frequency
Figure 13. Output Voltage vs. VCC; Figure 14. Output Voltage vs. Load Resistance;
325
330
335
340
345
350
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
Dif ferential O utput V oltage (m V ) .
0
50
100
150
200
250
300
350
0 50 100 150 200 250 300 350 400
Frequency ( MHz)
Dif ferential O utput V oltage (m V ) .
1.1
1.15
1.2
1.25
1.3
1.35
0 50 100 150 200 250
F r equenc y (MHz)
O ff s et Voltage ( V) .
1.2
1.21
1.22
1.23
1.24
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
O ff s et Voltage ( V) .
0.95
1.05
1.15
1.25
1.35
1.45
80 90 100 110 120 130 140 150
Load Resist anc e ( )
Out put Voltage (V) .
0.95
1.05
1.15
1.25
1.35
1.45
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
Out put Voltage (V) .
VOUT+
VOUT-
Ω
VOUT+
VOUT-
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AS1154
Datasheet - Typical Operating Characteristics
Figure 15. ICC vs. VCC Figure 16. ICC vs. Tem perature;
Figure 17. Short Circuit Current vs. VCC Figure 18. ICC vs. Frequency
8
9
10
11
12
13
-50-30-101030507090
Ambient Temperat ur e( °C)
Supply Cur r ent ( m A ) .
9
9.4
9.8
10.2
10.6
11
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
Supply Cur r ent ( m A ) .
Freq = 100MHz
Freq = 20MHz
0
2
4
6
8
10
12
14
16
18
0 50 100 150 200 250
Freque nc y ( MHz)
Supply Current (mA) .
3.6
3.65
3.7
3.75
3.8
3.85
3.9
3 3.1 3.2 3.3 3.4 3.5 3.6
S upply Voltage(V)
O utput S hor t Circ uit Cur r ent ( m A )
.
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AS1154
Datasheet - Detailed Description
8 Detailed Description
LVDS Interface
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined
by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication stan-
dards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise.
The AS1154 is an 800Mbps dual differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This devic e
accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals.
The AS1154 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less
ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are short-circuit cur-
rent limited, and enter a high-impedance state when the device is not powered or is disabled.
The current-steering architecture of the AS1154 requires a resistive load to terminate the signal and complete the transmission loop. Because
the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of
an LVDS receiver (AS1157, AS1158). Logic states are determined by the direction of current flow through the termination resistor.
With a typical 3.7mA output current, the AS1154 produces an output voltage of 370mV when driving a 100Ω load.
Termination
Because the AS1154 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors
should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resist or.
The AS1154 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may
range between 90 and132Ω, depending on the characteristic impedance of the transmission medium.
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AS1154
Datasheet - Applications
9 Applications
Figure 19. Typical Application Circuit
Power-Supply Bypassing
To by pass V CC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the
smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1154.
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other.
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices.
Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a
constant distance between the differential traces to avoid irregularities in differential impedance.
Avoid 90° turns (use two 45° turns).
Minimize the number of vias to further prevent impedance irregularities.
Table 5. Function Table
Input Output
INxOUTx+OUTx-
LL H
HHL
0.8V < VINx < 2.0V Undetermined Undetermined
LVDS
Signals
107Ω
LVTTL/LVCMOS
Data Inputs LVTTL/LVCMOS
Data Outputs
100Ω Shielded Twisted Cable or Microstrip PC Board Traces
Tx Rx
AS1157
LVDS Receiver
AS1154
0.1µF0.001µF
+3.3V
0.1µF0.001µF
+3.3V
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AS1154
Datasheet - Applications
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches.
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Bal-
anced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling.
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Driver Propagation Delay and Transition Time Waveforms
tTHLtTLH
tPLHD tPHLD
0 Diffe r ential
1.5V
20%
80%
0
20%
OUTx-
OUTx+
INx
VOH
VOL
0
1.5V
VDIFF = (VOUTx+) - (VOUTx-)
80%
00
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AS1154
Datasheet - Package Drawings and Markings
10 Package Drawings and Markings
Figure 23. 8-pi n SOIC Marking
Table 6. Packaging Code AYWWRZZ
YY WW RZZ
last two digits of the current year manufacturing week plant identifier free choice / traceability code
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AS1154
Datasheet - Ordering Information
11 Ordering Information
The devices are available as the standard products shown in Table 7.
Note: All products are RoHS compliant.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributo
Table 7. Ordering Information
Ordering Code Marking Description Delivery Form Package
AS1154-BSOU AS1154 Dual LVDS Driver Tubes 8-pin SOIC
AS1154-BSOT AS1154 Dual LVDS Driver Tape and Reel 8-pin SOIC
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AS1154
Datasheet
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All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
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any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
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