MR25H128APDF - EVERSPIN TECHNOLOGIES

MR25H128A

INTRODUCTION

The MR25H128A is a 128Kbit magnetoresistive random access memory (MRAM) device orga-

nized as 16,384 words of 8 bits. The MR25H128A oers serial EEPROM and serial

Flash compatible read/write timing with no write delays and unlimited read/write

endurance.

Unlike other serial memories, both reads and writes can occur randomly in memo-

ry with no delay between writes. The MR25H128A is the ideal memory solution for applications that must

store and retrieve data and programs quickly using a small number of I/O pins.

The MR25H128A is available in a 5 mm x 6 mm 8-pin DFN Small Flag package compatible with serial EE-

PROM, Flash, and FeRAM products.

The MR25H128A provides highly reliable data storage over a wide range of temperatures. The product is

oered with industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) and AEC-Q100 Grade 3

(-40° to +85 °C) operating temperature range options.

128Kb Serial SPI MRAM

FEATURES

• No write delays

• Unlimited write endurance

• Data retention greater than 20 years

• Automatic data protection on power loss

• Block write protection

• Fast, simple SPI interface with up to 40 MHz clock rate

• 2.7 to 3.6 Volt power supply range

• Low current sleep mode

• Industrial and Automotive temperatures

• Available in 8-pin DFN Small Flag RoHS-compliant package.

• Direct replacement for serial EEPROM, Flash, FeRAM

• Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options

• Moisture Sensitivity MSL-3

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 3

2. SPI COMMUNICATIONS PROTOCOL...................................................... 4

3. ELECTRICAL SPECIFICATIONS................................................................. 10

4. TIMING SPECIFICATIONS.......................................................................... 14

5. ORDERING INFORMATION....................................................................... 17

6. MECHANICAL DRAWING.......................................................................... 18

7. REVISION HISTORY...................................................................................... 19

How to Reach Us.......................................................................................... 20

Small Flag DFN

RoHS

MR25H128A

Overview

The MR25H128A is a serial MRAM with memory array logically organized as 16Kx8 using the four pin inter-

face of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral inter-

face (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash

components allowing MRAM to replace these components in the same socket and interoperate on a shared

SPI bus. Serial MRAM oers superior write speed, unlimited endurance, low standby & operating power, and

more reliable data retention compared to available serial memory alternatives.

16KB

MRAM ARRAY

Instruction Decode

Clock Generator

Control Logic

Write Protect

HOLD

SCK

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

14 8

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

System Conguration

Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are com-

mon among devices. Each device requires CS and HOLD pins to be driven separately.

MOSI

MISO

MOSI = Master Out Slave In

MISO = Master In Slave Out

SCK

SCKSISO SCKSISO

HOLD

HOLD HOLDCS CS

SPI

Micro Controller EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2

Figure 1.2 System Conguration

MR25H128A

Signal Name Pin I/O Function Description

CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the

memory is powered down to minimize standby power, inputs are ignored

and the serial output pin is Hi-Z. Multiple serial memories can share a com-

mon set of data pins by using a unique chip select for each memory.

SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at

all other times. SO is Hi-Z when HOLD is low. Data transitions on the data

output occur on the falling edge of SCK.

WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status

VSS 4 Supply Ground Power supply ground pin.

SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the

rising edge of SCK and ignored at other times. SI can be tied to SO to create

a single bidirectional data bus if desired.

SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 40

MHz to shift commands, address, and data into the memory. Inputs are

captured on the rising edge of clock. Data outputs from the MRAM occur

on the falling edge of clock. The serial MRAM supports both SPI Mode 0

(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is

normally low. In Mode 3, the clock is normally high. Memory operation is

static so the clock can be stopped at any time.

HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task.

When HOLD is low, the current operation is suspended. The device will

ignore transitions on the CS and SCK when HOLD is low. All transitions of

HOLD must occur while CS is low.

VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts.

HOLD

SCK

Table 1.1 Pin Functions

Figure 1.3 Pin Diagrams (Top View)

8-Pin DFN Small Flag Package

DEVICE PIN ASSIGNMENT

MR25H128A

2. SPI COMMUNICATIONS PROTOCOL

Instruction Description Binary Code Hex Code Address Bytes Data Bytes

WREN Write Enable 0000 0110 06h 0 0

WRDI Write Disable 0000 0100 04h 0 0

RDSR Read Status Register 0000 0101 05h 0 1

WRSR Write Status Register 0000 0001 01h 0 1

READ Read Data Bytes 0000 0011 03h 2 1 to ∞

WRITE Write Data Bytes 0000 0010 02h 2 1 to ∞

SLEEP Enter Sleep Mode 1011 1001 B9h 0 0

WAKE Exit Sleep Mode 1010 1011 ABh 0 0

Table 2.1 Command Codes

Status Register and Block Write Protection

The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 dene the mem-

ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)

is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable

writes to status register bits. The fast writing speed of MR25H128A does not require write status bits. The

state of bits 6,5,4, and 0 can be user modied and do not aect memory operation. All bits in the status

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care

Table 2.2 Status Register Bit Assignments

MR25H128A can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).

For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling

edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The

memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS

falls.

All memory transactions start when CS is brought low to the memory. The rst byte is a command code. De-

pending upon the command, subsequent bytes of address are input. Data is either input or output. There

is only one command performed per CS active period. CS must go inactive before another command can

be accepted. To ensure proper part operation according to specications, it is necessary to terminate each

access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or

aborted accesses.

MR25H128A

SPI COMMUNICATIONS PROTOCOL

WEL SRWD WP Protected Blocks Unprotected Blocks Status

0 X X Protected Protected Protected

1 0 X Protected Writable Writable

1 1 Low Protected Writable Protected

1 1 High Protected Writable Writable

Table 2.4 Memory Protection Modes

Status Register Memory Contents

BP1 BP0 Protected Area Unprotected Area

0 0 None All Memory

0 1 Upper Quarter Lower Three-Quarters

1 0 Upper Half Lower Half

1 1 All None

Table 2.3 Block Memory Write Protection

Read Status Register (RDSR)

The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can

be read at any time to check the status of write enable latch bit, status register write protect bit, and block

write protect bits. For MR25H128A, the write in progress bit (bit 0) is not written by the memory because

there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and

then driving CS high.

Figure 2.1 RDSR

When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,

BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,

status register bits BP0 and BP1 can be modied. Once SRWD is set to 1, WP must be high to modify SRWD,

BP0 and BP1.

SCK

Status Register Out

High Impedance High Z

Mode 3

Mode 0

10 2 3 4 5 6 7 0 1 2 3 4 5 6 7

00000101

MSB

76543210

MR25H128A

SPI COMMUNICATIONS PROTOCOL

Write Status Register (WRSR)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. The

WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a

WREN command while pin WP and bit SRWD correspond to values that make the status register writable

as seen in table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0

upon power cycling.

Write Enable (WREN)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The

WEL bit must be set prior to writing in the status register or the memory. The WREN command is entered

by driving CS low, sending the command code, and then driving CS high.

Write Disable (WRDI)

The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to

status register or memory. The WRDI command is entered by driving CS low, sending the command code,

and then driving CS high.

The WEL bit is reset to 0 on power-up or completion of WRDI.

Figure 2.3 WRDI

Figure 2.2 WREN

SCK

Instruction (06h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000110

SCK

Instruction (04h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000100

MR25H128A

SPI COMMUNICATIONS PROTOCOL

Figure 2.4 WRSR

SCK

Status Register In

High Impedance

Mode 3

Mode 0

Instruction (01h)

0000000176543210

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

The WRSR command is entered by driving CS low, sending the command code and status register write

data byte, and then driving CS high.

Read Data Bytes (READ)

The Read Data Bytes (READ) command allows data bytes to be read starting at an address specied by the

16-bit address. Only address bits 0-13 are decoded by the memory. The data bytes are read out sequen-

tially from memory until the read operation is terminated by bringing CS high The entire memory can be

read in a single command. The address counter will roll over to 0000h when the address reaches the top of

memory.

The READ command is entered by driving CS low and sending the command code. The memory drives the

read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-

nated by bring CS high.

Figure 2.5 READ

SCK

16-Bit Address

High Impedance

Instruction (03h)

Data Out 1 Data Out 2

00000011X3

765432107

210

MSB

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

X13

X = Don’t Care

MR25H128A

SPI COMMUNICATIONS PROTOCOL

Write Data Bytes (WRITE)

The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specied by

the 16-bit address. Only address bits 0-13 are decoded by the memory. The data bytes are written sequen-

tially in memory until the write operation is terminated by bringing CS high. The entire memory can be

written in a single command. The address counter will roll over to 0000h when the address reaches the top

of memory.

Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock

speed without write delays or data polling. Back to back WRITE commands to any random location in mem-

ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or

block organized memory making it ideal for both program and data storage.

The WRITE command is entered by driving CS low, sending the command code, and then sequential write

data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS

high.

Figure 2.6 WRITE

SCK

16-Bit Address

High Impedance

Instruction (02h)

00000010X321076543210

MSB MSB

012345678910 20 21 22 23 24 25 26 27 28 29 30 31

X13

Data Byte 1

X = Don’t Care

SCK

Data Byte 3

High Impedance

Data Byte NData Byte 2

34 210 76543210

MSB

76543210765

MSB

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3

Mode 0

MR25H128A

SPI COMMUNICATIONS PROTOCOL

Enter Sleep Mode (SLEEP)

The Enter Sleep Mode (SLEEP) command turns o all MRAM power regulators in order to reduce the overall

chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com-

mand code, and then driving CS high. The standby current is achieved after time, tDP

. If power is removed

when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid

command following SLEEP mode entry is a WAKE command.

Exit Sleep Mode (WAKE)

The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.

The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.

The memory returns to standby mode after tRDP

. The CS pin must remain high until the tRDP period is over.

Figure 2.7 SLEEP

Figure 2.8 WAKE

SCK

Standby CurrentActive Current

Mode 3

Mode 0

Sleep Mode Current

Instruction (B9h)

10111001

01234567

SCK

Sleep Mode Current

Mode 3

Mode 0

Standby Current

Instruction (ABh)

10101 011

01234567

RDP

MR25H128A

3. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric elds; however, it is advised that normal precautions be taken to avoid application of any voltage

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken to avoid

application of any magnetic eld more intense than the eld intensity specied in the maximum ratings.

Symbol Parameter Conditions Value Unit

VDD Supply voltage 2All -0.5 to 4.0 V

VIN Voltage on any pin 2All -0.5 to VDD + 0.5 V

IOUT Output current per pin All ±20 mA

PDPackage power dissipation 3All 0.600 W

TBIAS Temperature under bias

Industrial -45 to 95 °C

AEC-Q100 Grade 3 -45 to 95 °C

AEC-Q100 Grade 1 -45 to 135 °C

Tstg Storage Temperature All -55 to 150 °C

TLead

Lead temperature during solder (3

minute max) All 260 °C

Hmax_write Maximum magnetic eld (Write) During Write 12,000 A/m

Hmax_read

Maximum magnetic eld (Read or

Standby)

During Read or

Standby 12,000 A/m

1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic elds could aect device reliability.

2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more

than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited

to less than 20mA.

3 Power dissipation capability depends on package characteristics and use environment.

Table 3.1 Absolute Maximum Ratings 1

MR25H128A

Symbol Parameter Grade Min Typical Max Unit

VDD Power supply voltage

Industrial 2.7 - 3.6 V

AEC-Q100 Grade 3 2.7 - 3.6

AEC-Q100 Grade1 3.0 - 3.6 V

VIH Input high voltage All 2.2 - VDD + 0.3 V

VIL Input low voltage All -0.5 - 0.8 V

TATemperature under bias

Industrial -40 - 85 °C

AEC-Q100 Grade 3 -40 - 85 °C

AEC-Q100 Grade 1 1-40 - 125 °C

Note 1: AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2

years out of 20-year life.)

Table 3.2 Operating Conditions

ELECTRICAL SPECIFICATIONS

Symbol Parameter Conditions Min Typical Max Unit

ILI Input leakage current All - - ±1 μA

ILO Output leakage current All - - ±1 μA

VOL Output low voltage

IOL = +4 mA - - 0.4 V

IOL = +100 μA - - VSS + 0.2v V

VOH Output high voltage

IOH = -4 mA 2.4 - - V

IOH = -100 μA VDD - 0.2 - - V

Table 3.3 DC Characteristics

Table 3.4 Power Supply Characteristics

Symbol Parameter Conditions Typical Max Unit

IDDR Active Read Current

@ 1 MHz 2.5 3 mA

@ 40 MHz 6 10 mA

IDDW Active Write Current

@ 1 MHz 8 13 mA

@ 40 MHz 23 27 mA

ISB Standby Current CS High 190 115 μA

IZZ Standby Sleep Mode Current CS High 7 30 μA

1 ISB current is specied with CS high and the SPI bus inactive.

MR25H128A

4. TIMING SPECIFICATIONS

Table 4.1 Capacitance1

Symbol Parameter Typical Max Unit

CIn Control input capacitance - 6 pF

CI/O Input/Output capacitance - 8 pF

1 ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Table 4.2 AC Measurement Conditions

Figure 4.1 Output Load for Impedance Parameter Measurements

Figure 4.2 Output Load for all Other Parameter Measurements

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 4.1

Output load for all other timing parameters See Figure 4.2

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

30 pF

3.3 V

MR25H128A

TIMING SPECIFICATIONS

Power-Up Timing

The MR25H128A is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time

from the time when VDD (min) is reached until the rst CS low to allow internal voltage references to become

stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up

sequence.

Symbol Parameter Min Typical Max Unit

VWI Write Inhibit Voltage 2.2 - 2.7 V

tPU Startup Time 400 - - μs

Table 4.3 Power-Up

VDD

(max)

VDD(min)

tPU

Time

Normal Operation

Chip Selection not allowed

Reset state

of the

device

Figure 4.3 Power-Up Timing

MR25H128A

TIMING SPECIFICATIONS

Over the Operating Temperature Range and CL= 30 pF

Symbol Parameter Min Max Unit

fSCK SCK Clock Frequency 0 40 MHz

tRI Input Rise Time - 50 ns

tRF Input Fall Time - 50 ns

tWH SCK High Time 11 - ns

tWL SCK Low Time 11 - ns

Synchronous Data Timing (See gure 4.4)

tCS CS High Time 40 - ns

tCSS CS Setup Time 10 - ns

tCSH CS Hold Time 10 - ns

tSU Data In Setup Time 5 - ns

tHData In Hold Time 5 - ns

tVOutput Valid

Industrial Grade

VDD = 2.7 to 3.6v. 0 10 ns

VDD = 3.0 to 3.6v. 0 9 ns

AEC Q-100 Grade 3

VDD = 2.7 to 3.6v. 0 10 ns

VDD = 3.0 to 3.6v. 0 9 ns

AEC Q-100 Grade 1 VDD = 3.0 to 3.6v. 0 10 ns

Table continues next page.

Table 4.4 AC Timing Parameters

Synchronous Data Timing

MR25H128A

Symbol Parameter Min Max Unit

tHO Output Hold Time 0 - ns

HOLD Timing (See gure 4.5)

tHD HOLD Setup Time 10 - ns

tCD HOLD Hold Time 10 - ns

tLZ HOLD to Output Low Impedance - 20 ns

tHZ HOLD to Output High Impedance - 20 ns

Other Timing Specications

tWPS WP Setup To CS Low 5 - ns

tWPH WP Hold From CS High 5 - ns

tDP Sleep Mode Entry Time 3 - μs

tRDP Sleep Mode Exit Time 400 - μs

tDIS Output Disable Time 12 - ns

Table 4.4 (Cont’d) AC Timing Parameters

MR25H128A

TIMING SPECIFICATIONS

Figure 4.5 HOLD Timing

SCK

HOLD

Figure 4.4 Synchronous Data Timing

MR25H128A

5. ORDERING INFORMATION

Figure 5.1 Product Part Number Decoder Table

Grade Temperature Package Shipping Container Order Part Number

Industrial -40 to +85 C 8-DFN Small Flag Trays MR25H128ACDF

Tape and Reel MR25H128ACDFR

AEC-Q100 Grade 3 -40 to +85 C 8-DFN Small Flag Trays MR25H128APDF

Tape and Reel MR25H128APDFR

AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag Trays MR25H128AMDF

Tape and Reel MR25H128AMDFR

Table 5.1 Ordering Part Numbers

Memory Speed Voltage Density Revision Temp Package Ship Grade

Example Ordering Part Number MR 25 H 128 A P DF R ES

Everspin MRAM MR

40 MHz 25

3.0v. Vdd H

128 Kb 128

Revision A A

Industrial -40 to 85°C C

AEC-Q100 Grade 3 -40 to 85°C P

AEC-Q100 Grade 1 -40 to 125°C M

8-pin DFN Small Flag DF

Tray Blank

Tape and Reel R

Mass Producon Blank

Customer Samples CS

Engineering Samples ES

MR25H128A

Detail A

Pin 1 Index

0.10 C2X

NOTE:

1. All dimensions are in mm. Angles in degrees.

2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be

within 0.08 mm.

3. Refer to JEDEC MO-229-E

6. MECHANICAL DRAWINGS

Figure 6.1 DFN Small Flag Package

Exposed metal Pad. Do not con-

nect anything except VSS

Dimension A B C D E F G H I J K L M

Max 5.10 6.10 0.90 - 0.45 0.05 1.54 0.70 2.10 2.10 0.210 - -

Nominal 5.00 6.00 0.85 1.27

BSC 0.40 - 1.40 0.60 2.00 2.00 0.200 C0.45 R0.20

Min 4.90 5.90 0.80 - 0.35 0.00 1.26 0.50 1.90 1.90 0.190 - -

MR25H128A

Revision Date Description of Change

0.1 June 1, 2015 First Draft

0.2 September 29, 2015

Corrected address range and timing diagrams for READ and WRITE to

Address bits 0-13. Added Grade 3 parameters to Table 4.4 and refor-

matted the Table.

0.3 November 2, 2015 Revised Part Number Decoder Table.

1.0 October 1, 2016

Production release. Removed all Preliminary status statements and

indications. Added nominal values to DFN package outline dimen-

sions table.

1.1 February 1, 2017 Added tHO and tV relationship to Synchronous Data Timing

1.2 March 23, 2018 Updated the Contact Us table

7. REVISION HISTORY

MR25H128A

Everspin Technologies, Inc.

Information in this document is provided solely to enable system and

software implementers to use Everspin Technologies products. There are

no express or implied licenses granted hereunder to design or fabricate any

integrated circuit or circuits based on the information in this document.

Everspin Technologies reserves the right to make changes without further

notice to any products herein. Everspin makes no warranty, representation

or guarantee regarding the suitability of its products for any particular pur-

pose, nor does Everspin Technologies assume any liability arising out of the

application or use of any product or circuit, and specically disclaims any and

all liability, including without limitation consequential or incidental dam-

ages. “Typical” parameters, which may be provided in Everspin Technologies

data sheets and/or specications can and do vary in dierent applications

and actual performance may vary over time. All operating parameters

including “Typicals” must be validated for each customer application by

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Filename:

EST02895_MR25H128A_Datasheet_Rev 1.2 032318