ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
1
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
GENERAL DESCRIPTION
The ICS85311 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V ECL/
LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input levels.The
ICS85311 is characterized to operate from either a 2.5V
or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85311 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
FEATURES
•2 differential 2.5V/3.3V L VPECL / ECL outputs
•1 CLK, nCLK input pair
•CLK, nCLK pair can accept the following differential input
levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL
•Maximum output frequency up to 1GHz
•Translates any single ended input signal to 3.3V L VPECL
levels with resistor bias on nCLK input
•Output skew: 15ps (maximum)
•Part-to-part skew: 100ps (maximum)
•Propagation delay: 1.4ns (maximum)
•L VPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V , VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V , V EE = -2.375V to -3.465V
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85311
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
,&6
Vcc
CLK
nCLK
VEE
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
2
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
2,10Qn,0QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
5V
EE
rewoP.dnuorgottcennoC.nipylppusevitageN
6KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
7KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
8V
CC
rewoP.V3.3rov5.2ottcennoC.nipylppusevitisoP
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnIKLCn,KLC4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
3
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VCC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, VO-0.5V to VCC + 0.5V
Package Thermal Impedance, θJA 112°C/W
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP531.33.3564.3V
I
EE
tnerruCylppuSrewoP 52Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
CC
V=
NI
V564.3=051Aµ
KLCnV
CC
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCV
CC
V,V564.3=
NI
V0=5-Aµ
KLCnV
CC
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP51.03.1V
V
RMC
;egatloVtupnIedoMnommoC 2,1ETON V
EE
5.0+V
CC
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.VsiKLCn,KLCrofgatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP573.25.2526.2V
I
EE
tnerruCylppuSrewoP 52Am
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
4
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
TABLE 4F. AC CHARACTERISTICS, VCC = 3.3V±5%, VCC = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuOmumixaM 1zHG
t
DP
1ETON;yaleDnoitagaporP IJzHG19.04.1sn
t
)o(ks4,2ETON;wekStuptuO 51sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 001sp
t
R
emiTesiRtuptuOzHM05@%08ot%02003007sp
t
F
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO8425%
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA .tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON .stniopssorclaitnereffidtuptuoehttaderusaeM segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna .stniopssorclaitnereffidehtta .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
CC
V=
NI
V526.2=051Aµ
KLCnV
CC
V=
NI
V526.2=5Aµ
I
LI
tnerruCwoLtupnI KLCV
CC
V,V526.2=
NI
V0=5-Aµ
KLCnV
CC
V,V526.2=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP51.03.1V
V
RMC
;egatloVtupnIedoMnommoC 2,1ETON V
EE
5.0+V
CC
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.VsiKLCn,KLCrofgatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
TABLE 3E. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCC = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
0.1-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 56.09.0V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
5
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
PARAMETER MEASUREMENT INFORMATION
FIGURE 1A - 3.3V O UTPUT LOAD TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VCC = 2.0V
VCC
VEE = -1.3V ± 0.135V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VCC = 2.0V
VCC
VEE = -0.5V ± 0.125V
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
6
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
FIGURE 4 - PART-TO-PART SKEW
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
FIGURE 3 - OUTPUT SKEW
tsk(o)
Qx
nQx
Qy
nQy
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
VCMR
Cross Points
VPP
CLK
nCLK
VEE
VCC
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
7
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
FIGURE 7 - odc & tPERIOD
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
CLK, Qx
nCLK, nQx
FIGURE 6 - PROPAGATION DELAY
tPD
CLK
nCLK
Q0 - Q1
nQ0 - nQ1
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
Clock Inputs
and Outputs
20%
80%
20%
80%
tRtF
VSWING
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
8
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
R2
1K
VCC
CLK_IN +
-
R1
1K
C1
0.1uF
V_REF
R2
1K
VCC
CLK_IN +
-
R1
1K
C1
0.1uF
V_REF
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
9
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85311.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation of the ICS85311 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core) = VCC * IEE = 3.465V * 25mA = 86.6mW
•Power (outputs) = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 x 30.2mW = 60.4mW
Total Power (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the
reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
In order to determine if the junction temperature is below 125°C, the appropriate junction-to-ambient thermal
resistance θJA
must be used
in conjunction with the total power dissipation. Assuming a moderate air low of 200 linear
feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per the table below:
Tj = θJA * Pd_total + TA where Pd_total is the total power dissipation of the device and TA is the ambient
temperature. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.147W * 103.3°C/W = 85.2°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are
loaded, supply voltage, air flow, and the type of board (single layer or multi-layer).
Thermal Resistance q
JA
for 8-pin SOIC, Forced Convection
q
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
10
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 9.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load,
and a termination voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
 (V
CC
- 2V))/R
L
]*(V
CC
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
 (V
CC
- 2V))/R
L
]*(V
CC
- V
OL_MAX
)
•For logic high , V
OUT
= V
OH_MAX
= V
CC
 1.0V
Using V
CC
= 3.465, this results in V
OH_MAX
= 2.465V
•For logic low , V
OUT
= V
OL_MAX
= V
CC
 1.7V
Using V
CC
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Q1
VOUT
VCC
RL
50
VCC - 2V
Figure 9 - LVPECL Driver Circuit and Termination
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
11
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85311 is: 225
TABLE 5. θJAVS. AIR FLOW TABLE
q
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
12
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
PACKAGE OUTLINE - M SUFFIX
D
EH
SEATING
PLANE
e
A
N
A1
A2
B
C
L
α
4
1
5
8
hx45˚
.10 (.004)
TABLE 6. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliMsehcnI
NUMINIMMUMIXAMNUMINIMMUMIXAM
N8
A53.157.1235.08860.0
1A01.052.00400.08900.0
2A52.105.12940.00950.0
B33.015.0310.0020.0
C91.052.05700.08900.0
D08.400.50981.08691.0
E08.300.47941.04751.0
eCISAB72.1CISAB050.0
H08.502.64822.00442.0
h52.005.0010.0020.0
L04.072.1610.0050.0
α°0°8°0°8
ICS85311AM www.icst.com/products/hiperclocks.html REV. A JUNE 29, 2001
13
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
TABLE 7. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
MA11358SCIMA11358SCICIOSdael8ebutrep69C°07otC°0
TMA11358SCIMA11358SCIleeRdnaepaTnoCIOSdael80052C°07otC°0