fax id: 5408 CY7C455 CY7C456 CY7C457 CYPRESS 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features High-speed, low-power, first-in first-out (FIFO) memories 512 x 18 (CY7C455) 1,024 x 18 (CY7C456) 2,048 x 18 (CY7C457) 0.65 micron CMOS for optimum speed/power ieee 83-MHz operation (12 ns read/write cycle ime) Low power Ioc=90 mA Fully asynchronous and simultaneous read and write operation Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags TTL compatible Retransmit function Parity generation/checking Output Enable (OE) pins Independent read and write enabie pins Center power and ground pins for reduced noise Supports free-running 50% duty cycle clock inputs * Width Expansion Capability * Depth Expansion Capability * 52-pin PLCC and 52-pin PQFP . . Functional Description The CY7C455, CY7C456, and CY7C457 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cas- caded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data buff- ering needs, including high-speed data acquisition, multipro- cessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). Do- 17 INPUT REGISTER Logic Block Diagram Pin Configurations ckKW ENW | i FLAG/PARITY PROGRAM Dis WRITE REGISTER Dis CONTROL | Dis Dig tortor b.. FLAG : LOGIC FORT FAM WF ss a * ENF 1024x 18 , WRITE AEAD OE 2048x 1B fH POINTER POINTER Or /PG2/PES = Qs aR RESET Tom Ou FURT otf Ree Se THREE-STATE READ OUTPUT REGISTER coo RETRANSMIT LOGIC or Qo - 7, Qg/PGUPET . c455-1 0455-2 Og. 1g. CUT/PG2/PES cKR ENR For the most recent information, visit the Cypress web site at www.cypress.com 2-306CYPRESS CY7C455 CY7C456 CY7C457 Pin Configurations (continued) PQFP Top View SAARSERSSE AAS fy a noceoradan 1 HERE Aad al EL a 82 51 50.49 48 47 46 45.44 43.42.4140 | De tO 39 f= Dig Dyce 3g rc On Do 3 x! 4 ENW ooo 5 cKW. 6 7C455 FCT 7 70456 EF CI 8 7O487 ROPAFEI 9 oo 10 ame 2g Ez Qy7/PG2/PES Cort 12 2g LT Oe Os I 13 o7 EO Os {14 + 0455-3 Functional Description (continued) In the standalone and width expansion configurations, a LOW on the retransmit (FIT) input causes the FIFOs to retransmit the data. Read enable (ENR) and the write enable (ENW) must both be HIGH during the retransmit, and then ENF is used to access the data.When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). In addition, the CY7C455, CY7C456, and CY7C457 have an output enable pin (OE). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are achievable in the standalone configuration, and up to 83.3 MHz is achievable when FIFOs are cascaded far depth expan- sion. Depth expansion is possible using the cascade input (XT), cas- cade output (XO), and First Load (FL) pins. The XO pin is connected to the XT pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device, The FT pin of the first device is tied to Vgs. The CY7C455, CY7C-456, and CY7C457 provide three status pins. These pins are decoded to determine one of six states: Empty, Almost Empty, Less than or Equal to Half Fuil, Greater than Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full flag (PAFE) shares the XO pin on the CY7C455, CY7C456, and CY7C457, This flag is valid in the standaione and width-expansion configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO when it will be activated. The flags are synchronous, i.e., they change state relative to either the read clock (CKR) or the write clock (CKW). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the CKR. The flags denoting Half Full, Almost Full, and Full states are updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. This time is typically equal to approximately one cycle time. The CY7C455/6/7 uses center power and ground for reduced noise. All configurations are fabricated using an advanced 0.65u CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 2-307CY7C455 CY7C456 Fr CY70457 CYPRESS = Selection Guide / 7C455/6/7~12 7C458/6/7-14 7C455/6/7-20 7C455/6/7-30 Maximum Frequency (MHz) 83.3 714 50 333 Maximum Cascadable Frequency 83.3 714 50 333 Maximum Access Time (ns) 9 10 15 20 Minimum Cycle Time (ns) 12 14 20 30 Minimum Clock HIGH Time (ns) 5 6.5 9 12 Minimum Clock LOW Time (ns) 5 65 9 12 Minimum Data or Enabie Set-Up (ns) 4 5 6 7 Minimum Data or Enable Hold (ns) 0 0 0 0 Maximum Flag Delay (ns) 9 10 15 20 Meximum Current | Commercial 160 160 140 120 (mA) Industrial 180 180 160 140 Selection Guide (continued) CY7C455 CY7C456 CY7C457 Density 512 x 18 1,024 x 18 2,048 x 18 DE, Depth Cascadable Yes Yes Yes Package 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP 52-Pin PLCC/PQFP Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature wo... we Ambient Temperature with Power Applied... vee Supply Voltage to Ground Potential. aevtterne ee DC Voltage Applied to Outputs in High Z State .. DC Input Voltage .. . . Output Current into Outputs (Low) . Static Discharge Voltage .... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current >200 mA 65C to +150C Operating Range o Ambient we 55C to +125C Range Temperature Vec ~0.5V to +7.0V Commercial C to +70C 5V + 10% - -08Vt0+7.0y _| Industrial!) 40C to +85C 5V + 10% Note. - B.0V to +7 OV 1 T, is the instant on case temperature . 20 mA 2-308CY7C455 CY7C456 CY7C457 9 CYPRESS Pin Definitions Signa! Name | VO Description Do 47 | | Data inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ ;7) into the FIFO's memory. If MR is asserted at the rising edge of CKW, data is written into the FIFOs programming register. Dg, 47 are ignored if the device is configured for parity generation. Qo-7 | Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Qo _ 7. Qg 16 Qg _ 4g) Out of the FIFOs memory. If MA is active at the rising edge of CKR, data is read from the programming register. Q)/PGI/PET | | Function varies according to mode: Q47/PG2/PE2 Parity disabled - same function as Qg_ 7 and Qg _ 16 Parity enabied, generation parity generation bit (PG,) Parity enabled, check Parity Error Flag (PE,) ENW { | Enabie Write: Enables the CKW input (for both non-program and program modes). ENR | | Enable Read: Enables the CKR input (for both non-program and program modes). CKW 1 | Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and Full flag states. When MR is asserted, CKW writes data into the program register. CKR | | Read Ciock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and Almost Empty flag states. When MR is asserted, CKR reads data out of the program register. AF O | Half Full Flag: Synchronized to CKW. E/F O | Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW. PAFE/KO O | Dual-Mode Pin: Not Cascaded programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR. Cascaded ~ expansion out signal, connected to XT of next device. xT | | Expansion-In Pin: Not Cascaded XT is tied to Vgg. Cascaded - expansion input, connected to XO of previous device. FUR | | First Load/Retransmit Pin: Cascaded ~ the first device in the daisy chain will have FT tied to Vgg; aif other devices will have FT tied to Voc (Figure 1). Not Cascaded ~ tied to Veg. Retransmit function is also available in standalone mode by strobing AT. WR | | Master Reset: Resets device to empty condition. Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or jess locations from Full/Empty. Programming Mode: Data present on Dg . 940, or 11 and Di5.17 is written into the programmable register on the rising edge of CKW. Program register contents appear on Qg.9 10, or 11 aNd Qy5.17 after the rising edge of CKR. OE 1 | Output Enable for Qo _ 7, Qg ~ 46. Qg/PGI/PET and Q,7/PG2/PE@ pins. 2-309CY7C455 CY7C456 ae CY7CAS7 Electrical Characteristics Over the Operating Range TC455/6/7~ | 7C455/6/7 | 7C455/6/7~ | 7C455/6/7 12 14 20 30 Parameter Description Test Conditions Min. | Max | Min. | Max | Min. | Max | Min. | Max | Unit Vou Output HIGH Vec#Min., loy=-2.0mA | 2.4 24 2.4 2.4 Vv Voltage Vo. Output LOW Voc = Min., Io, = 8.0 mA 0.4 0.4 0.4 04 |v Voltage Vil Input HIGH Voltage 22 | Veo | 22 1 Voc] 2.2 | Voc | 22 | Veo] Vv Vv, FI Input LOW Voltage -05/ 08 |-05/ 08 |-05| 08/05] 08] Vv lx Input Leakage Voc = Max. ~10 | +10 | -10 | +10 | -10 | +10 | -10 | +10 | WA Current log! Output Short Voc = Max., Voyr = GND | -90 -30 90 -90 mA Circuit Current loz. Output OFF, High Z | OF = Vin, Vgg < Vo < Veg | -10 | +10 | -10 | +10 | -10 | +10 | -10 | #10 | pA lozH Current lec) Operating Current | Voc = Max., Com 160 160 140 120 | mA lour = O mA ind 180 180 160 140 | mA loca! Operating Current | Vog = Max., Com! 30 90 90 90 | mA lour = 0 mA ind 100 400 100 400 | mA igpl Standby Current | Vco = Max., Com! 40 40 40 40 | mA lour = mA ind 40 40 40 40 | mA Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f= 1 MHz, 10 pF Court Output Capacitance Voc = 5.0V 12 pF AC Test Loads and Waveforms: 9: 10. 11. 12] Ri 5000 5V o_ ALL INPUT PULSES QUTPU CL R2 I 3332 INCLUDING-+- = te JIG AND ~ - SCOPE 0455-4 455-5 Equivalent to: THEVENIN EQUIVALENT 2002, OUTPUT o1y 0 2 z oe tes: The Vj, and V; specifications apply for all inputs except XT. The XT pin is not a TTL input. It is connected to either XO of the previous device or Vgs. Test no more than one output at a time for not more than one second. input signals switch from OV to 3V with a rise/fall time of tess than 3 ns, clocks and clock enables switch at maximum frequency (fyax). while data inputs switch at fyyay/2. Outputs are unloaded. Input signals switch trom OV to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz. while the data inputs switch at 10 MHz. 5 Outputs are unloaded, 6. All input signals are connected to Vec. All outputs are unloaded. Read and write clocks switch at maximum frequency (fax). 7. Tested initially and after any design or process changes that may affect these parameters. 8. Cy = 30 pF for ali AC parameters except for toyz. 9. OC, = 5 pF for toyz. 10. All AC measurements are referenced to 1.5V except tog, torz, aNd toyz. 11. tog and to, z are measured at + 100 mV from the steady state. 12. toyz is measured at +500 mV from Vo, and 500 mV from Voy. RON 2-310CY7C455 CY7C456 J CYPRESS CY7C457 Switching Characteristics Over the Operating Range!'! 7C455/6/7 | 7C455/6/7 | 7C455/6/7~ | 7C455/6/7- 12 14 20 30 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tcexw Write Clock Cycle 12 14 20 30 ns tcKA Read Clock Cycle 12 14 20 30 ns toxH Clock HIGH 5 6.5 9 12 ns toKe Clock LOW 5 6.5 9 12 ns ta Data Access Time 9 10 15 20 ns tou Previous Output Data Hold After Read HIGH 0 0 0 0 ns ten Previous Flag Hold After Read/Write HIGH 9 0 0 9 ns tsp Data Set-Up 4 5 6 7 ns typ Data Hold 0 0 0 0 ns i) tsen Enable Set-Up 4 5 6 7 ns 7 tuen Enable Hold 0 0 0 0 ns toe DE LOW to Output Data Valid 9 10 15 20 | ns to.z 41] OE LOW to Output Data in Low Z 0 0 0 0 ns tonz "4 | OE HIGH to Output Data in High Z 9 10 15 20 | ns tpg ; Read HIGH to Parity Generation 9 10 15 20 | ns ipE Read HIGH to Parity Error Flag 9 10 15 20 ns ten Flag Delay 9 10 15 20 ns tsxew1'! | Opposite Clock After Clock 0 0 0 0 ons tsxewsl Opposite Clock Before Clock 12 14 20 30 ns tpmr Master Reset Pulse Width (MR LOW) 14 14 20 30 ns tscma Last Valid Clock LOW Set-Up to MR LOW 0 0 0 0 ns toumrR Data Hald From MR LOW 0 0 0 0 ns turA Master Reset Recovery 12 14 20 30 ns (MR HIGH Set-Up to First Enabled Write/Read) iMRF MA HIGH to Flags Valid 12 14 20 30 | ns tama MR HIGH to Data Outputs LOW 12 14 20 30 | ns tsmap Program ModeMA LOW Set-Up 12 14 20 30 ns tumeap Program Mode-MR LOW Hold 9 10 15 20 ns tetp Program ModeWrite HIGH to Read HIGH 12 14 20 30 ns tap Program ModeData Access Time 12 14 20 30 ns touP Program Mode-Data Hold Time from MR HIGH | 0 0 0 0 ns tear Retransmit Pulse Width 12 14 20 30 ions tata Retransmit Recovery Time 12 14 20 30 Las | 13. Test conditions assume signal transition time of 3 ns or tess, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms and capacitance as in notes 8 and 9, unless otherwise specified. 14. Atany given temperature ang voltage condition, to, 2 is greater than toy for any given device. 15. tgxews Is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purpeses of flag update). If the opposite clock occurs less than tsxew: after the clock, the decision ot whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; L.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Aimost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; Le., CKW is the clock tor the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Aimost Empty flags. 16. tgxewe is the minimum time an opposite clock can occur before 4 clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). It tne opposite clack occurs less than tgxpy2 before the clock, the decision of whether or nat to include the opposite clock in the current clock cycle is arbitrary. See Note 15 for definition of clock and apposite clock. 2-311CY7C455 CY7C456 CY7C457 Switching Waveforms Write Clock Timing Diagram toxH cKW ENABLED WRITE tsp typ VALID DATA IN teen DISABLED WRITE Do 17 ENW tFH E/F,PAFE,AF 0455-6 Read Clock Timing Diagram lox toxR OKA ENABLED READ ta ton DISABLED AEAD Qo-17 PREVIOUS WORD NEW WORD tsen teH E/F,PAFE try feo 0485-7 MasterReset (Default with Free-RunningClocks) Timing Diagram 7, 18, 19, 20) tpmr MR iscmA CKW CKR toHMR Qo- 47 VALID DATA ALL DATA OUTPUTS LOW E/F,PAFE AF 0455-8 Notes: 17. To only perform reset (no programming} the following criteria must be met: ENW or CKW must be inactive while MA is LOW. . To only perform reset (no programming), the following criteria must be met: ENA or CKR must be inactive while MR is LOW. . All data outputs (Qy . 7) go LOW as a result of the rising edge of WR after tama: In this example, Qo . 7 will remain valid until toypsn if either the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it. 2-312CY7C455 CY7C456 SY cypress CY7C457 Switching Waveforms (continued) Master Reset (Programming Mode) Timing Diagram!"? 2! ft tsMRP ; tHMRP - MR .~ 7 / toKH } - tMAR CKW if opcom MW wre ENW Low fmm tetp >| tsp typ Gt 5 7 V7 bore KS OK KK OOK OK TKR tsmpP tuMRP CKR / PaM a ee ENF Low i tcKH toHMR tt tap touP | tampa J Qo-17 VALID DATA PGM wor xxKK KOR ot RATA c455-9 Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram (19, 20] f isaap y . tuuae K be tow a Z toxH ANG, fou RSA tseN tHEN [s tte > XX DK toe KKK KKK en U/ | DK 18 DR DIOK 080 XOX TO tawr toHmMR Kt~ tap touP ALL DATA Qo -17 VALID DATA x PGM WORD K outputs iow 455-10 2-313Read to Empty Timing Diagram COUNT CKR CKW CYPRESS Switching Waveforms (continued) {21, 24, 25] CaN _ ENABLED READ 1 (NO CHANGE) LATENT CYCLE CY7C455 CY7C456 CY7C457 R pit ENABLED READ UPDATE READ Ke tgkew, ete tskewe > wt WRITE tow it teD bt teD fet tery 0455-12 Read to Empty Timing Diagram with Free-RunningClocks COUNT CKR ENR __ [21, 22, 23, 24] LATENT CYCLE R AG UPOATE READ ft tsxew1 >e._ tskeEW2 ] cKW f w\ ON Koen we ENABLED WRITE ws we ENW \ / AF HIGH Me teD he teD Ie te EF LOW PAFE cABS-11 Notes: 21. Count is the number of words in the FIFO. 22. The FIFO is assumed to be programmed with P>0 (.e., PAFE does not transition at Empty or Full}. 23, R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tgxewe before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tsx_ewe before A4, R4 includes W3 in the flag update. 24. CKR is clock and CKW is apposite clock. mp 25. 3 updates the flag to the ty state by asserting E/F. Because W1 occurs greater than tgxew, after R3, R3 does not recognize Wi when updating flag status. But because Wt occurs tgxews before R4, R4 inciudes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is important to note that R4 is a jatent cycle: i.e.. it only updates the flag status regardless of the state of ENR. It does not change the count or the FIFOs data outputs. 2-314CY7C455 CY7C456 SBP Cyprsss CY7C457 Switching Waveforms (continued) Read to Almost Empty Timing Diagram with Free-Running Clocks" 24, 261 COUNT 17 18 17 s SPN _ oi _7 7 ENABLED READ ENR PN iskew2 Ww3 CaN N08 we WRITE WRITE ENW PX AF HIGH EF HIGH pe ten ft tep re teD PAFE 455-14 Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks (1, 24, 26, 27, 28) 18 (no change} FLAG UPDATE CYCL RF HIGH tit HIGH ee te he tery pe trp PAFE 0465-13 Notes: 26. The FIFO in this example is assumed to be prograrnmed ta its default flag values. Almast Eropty is 16 words fromm Empty; Almost Full is 16 iocations from Full. 27. RA only updates the flag status. it does not affect the count because Sta is HIGH. . 28. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 A18; two enabled writes: W2, W3) before 2 read (R4) can update flags to the Less Than Half Full state. 2-315CY7C455 CY7C456 CYPRESS CY7C457 Switching Waveforms (continued) Write to Half Full Timing Diagram with Free-Running Clocks?" 29, 30. 31] 1024 1025 4024 4023 1024 COUNT [Bt a (613! gi St 512) (256) (2571 266 255 bos CKW ws W4 / ENABLED WRITE ENW \ it IskEW: pe tsxew2 } CKR Ri Ra Ra RS R6 ENABLED READ Ne be Ep te] R2 ENABLED READ e ten e te AF EF HIGH PAFE HIGH 0455-15. Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks!" 2% 9. 9". 32. 33] 1023 4511] [255] (no change) 1024 COUNT (Beet cKw V7 em lt ISKEW? R4 AS Re R7 Ne be ten Me ten we tery FF E/F HIGH PAFE nich c455~16 Notes: 29. CKW is clock and CKR is opposite clock. 30. Count = 1,025 indicates Half Full for the CY7C446 and CY7C466., Count = 513 indicates Haif Full for the CY7C447 and CY7C457. Count = 257 indicates Halt Fuil for the CY7C044B and CY7C458. 3t. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the HF to be true (LOW). 32. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH. 33. When making the transition from Half Full to Lees Than Half Full, the count must decrease by two (1.e., 1,025 A1,023; two enabled reads: R2 and R3) before a write (W4) can update flags to less than Half Full. 2-316CY7C455 CY7C456 CYPRESS CY7TCA57 Switching Waveforms (continued) Write to Almost Full Timing Diagram (21,26, 20, 24, 36) 2031 2030 2031 (1017; 2032 2033 COUNT [1017] [1016] [495] 1 [496] {497} (495) 1494) koe ~~ 7 k- = = = 4 bm mm me ey 20360 {10716] i 2031 [1017] 2032 [1018] (494) (496) (agg)! 4 L CKW / FLAG UPDATE redennn ENW Low | ft tskewt | iskew2 CKR Rt Yr \ /| Lse\ 7] ENABLED, READ a ENR Low AF Low CA55-18 Write to Almost Full Timing Diagram with Free-RunningClocks "7 2) 2031 2030 2031 COUNT (1047) [1016} (1017) {495] 1494] [495] CKW ENABLED WRITE e- tskewt t Iskew2 >Y CKR Rg RS AS RE ENABLED ENABLED AREAS READ HF Low EF HIGH jet te ae we te i# ten PAFE cA85-17 Notes: 34. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than tgxew, after W2, W2 does not recognize R1 when updating flag status. W3 includes A2 in the flag update because R2 occurs greater than tgxeywe before W3. Note that W3 does not have to be enabled to update flags. 35. The dashed lines show W@ as a flag update write rather than an enabled write because ENW is HIGH. 2-317CY7C455 CY7C456 W CYPRESS CY7C457 Switching Waveforms (continued) Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks (2+. 26, 29} 2030 [1016] [494] (no change) FLAG UPDATE CYCLI 2031 COUNT [1017] [485] w7 ENABLED WRITE tgkew2 >} HIG = tro trp le tep PAFE cA465-19 Write to Full Flag Timing Diagram with Free-Running Clocks?" 29. 96) 2047 2048 2048 2047 LATENT CYCLE 2048 2048 COUNT 1023) (1024) [1024] i023] a {1024} [1024] 514} 1512] (512] sti} {512} 1512] CKW wi we wa Ws We. /)\ ENABLED IGNORED FLAG ENABLED IGNORED WRITE WRITE UPDATE WRITE WRITE > tskewe WRITE ew LXXXXXPOOO pe tgkew, pee-. tgxewe wn ENABLED READ nt ENR \ / AF Low he te tcp le trp EF PAFE Low 455-20 Note: 36. W2 is ignored because the FIFO is full (count = 2,048 [1,024] [512}). It is important to note that W3 is also ignored because R3, the first enabled read after full, occurs less than tgxew2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tsxewe before W4, W4 inctudes R3 in the flag update. 2-318CY7C455 CY7C456 CYPRESS CY7C457 Switching Waveforms (continued) Even Parity Generation Timing Diagram': 38] CKR ENABLED READ DISABLED READ tpg PE,, (PEp) Qo-7 PREVIOUS WORD: NEW WORD: (Qg .. +6) EVEN NUMBER OF 1s ODD NUMBER OF 1s EXO AXXXXY XRR]OOOXL 0455-24 Even Parity Generation Timing Diagram (87. 89] CKR 7 ENABLED READ DISABLED READ PE,, (PE2) lq tpg (pi) BENNER XOXOXO eveN NRF 1 POON BREOY RAOOOK cAS5-22 Notes: 37. In this exampie, the FIFO is assumed to be programmed to generate even parity. The Q,_, word is shown. The example is similar for the Qg.,_ word. 38. if Q,_7 new word a.so has an even number of 1s, then PG1 stays LOW. 39. 1 Q,_7 new word aise has odd number of ts, then PG1 stays HIGH 2-319CY7C455 CY7C456 CY7C457 CYPRESS Switching Waveforms (continued) (40] Even Parity Checking CKW WRITE M WRITE M+1 WRITE M+2 . es LL tpg | tee /L. PE; at (PE) AF oo KOKO HEEB OK URE BEE OX HS a 0455-23 Output Enable Timing" 7! CKR READ M41 ENR LOW OE KR tonz tog | Qo. 17 WORD MS WORD Get touz 0455-24 Retransmit Timing 44) FURT N tert yr tevR RENWEN EMF, AF, PAFE KOQOODO OOD DDO 42X5-21 Notes: 40. in this example, the FIFO is assumed to be programmed to check for even parity. The Qo.7 word is shown. 41. This example assumes that the time from the CKR rising edge to valid word M+1 > t,. The Qo.7 word is shown. 42. itENR was HIGH around the rising edge of CKR {i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1. 43. Clocks are free running in this case. 44. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tarp. 2-320CYPRESS CY7C455 CY7C456 CY7C457 Architecture The CY7C455/6/7 consists of an array of 12, 1024, or 2048 words of 18 bits each (implemented by a dual-port array of SRAM ceils), a read pointer, a write pointer, contro! signals (CKR, CKW, ENR, ENW, and MR), and flags (AF, E/F, PAFE). The CY7C455/6/7 also includes the control signals GE, FL, XI, and XO for depth expansion. Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the Empty condition signified by E/F and PAFE being LOW and HF being HIGH. All data outputs (Qg.47) go low at the rising edge of MR. in order for the FIFO to reset to its default state, a falling edge must occur on MA and the user must not read or write while MR is LOW (unless ENR and ENW are HIGH or unless the device is being programmed), Upon compietion of the master reset cy- cle, all data outputs will go LOW tay after MR is deasserted. All flags are guaranteed to be valid tune after MR is taken HIGH. FIFO Operation When the ENW signal is active (LOW), data present on the Do..17 pins is written into the FIFO on each rising edge of the CKW signal. Similarly, when the ENF signal is active, data in the FIFO memory will be presented on the Qo_17 outputs. New data will be presented on each rising edge of CKR while ENF is active. ENR must set up tgex, before CKR for it to be a valid tead. ENW must occur igen before CKW for it to be a valid write. An output enabte (OE) pin is provided to three-state the Qo_47 outputs when OE is asserted. When OE is enabled (low), data in the output register will be available to the Qp_,7 outputs after tog. If devices are cascaded, the OF function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Qg_47 outputs even after additional reads occur. Programming The CY7C455/6/7 is programmed during a master reset cycle. it MR and ENW are LOW, a rising edge on CKW will write the Do 7.8.09 and Dy5_17 inputs into the programming ragister!**!, MR must be set up a minimum of tgypp before the program write rising edge and held tyyrp after the program write falling edge. The user has the ability to also perform a program read during the master reset cycle. This will occur at the rising edge of CKR when MR and ENR are asserted. The program read rust be performed a minimum of terp after a program write, and the program word will be available tap after the read oc- curs. If a program write does not occur, a program read may occur a minimum of tgypp after MR is asserted. This will read the default program value. Notes: When free-running clocks are tied to CKW and CKR, program- ming can still occur during a master reset cycle with the adher- ence to a few additional timing parameters. The enabie pins must be set-up tgey before the rising edge of CKW or CKR. Hold times of tuen must also be met for ENW and ENR. Data present on Do_g during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags will become active. See Table 7 for a description of the six possible FIFO states. P in Table 7 refers to the decimal equivalent of the binary number represented by Do_+ g or g- Programming options for the CY7C455/6/7 are listed in Table 4. The programmable PAFE function on the CY7C455/6/7 is only valid when not cascaded. If the user elects not to program the FIFOs flags, the default is as follows: the Almost Empty con- dition (Almost Full condition) is activated when the FIFO con- tains 16 or iess words (empty locations). Parity is programmed with the Dys_17 bits. See Table 4 for a summary of the various parity programming options. Data present on Dye 47 during a program write will determine whether the FIFO will generate or check even/odd parity for the data present on Do.7 and Dg_1, thereafter. If the user elects not to program the FIFO, the parity function is disabled. Flag Operation and parity are described in greater detail in subse- quent sections. Flag Operation The CY7C455/6/7 provides three status pins when not cas- caded. The three pins, E/F, PAFE, and HF, allow decoding of six FIFO states (Table 1). PAFE is not available when the CY7C455/6/7 is cascaded for depth expansion. All flags are synchronous, meaning that the change of states is relative to one of the clocks (CKR or CKW, as appropriate) [46] The Emp- ty and Almost Empty flag states are exclusively updated by each rising edge of the read clock (CKF). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while ENR=LOW) causes the flag pins to output a state that represents Empty. The Half Full, Almost Full, and Full flag states are updated exclusively by the write clock (CKW). For example, if the CY7C457 contains 2,047 words (2,048 words indicate Full for the C7C457), the next write (rising edge of CKW while ENW=LOW) causes the flag pins to output a state that is decoded as Full. Since the flags denoting emptiness (Empty, Aimost Empty) are only updated by CKR and the flags signifying fuliness (Half Full, Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware that if a boundary (Empty, Almost Empty, Half Full, Almost Fuil, or Full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e., CKW does not affect Empty or Almost Empty), a flag update cycle is necessary to represent the FIFOs new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty and Almost Empty flags; CKR is the opposite clock for Haff Full, Almost Full, and Full flags). Until a proper flag update cycle is executed, the syn- chronous flags will not show the new state of the FIFO. 45, CKW will write Dg_g into the programming register. CKR will read Do_, during a programming register read. 46, The synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to. 2-321CY7C455 CY7C456 CY7C457 CYPRESS When updating flags, the FIFO must make a decision as to whether or not the opposite clack was recognized when a clock updates the flag. For example (when updating the Empty flag), if @ write occurs at least tgxeyw: after a read, the write is guar- anteed not to be included when CKA updates the flag. If a write occurs at least tgxewe before a read, the write is guaranteed to be included when CKR updates flag. If a write occurs within toxew1 after or tsxewe before CKR, then the decision of wheth- er or not to include the write when the flag is updated by CKR is arbitrary, The update cycle for non-boundary flags (Almost Emply, Half Full, Almost Full) is different from that used to update the boundary flags (Empty, Full). Both operations are described below. Boundary and Non-Boundary Flags Boundary Flags (Empty) The Empty flag is synchronized to the CKR signal (i.e., the Empty flag can only be updated by a clock pulse on the CKR pin). An empty FIFO that is written to will be described with an Empty flag state until a rising edge is presented to the CKR pin. When making the transition from Empty to Almost Empty (or Empty to Less than or Equal to Half Full), a clock cycle on CKR is necessary to update the flags to the current state. In such a state (flags showing Empty even though data has been written to the FIFO), two read clock cycles are required to read data out of the FIFO. The first read serves only to update the flags to the Almost Ernpty or Less than or Equal to Half Full state, while the second read outputs the data. This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in FIFO). it simply deasserts the Empty flag. The flag is updated regardiess of the ENR state. Therefore, the update occurs even when ENA is deasserted (HIGH), so that a valid read is not necessary to update the flags to correctly describe the FIFO. In this example, the write must occur at least tgxewe before the flag update cycle in order for the FIFO to guarantee that the write will be included in the count when CKR updates the flags. When a free-running clock is connected to CKR, the flag is updated each cycle. Table 2 shows an example of a sequence of operations that update the Empty flag. Truth Tabtel*] Table 1. E/F | PAFE | HF Words in FIFO Boundary Flags (Full) The Full flag is synchronized to the CKW signal (i.e., the Full flag can only be updated by a clock pulse on the CKW pin). A full FIFO that is read will be described with a Full flag until a rising edge is presented to the CKW pin. When making the transition from Full to Almost Full (or Full to Greater Than Half Full), a clock cycle on CKW is necessary to update the flags to the current state, In such a state (flags showing Full even through data has been read from the FIFO), two write cycles are required to write data into the FIFO, The first write serves only to update the flags to the Almost Full or Greater Than Half Full state, while the second write inputs the data. This first write cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in the FIFO). It simply deasserts the Full flag. The flag is updated regardless of the ENW state. Therefore, the update occurs even when ENW is deasserted (HIGH), so that a valid write is not necessary to update the flags to correctly describe the FIFO. In this example, the read must occur at least tgxewe before the flag update cycle in order for the FIFO to quarantee that the read will be included in the count when CKW updates the flags. When a free-running clock is connected to CKW, the flag updates each cycle. Full flag operation is similar to the Empty flag operation described in Table 2. Non-Boundary Flags (Aimost Empty, Half Full, Almost Full) The CY7C455/6/7 features programmable Almost Empty and Almost Full flags. Each flag can be programmed a specific distance from the corresponding boundary flags (Empty or Full). The flags can be programmed to be activated at the Empty or Full boundary, or at any distance from the Empty/Full boundary. When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAFE flag will be asserted signifying that the FIFO is Almost Empty. When the FIFO is within that same number of empty locations from being Full, tha PAFE will also be asserted signifying that the FIFO is Almost Full. The HF flag is decoded to distinguish the states. The default distance from where PAFE becomes active to the boundary (Empty, Full) is 16 words/ocations. The Almost Full and Almost Empty flags can be programmed so that they are only active at Full and Empty boundaries. However, the oper- ation will remain consistent with the non-boundary flag opera- tion that is discussed below. Words in FIFO Words in FIFO 47. Pis the decimal value af the binary number represented by Dp_7 for the CY7C455, Dp_, for the CY7C456, and Do_s for the CY7C487. P = 0 signifies that the Almost Empty state = Empty state. 2-322CY7C455 CY7C456 IorpRE gs CY7C457 Table 2. Empty Flag (Boundary Flag) Operation Example Status Before Operation Status After Operation Number Number Current of Next of State of Words State Words FIFO E/F | AFE | RF | inFIFO | Operation | of FIFO | E/F | AFE | HF | in FIFO Comments Empty 0 0 1 0 Write Empty 0 0 1 1 Write (ENW = 0) Empty 0 0 1 1 Write Empty 0 0 1 2 Write (ENW = 0) Empty 0 0 1 2 Read AE 1 0 1 2 Flag Update (ENR = X) AE 1 0 1 2 Read AE 1 0 1 1 Read (ENR = 0} AE 1 0 1 1 Read Empty 0 0 1 0 Read (transition from (ENR = 0) Almost Empty to Empty) Empty 0 0 4 0 Write Empty 0 0 1 4 Write (ENR = 0) Empty 1 0 1 1 Read AE 1 0 1 1 Fiag Update (ENR = X) AE 1 0 1 1 Read Empty 0 0 1 0 Read (transition from (ENR = 0) Almost Empty to Empty) Almost Empty is only updated by CKR while Half Full and Ai- most Full are updated by CKW. Non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO status. For example, if the FIFO just reaches the Greater than Half Full state, and then two words are read from the FIFO, a write clock (CKW) will be required to update the flags to the Less than Half Full state. However, unlike the boundary flag latent cycle, the state of the enable pin (ENW in this case) affects the operation. Therefore, set-up and hold times for the enable pins must be met (tgeny and ty_en)- lf the enable pin is active during the flag update cycle, the count and data are updated in addition to PAFE and HF. If the enable pin is not asserted during the flag update cycle, only the flags are updated. Table 3 shows an example of a se- quence of operations that update the Almost Empty and Al- most Full flags The CY7C455/6/7 also features even or odd parity checking and generation. Dy5_,7 are used during a program write to describe the parity option desired. Table 4 summarizes pro- grammable parity options. If the user elects not to program the device, then parity is disabled. Parity information is pro- vided on two multi-mode output pins (Q/PG1/PET and Q47/PG2/PE2). The three possible modes are described in the tollowing paragraphs. Programmable Parity Parity Disabied (Q,/Q,7 mode) When parity is disabled (or the user does not program parity option) the FIFO stores all 18 bits present on Do..17 inputs internally and will output all 18 bits on Qg_47. Parity Generate (PG mode) This mode is used to generate either even or odd parity (as programmed) from Do.7 and Dg 4. Og and D,;7 inputs are ignored. The parity bits are stored internally as Dg and Dy7, and during a subsequent read will be available on the PG1 and PG2 pins along with the data words from which the parity was generated (Qo_7 and Qg_;g). For example, if par- ity generate is set to ODD and the Do inputs have an EVEN number of 1s, PG1 will be HIGH. Parity Check (PE mode) If the FIFO is programmed for parity checking, it will compare the parity of Do_g and Do_,7 with the program register. For example, Dg and D7 will be set according to the result of the parity check on each word. When these words are later read, PE, and PE, will reflect the result of the parity check. Ifa parity error occurs in Dp_g, Dg will be set LOW internally. When this word is later read, PE, will be LOW. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tarp after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read point- er is incremented until it is equal to the write pointer. Flags are gov- erned by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after ac- tivation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Width Expansion Modes During width expansion all flags (programmable and nonpro- gramrnable) are available. These FIFOs can be expanded in 2-323CY7C455 CY7C456 CY7C457 SF cyeress width to provide word width greater than 18 in increments of 18. During width expansion mode ail control line inputs are common. When the FIFO is being read near the Empty (Full) boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the Not Empty (Not Full) condition to insure that the next read (write) will per- form the same operation on all devices. Checking all sets of flags is critical so that data is not read from the FIFOs staggered by one clock cycle. This situation could occur when the first write to an empty FIFO and a read are very clase together. If the read occurs less than tsxewe after the first write to two wicth-expanded devices, A and B, device A may go Almast Empty {read recognized as flag update) while device B stays Empty (read ignored). This occurs be- cause a read can be either recognized or ignored if it oc- curs within tgxewe cf a write. The next read cycle outputs the first half of the first word on device A while device 8 updates its flags to Almost Empty. Subsequent reads will continue to output staggered data assuming more data has been written to FIFOs. Depth Expansion Mode The CY7C-455/6/7 can operate up to 83.3 MHz when cascad- ed. Depth expansion is accomplished by connecting expan- sion out (XO) of the first device to expansion in (XT) of the next device, with XO of the last device connected to XT of the first device. The first device has its first load pin (FL) CK DATA IN Do- 7 tied to Vgg while all ather devices must have this pin tied to Voc. The first device will be the first to be write and read enabled after a master reset. Proper operation also requires that all cascaded devices have common CKW, CKR, ENW, ENR, Dg_47, Qg-17, and MR pins. When cascaded, one device at a time will be read enabled so as to avoid bus contention. By asserting XO when ap- propriate, the currently enabled FIFO alerts the next FIFO that it should be enabled. The next rising edge on CKR puts Qo_17 outputs of the first device into a high-impedance state. This occurs regardless of the state of ENR or the next FIFOs Empty flag. Therefore, if the next FIFO is empty or undergoing a latent cycle, the Qo_;7 bus will be in a high-im- pedance state until the next device receives its first read, which brings ifs data to the Qo_+7 bus. Program Write/Read of Cascaded Devices Programming of cascaded FIFOs is the same as for a single device. Because the controls of the FIFQs are in parallel when cascaded, they ail get programmed the same. During program mode, only parity is programmed since Almost Full and Almost Empty flags are not available when CY7C455/6/7 is cascaded. Only the first device (FIFO with FL=LOW)} will output its pro- gram register contents on Qo_7 during a program read. Qpo.17 of all other devices will remain in a high-impedance state to avoid bus contention. CATA OUT Qo- sz Figure 1. Depth Expansion with CY7C455/6/7 2-324CY7C455 CY7C456 j CYPRESS CY7C457 Table 3, Almost Empty Flag (Non-Boundary Flag) Operation Example!*2! Status Before Operation Status After Operation Number Number Current of Words Next State ofwords State of FIFO | E/F | AFE | RAF | in FIFO | Operation | of FIFO | E/F | PAFE | AF | in FIFO Comments AE 1 0 1 32 Write AE 1 0 1 33 Write (ENW = 0) AE 1 0 1 33 Write AE 1 0 1 34 Write (ENW = 0) AE 1 0 1 34 Read <HF 1 1 1 33 Fiag Update and (ENF = 0) Read <HF 1 1 1 33 Read <HF 1 1 1 33 ignored Read (ENR = 1) (ENR = 1) <HF 1 1 1 33 Read AE i 4 0 1 32 Read (transition from (ENR = 0) L <HF to AE) - Table 4, Programmable Parity Options 017 016 D15 Condition 0 xX x Parity disabled. 1 0 0 Generate even parity on PG output pin. 1 0 1 Generate odd parity on PG output pin. 1 4 0 Check for even parity. Indicate error on PE output pin. 1 1 1 Check for odd parity. indicate error on PE output pin. Note: 48. Applies te CY7C455/6/7 operations when devices are programmed so thal Almost Empty becomes active when the FIFO contains 32 or fewer words. 2-325CY7C455 CY7C456 CY7C457 CYPRESS Ordering Information $12x18 Clocked FIFO Speed Package Package Operating (ns) Ordering Code Name Type Range 12 CY7C455~12C J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C455-12NC N52 52-Pin Plastic Quad Flatpack CY7C455-12u1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 14 CY7C455-14JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C45514NC N52 52-Pin Plastic Quad Flatpack CY7C455-14J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 20 CY7C455-20JC J69 52-Lead Plastic Leaded Chip Carrier | Commerciai CY7C455-20NC N52 52-Pin Plastic Quad Flatpack CY7C456-20J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 30 CY7C455-30JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C455-30NC N52 52-Pin Piastic Quad Fiatpack CY7C455~30J! J69 52-Lead Plastic Leaded Chip Carrier | Industrial 1Kx18 Clocked FIFO Speed Package Package Operating (ns) Ordering Code Name Type Range 12 CY7C45612U0 J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C45612NC N52 2-Pin Plastic Quad Flatpack CY7C456-12u1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 14 CY7C45614C J9 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C45614NC N52 52-Pin Plastic Quad Fiatpack CY7C456-14J1 J69 52-Lead Plastic Leaded Chip Carrier | Industriai 20 CY7C45620JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C456~20NC N52 52-Pin Plastic Quad Flatpack CY7C456-20Ji J69 52-Lead Plastic Leaded Chip Carrier | Industrial 30 CY7C456-30J5C J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY?7C456-30NG N52 52-Pin Plastic Quad Fiatpack | CY7C456~30U1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 2Kx18 Clocked FIFO Speed Package Package Operating (ns) Ordering Code Name Type Range 12 CY7C457-12JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C457-12NC N52 52-Pin Plastic Quad Flatpack CY7C457-12J1 J69 2-Lead Plastic Leaded Chip Carrier | Industriaf 14 CY7C457-145C J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C457-14NC N52 52-Pin Plastic Quad Flatpack CY7C457-14J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 20 CY7C457~20JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C457-20NC N52 52-Pin Plastic Quad Fiatpack CY7C457-20J1 J69 52-Lead Plastic Leaded Chip Carrier | Industrial 30 CY7C457-30JC J69 52-Lead Plastic Leaded Chip Carrier | Commercial CY7C457-30NC N52 52-Pin Plastic Quad Fiatpack CY7C457-30JI J9 52-Lead Plastic Leaded Chip Carrier | Industrial Document #: 38-00211-E 2-326