MMA6222AKEG
Rev 0, 12/2009
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Analog Dual Axis Micromachined
Accelerometer
The MMA62XXAKEG series of dual axis (X and Y) silicon capacitive,
micromachined accelerometers features a full digital signal processing for
filtering, trim and data formatting. It has be en optimized for analog output and
offers an over-damped transducer.
Features
• Available in ±20/20g, ±50/50g, or ±100/100g versions. Additional g-ranges
between 20 and 100g may be available upon request
• Full-scale range is independently specified for each axis
• 400 Hz, 4 Pole, 16 µs sample time, additional filter options are available
• Ratiometric analog voltage output
• Capture/hold input for system-wide synchronization support
• 3.3 or 5 V single supply operation
• On-chip temperature sensor and voltage regulator
• Internal self-test
• Minimal external component requirements
• Pb-free 20-pin SOIC package
• Qualified AEC-Q100, Rev. F Grade 2 (-40°C/ +105°C)
Typical Applicat ions
• Crash Detection (Airbag)
• Impact and vibration monitoring
• Shock detection
ORDERING INFORMATION
Device Name X-Axis g-Level Y-Axis g-Level Temperature Range Package Packaging
MMA6222AEG 20 20 -40 to +105°C 475A-02 Tubes
MMA6222AEGR2 20 20 -40 to +105°C 475A-02 Tape & Reel
MMA6222AKEG* 20 20 -40 to +105°C 475A-02 Tubes
MMA6222AKEGR2* 20 20 -40 to +105°C 475A-02 Tape & Reel
MMA6255AEG 50 50 -40 to +105°C 475A-02 Tubes
MMA6255AEGR2 50 50 -40 to +105°C 475A-02 Tape & Reel
MMA6255AKEG* 50 50 -40 to +105°C 475A-02 Tubes
MMA6255AKEGR2* 50 50 -40 to +105°C 475A-02 Tape & Reel
MMA621010AEG 100 100 -40 to +105°C 475A-02 Tubes
MMA621010AEGR2 100 100 -40 to +105°C 475A-02 Tape & Reel
MMA621010AKEG* 100 100 -40 to +105°C 475A-02 Tubes
MMA621010AKEGR2* 100 100 -40 to +105°C 475A-02 Tape & Reel
*Part number sourced from a different facility.
MMA6222AKEG
MMA6255AKEG
MMA621010AKEG
2-AXIS
ACCELEROMETER
KEG SUFFIX (Pb-free)
20-LEAD SOIC
CASE 475A-02
PIN CONNECTIONS
1
16
2
15
3
14
4
13
5
12
6
11
7
20
8
19
N/C
VSS
N/C
VCC
XOUT
N/C
VPP
VSSA
CAP/HOLD
SCLK
CREGA
20-PIN SOIC PACKAGE
9
10
18
17
YOUT
ST
CREG
RESET STATUS
CREF
CREF
CREGA
N/C
N/C: NO INTERNAL CONNECTION
MMA6222AEG
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2Freescale Semiconductor
Figure 1-1 Simplified Airbag Application Diagram
1.1 INTRODUCTION
The MMA62XXKEG is trimmed to provide the most accurat e voltage representation of acceleration at XOUT and YOUT. This is
done by adjusting the signal within the DSP to compensate for errors within the digital-to-analog converters. The SPI is disabled
when the device is in normal operating mode, and dedicated ST (self-test activation) and STATUS pin functions are assigned.
1
μ
F100 nF 1
μ
F
V
CC
MMA62XXAKEG
V
CC
C
REG
C
REGA
V
SS
V
PP
/TEST
CS
SCLK
ST
STATUS
CS_A
SCLK1
I/O
Main MCU
I/O
CS_D
SCLK2
MOSI2
MISO2
CS
SCLK
DI
DO
Deployment IC
V
SSA
C
REF
100 nF
XOUT
YOUT
ADC
Safing
Sensor(s) /
Comparator
Filter
DEPLOY_EN1
DEPLOY_EN2
Note: If one axis of th e MMA62XXAKEG sensor is expected to be used as a confirmation of t he other axis, Freescale
recommends th at MMA62XXAKEG used in conjunction with an additional sens ing/safing device for each ax is.
MMA6222AKEG
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Freescale Semiconductor 3
1.2 BLOCK DIAGRAM
A block diagram illustra ting the major components of the design is shown in Figure 1-2.
Figure 1-2 MMA62XXAKEG Block Diagram
Figure 1-3 MMA62XXAKE G DSP Block Diagram
NOTE: Models of signal chain are available up on requ est
V
CC
V
SS
ST
STATUS
SCLK
RESET
SELF-TEST
C
REG
C
REF
V
PP
X
OUT
INTERFACE TEMP.
SENSOR
SD
CONVERTER
VOLTAGE
REGULATOR
g-CELL
(Y)
g-CELL
(X)
CONTROL
LOGIC
UNIT
DATA ARRAY
PROGRAMMABLE
SD
CONVERTER
CLOCK
INTERNAL
MONITOR
C
REGA
CAP/HOLD
DAC Y
OUT
Y IN
X IN
DIGITAL
Y OUT
X OUT
DSP
TEMP (SEE
FIGURE 1-2
)
OUT
CONTROL
IN STATUS
OUT
DAC
C
REF
C
REGA
V
SSA
CLOCK
PRIMARY
OSCILLATOR
REFERENCE
OSCILLATOR
SINC
FILTER
SINC
FILTER
OFFSET,
LOW-PASS
FILTER
TO X DAC
GAIN,
LINEARITY
ADJUST OUTPUT
SCALING
DSP
CONTROL
TO Y DAC
TEMP
CONTROL
IN
OFFSET
MONITOR
Y IN
X IN
OUT
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4Freescale Semiconductor
1.3 PIN FUNCTIONS
The pinout for the MMA62XXAKEG device is illustrated in Figure 1-4. Pin functions are described below . When self-test is active,
the output becomes more positive in bot h axes if ST1 is cleared , or more negative in both axes if ST1 is set.
Figure 1-4 MMA62XXAKEG Pinout
1
16
2
15
3
14
4
13
5
12
6
11
7
20
8
19
N/C
VSS
N/C
VCC
XOUT
N/C
VPP
VSSA
CAP/HOLD
SCLK
CREGA
20-PIN SOIC PACKAGE
9
10
18
17
YOUT
ST
CREG
RESET STATUS
CREF
CREF
CREGA
N/C
N/C: NO INTERNAL CONNECTION
X: 0g
Y: -1g
X: +1g
Y: 0g
X: 0g
Y: +1g
X: -1g
Y: 0g
Response to static orientation within 1g field.
TO CENTER OF
GRAVITATION FIELD
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1.4 PIN FUNCTION DESCRIPTIONS
1.4.1 VCC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best per-
formance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.
1.4.2 VSS
This pin is the power supply return no de for the digital circuitry on the MMA62XXKEG device.
1.4.3 VSSA
This pin is the power supply return node for analog circuitry on the MMA62XXAKEG device. An external bypass capacitor be-
tween this pin and VCC is required, as described in Section 1.5.
1.4.4 CREG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this
pin and VSS, as described in Section 1.5.
1.4.5 CREGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must
be connected between these pins and VSSA, as described in Section 1.5. T wo pins are provided to support redundant connection
to the printed wiring board assembly . Redundant external capacitors may be connected to these pins for maximum reliability, as
described in Section 1.5.
1.4.6 CREF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two exte rnal
filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to
support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these
pins for maximum reliability, as described in Section 1.5.
1.4.7 VPP
This pin should be tied directly to VSS.
1.4.8 SCLK
This input may be left unconnected unless it is desired to initiate device reset as described in Section 1.4.9.
1.4.9 RESET
This pin may be used to initiate a hardware reset. If RESET is held low and SCLK is held high for 512 μs, the internal reset signal
is asserted.
An internal pull-up de vice is connected to this pin.
1.4.10 STATUS
This pin provides an indicator of internal status. The STATUS output will be driven to a logic high level should any of the following
fault conditions be detected:
• Internal parity fault
• Over-temperature condition
• Internal clock frequency fault
• Device reset
• Device initialization
Immediately following device reset, ST A TUS is placed in a high impedance state for approximately 800 μs. At the end of this time,
STA TUS is driven high and a 3ms stabilization delay required by the internal circuitry begins. The ST ATUS condition may not be
cleared during the stabilization delay. Reset is reported by the device so the system can be aware of potential difficulties if unex-
pected resets occur.
Once asserted, the STATUS output will remain high until the ST pin is driven from a logic low to a logic high state. If a fault con-
dition persists, the STATUS output will be driven hig h again as soon as it is cleared.
MMA6222AEG
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1.4.11 ST
This pin performs a dual function. When driven to a logic high level, the internal self-test voltage generator is activated. A low-to-
high transition on this pin will clear the internal STATUS latch. Note that under certain fault conditions, the STATUS latch will be
immediately reset, indicating a terminal fault condition.
A diagram illustrating operation of the STATUS latch following device initialization is illustrated in Figure 1-5.
Figure 1-5 ST and STATUS Interaction
1.4.12 CAP/HOLD
When this input pin is low , acceleration data is updated by the DSP whenever a data sample becomes available. Upon a low-to-
high transition of CAP/HOLD acceleration data is frozen. Acceleration data is not updated as long as the pin remains at a logic
‘1’ level. This pin may be tied directly to VSS if the hold function is not desired.
1.4.13 XOUT, YOUT
T wo digital-to-analog converters (DACs) are provided. These converters translate output of the DSP block into voltage levels pro-
portional to the magnitude of the numerical result and ratiometric to VCC.
1.5 EXTERNAL COMPONENTS
The connections illustrated in Figure 1-1 are recommended. Careful printed wiring board layout and component placement is es-
sential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A
grounded land area with solder mask should be placed under the package for improved shielding of the device from external
effects. If a land area is not provided, no signals should be routed bene ath the package. See Figure 1-1.
ST
FAULT DETECT
SELF TEST ENABLE
VDD
D
R
Q
STATUS
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SECTION 2 PERFORMANCE SPECIFICATION
2.1 MAXIMUM RATINGS
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device con-
tains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep input and output voltages within the range VSS ≤ V ≤ VCC.
Notes:1. Verified by characterization, not tested in production.
2.2 OPERATING RANGE
The operating ratings are the limits normally expected in the application and define the range of operation.
Notes:1. Characterized at all values of VL and VH. Production test is conducted at typical voltage unless otherwise noted.
2. Parameters tested 100% at final test.
Ref Rating Symbol Value Unit
1Supply Voltage VCC -0.3 to +7 V(1)
2 CREG, CREGA, CREF VREG -0.3 to +3 V(1)
3 VPP VREG -0.3 to +11 V(1)
4SCLK, ST, CAP/HOLD VIN -0.3 to VCC + 0.3 V(1)
5STATUS (high impedance state) VIN -0.3 to VCC + 0.3 V(1)
6 XOUT, YOUT (DACEN = 0) VDAC -0.3 to VCC + 0.3 V(1)
7Current Drain per Pin Excluding VCC and VSS I10 mA (1)
8Acceleration (without hitting internal g-cell stops) gmax ±800 g(1)
9Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g(1)
10 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g(1)
11 Drop Shock (to concrete surface) hDROP 1.2 m(1)
12
13
14
Electrostatic Discharge
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model (MM)
VESD
VESD
VESD
±2000
±500
±200
V
V
V
(1)
(1)
(1)
15 Storage Temperature Range Tstg -40 to +125 °C (1)
Ref Characteristic Symbol Min Typ Max Units
16
17
Supply Voltage
Standard Operating Voltage, 3.3V operating range
Standard Operating Voltage, 5V operating range VCC
VCC
VL
+3.15
+4.75 +3.3
+5.0
VH
+3.45
+5.25 V
V(1)
(1)
18 Operating Temperature Range TA
TL
-40 ⎯TH
+105 C(2)
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2.3 ELECTRICAL CHARACTERISTICS
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified
Notes:1. Parameters tested 100% at final test.
2. Verified by characterization, not tested in production.
3. Tested at VCC = VL and VCC = VH.
4. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.
5. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected.
(#) Indicates a FSL significant parameter (CPK > 1.33).
(*) Indicates a FSL critical parameter (CPK > 1.67).
Ref Characteristic Symbol Min Typ Max Units
19 Supply Current Drain
Analog-only output configuration IDD ⎯9.0 mA (1)
20
21
22
23
24
25
26
27
28
29
30
31
Power-On Recovery Threshold (See Figure 2-1)
VCC
CREG
CREGA
CREF
Power-On Reset Threshold (See Figure 2-1)
VCC
CREG
CREGA
CREF
Hysteresis (VPOR_N - VPOR_A, See Figure 2-1)
VCC
CREG
CREGA
CREF
VPOR_N
VPOR_N
VPOR_N
VPOR_N
VPOR_A
VPOR_A
VPOR_A
VPOR_A
VHYST
VHYST
VHYST
VHYST
2.77
1.80
2.18
1.11
2.77
1.80
2.18
1.11
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
3.15
2.32
2.50
1.29
2.95
2.10
2.31
1.19
388
300
261
150
V
V
V
V
V
V
V
V
mV
mV
mV
mV
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
32 Minimum Functional Voltage (See Figure 2-1) VDACU ⎯ ⎯ 2.0 V(2)
33
34
35
Internally Regulated Voltages
CREG
CREGA (3)
CREF
*
*
VDD
V2.5
VREF
2.42
2.42
1.20
2.50
2.50
1.25
2.58
2.58
1.29
V
V
V
(1)
(1)
(1)
36
37
External Filter Capacitor (CREG, CREGA)
Value
ESR (including interconnect resistance) CREG
ESR 800
⎯1000
⎯
⎯
200 nF
mΩ(2)
(2)
38 Power Supply Coupling (4)
Analog output See Figure 2-2 (2)
39
40
41
42
43
44
Analog Sensitivity (XOUT, YOUT)
20g Range
35g Range
50g Range
100g Range
Sensitivity Erro r
TA = 25°C
40°C ≤ TA ≤ 105°C
*
*
*
*
*
*
ASENS
ASENS
ASENS
ASENS
ΔSENS
ΔSENS
⎯
⎯
⎯
⎯
-8
-8
23.40
13.40
9.37
4.68
⎯
⎯
⎯
⎯
⎯
⎯
+8
+8
mV/V/g
mV/V/g
mV/V/g
mV/V/g
%
%
(1)(5)
(1)(5)
(1)(5)
(1)(5)
(1)(5)
(1)(5)
45 Offset at 0g
Analog output (XOUT, YOUT) * AOUT 0.46 × VCC 0.5 × VCC 0.54 × VCC V(1)(5)
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2.3 ELECTRICAL CHARACTERISTICS (CONTINUED)
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified
Notes:1. Parameters tested 100% at final test.
2. Parameters tested 100% at unit probe.
3. Verified by characterization, not tested in production.
Ref Characteristic Symbol Min Typ Max Units
46
47
48
49
50
51
52
53
Output value on overrange
20g Range
35g Range
50g Range
100g Range
Output value on Underrange
20g Range
35g Range
50g Range
100g Range
gOVER
gOVER
gOVER
gOVER
gUNDER
gUNDER
gUNDER
gUNDER
+20.0
+35.0
+50.0
+100.1
-20.1
-35.1
-50.1
-100.3
+20.9
+36.6
+52.1
+104.3
-20.9
-36.6
-52.2
-104.5
+22.1
+38.7
+55.3
+110.5
-22.2
-38.8
-55.4
-110.7
g
g
g
g
g
g
g
g
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
54
Maximum acceleration without saturation of internal
circuitry
All ranges gSAT -200 —+200 g(3)
55 Nonlinearity NLOUT -1 — 1 % FSR (3)
56 Noise (1Hz-1kHz) nSD — — 1.1 mg/√Hz (3)
57
58
Positive Self Test Output Change
(XOUT, YOUT, analog)
TA = 25°C
-40°C ≤ TA ≤ 105°C ΔST
ΔST 10
10 —
—18
18 % FS
% FS (1)
(1)
59
60
61
62
Cross-Axis Sensitivity
VZX
VYX
VZY
VXY
VZX
VYX
VZY
VXY
-4
-4
-4
-4
—
—
—
—
+4
+4
+4
+4
%
%
%
%
(3)
(3)
(3)
(3)
63
64
65
66
67
68
69
DAC Characteristics (XOUT, YOUT)
Minimum Output Level, IOUT = -200 μA
Maximum Output Level, IOUT = 200 μA
Offset Error
Gain Error
Differential Nonlinearity
Integral Nonlinearity
TA = 25°C
-40°C ≤ TA ≤ 105°C
AVLOW
AVHIGH
OFST
GERR
DNL
INL
INL
—
VCC - 0.25
-0.2
-0.3
-2
-3
-3.5
—
—
—
—
—
—
0.25
—
+0.2
+0.3
+2
+3
+3.5
V
V
%FSR
%FSR
digit
digit
digit
(2)
(2)
(2)
(2)
(2)
(2)
(3)
70
71
Output High Voltage
STATUS (ILoad = -100 μA)
3.15 V ≤ (VCC - VSS) ≤ 3.45 V
4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOH
VOH
3.25
3.75 —
——
—V
V(2)
(2)
72
73
Output Low Voltage
STATUS (ILoad = 100 μA)
3.15 V ≤ (VCC - VSS) ≤ 3.45 V
4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOL
VOL
—
——
—0.4
0.4 V
V(2)
(2)
74
75
Output Loading (STATUS)
Load Resistance
Load Capacitance ZOUT
COUT
47
——
——
35 kΩ
pF (3)
(3)
MMA6222AEG
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10 Freescale Semiconductor
2.3 ELECTRICAL CHARACTERISTICS (CONTINUED)
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified
Notes:2. Parameters tested 100% at unit probe.
3. Verified by characterization, not tested in production.
Ref Characteristic Symbol Min Typ Max Units
76
77
Output Loading (XOUT, YOUT)
Load Resistance
Load Capacitance ZOUT
COUT
25
——
——
60 kΩ
pF (3)
(3)
78
79
Input High Voltage
RESET, SCLK, ST, CAP/HOLD
3.15 V ≤ (VCC - VSS) ≤ 3.45 V
4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIH
VIH
1.5
2.5 —
——
—V
V(2)
(2)
80
81
Input Low Voltage
RESET, SCLK, ST, CAP/HOLD
3.15 V ≤ (VCC - VSS) ≤ 3.45 V
4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIL
VIL
—
——
—0.85
1.0 V
V(2)
(2)
82
83
84
85
Input Current
High (at VIH)
SCLK, ST, CAP/HOLD
VPP/TEST (internal pulldown resistor)
Low (at VIL)
RESET
IIH
RIN
IIL
-30
190
30
-50
270
50
-260
350
260
μA
kΩ
μA
(2)
(2)
(2)
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Freescale Semiconductor 11
2.4 CONTROL TIMING
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified
Notes:1. Parameters tested 100% at final test.
2. Parameters tested 100% at unit probe.
3. Verified by characterization, not tested in production.
4. (*) Indicates a FSL critical parameter (CPK > 1.67). (#) Indicates a FSL significant parameter (CPK > 1.33).
7. Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency.
9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected.
10. Low-pass filter characteristics match those of other Freescale accelerometer devices. Cutoff frequencies shown are -4dB
referenced to 0 Hz response, to correspond with previous specifications.
Ref Characteristic Symbol Min Typ Max Units
DSP Low-Pass Filter (Note 9)
Cutoff frequency (Note 10)
86 Filter Option $0C, $1F fC(LPF) 380 400 420 Hz (7)
87
DSP Low-Pass Filter
Cutoff frequency (-3dB, referenced to 0 Hz)
Filter $0C, $1F fC(LPF) 335 353 371 Hz (7)
88 Filter Order
Filter $00 - $12 OLPF — 4 — 1 (7)
89 Power-On Recovery Time
Power applied to XOUT, YOUT valid tXY —— —10 ms (1)
90 Internal Oscillator Frequency fOSC 3.8 4.0 4.2 MHz (1)
91 Clock Monitor Threshold fMON 3.6 —4.4 MHz (7)
92 Chip Select to Internal Reset (See Figure 2-3) tCSRES 486 512 538 μs(7)
93
94
DAC Low-Pass Filter
Number of Poles
Cutoff Frequency nPOLES
fC—
51
10 —
20 unit
kHz (1)
(7)
95 Sensing Element Rolloff Frequency (-3 dB) BWGCELL — 3 — kHz (1)
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Figure 2-1 Power-Up Timing
Figure 2-2 Power Supply Coupling - DAC Outputs
VCC
tXY
XOUT/YOUT
5.5V
VPOR_N VPOR_A
VDACU
DAC OUTPUT
UNCERTAIN
POR
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Freescale Semiconductor 13
Figure 2-3 CS Reset Timing
INTERNAL RESET
CS
t
CSRES
SCLK
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14 Freescale Semiconductor
PACKAGE DIMENSIONS
MMA6222AKEG
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Freescale Semiconductor 15
PACKAGE DIMENSIONS
MMA6222AKEG
Rev. 0
12/2009
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical
characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further
information, see http:/www.freescale.com or contact your Freescale sales representative.
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