LTC3026-1
1
30261f
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
1.5A Low Input Voltage
VLDO Linear Regulator
The LTC
®
3026-1 is a very low dropout (VLDO™) linear
regulator that can operate at input voltages down to
1.14V. The device is capable of supplying 1.5A of output
current with a typical dropout voltage of only 100mV.
Output current comes directly from the input supply to
maximize efficiency.
The LTC3026-1 is the same as the LTC3026 but has the
boost converter internally disabled. With the boost con-
verter disabled, the SW pin of the LTC3026 is replaced with
a ground pin and the BST pin is replaced with a BIAS pin
that requires an external 5V supply for operation.
The LTC3026-1 regulator is stable with 10μF or greater
ceramic output capacitors. The device has a low 0.4V
reference voltage which is used to program the output
voltage via two external resistors. The device also has
internal current limit, overtemperature shutdown, and
reverse output current protection. The LTC3026-1 is avail-
able in a small 10-lead MSOP or low profile (0.75mm)
10-lead 3mm × 3mm DFN package.
1.2V Output Voltage from 1.5V Input Supply
n Input Voltage Range: 1.14V to 5.5V
n Low Dropout Voltage: 100mV at IOUT = 1.5A
n Adjustable Output Range: 0.4V to 2.6V
n Output Current: Up to 1.5A
n Excellent Supply Rejection Even Near Dropout
n Shutdown Disconnects Load from VIN and VBST
n Low Operating Current:
I
IN = 95μA at VIN = 1.5V
I
BIAS = 175μA at VBIAS = 5V
n Low Shutdown Current:
I
IN < 1μA (Typ), IBST = 0.1μA (Typ)
n Stable with 10μF or Greater Ceramic Capacitors
n Short-Circuit, Reverse Current Protected
n Overtemperature Protected
n Available in 10-Lead MSOP and 10-Lead
(3mm × 3mm) DFN Packages
n High Efficiency Linear Regulator
n Post Regulator for Switching Supplies
n Microprocessor Supply
Dropout Voltage vs Output Current
IN
0.4V
OUT
BIAS
GND
GNDS
ADJ
PG
1μF
COUT
10μF
VIN = 1.5V
VOUT = 1.2V,
1.5A
VBIAS = 5V
OFF ON
100k
8.06k
4.02k
LTC3026-1
30261 TA01a
SHDN
+
–
1μF
IOUT (A)
0
DROPOUT (mV)
100
150
30261 TA01b
50
00.5 1.0 1.5
1.2V
1.5V
2.0V
2.6V
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and ThinSOT, VLDO are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
LTC3026-1
2
30261f
ABSOLUTE MAXIMUM RATINGS
VBIAS to GND ................................................ –0.3V to 6V
VIN to GND ................................................... –0.3V to 6V
PG to GND ................................................... –0.3V to 6V
SHDN to GND ............................................ –0.3V to 6.3V
ADJ to GND .................................. –0.3V to (VIN + 0.3V)
GND to GNDS ............................................ –0.3V to 0.3V
(Note 1)
TOP VIEW
DD PACKAGE
10-LEAD (3mm = 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1OUT
OUT
ADJ
PG
SHDN
IN
IN
GND
GNDS
BIAS
11
GND
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
IN
IN
GND
GNDS
BIAS
10
9
8
7
6
OUT
OUT
ADJ
PG
SHDN
TOP VIEW
MSE PACKAGE
10-LEAD PLASTIC MSOP
11
GND
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3026EDD-1#PBF LTC3026EDD-1#TRPBF LGHG 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3026IDD-1#PBF LTC3026IDD-1#TRPBF LGHG 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3026EMSE-1#PBF LTC3026EMSE-1#TRPBF LTGHH 10-Lead Plastic MSOP –40°C to 125°C
LTC3026IMSE-1#PBF LTC3026IMSE-1#TRPBF LTGHH 10-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range
(Note 7) ............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (MSE, Soldering, 10 sec) .........300°C
LTC3026-1
3
30261f
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage (Note 2) l1.14 5.5 V
IIN Operating Current IOUT = 100μA, VSHDN = VIN, 1.2V ≤ VIN ≤ 5V l95 200 μA
Shutdown Current VSHDN = 0V, VIN = 3.5V l0.6 20 μA
VBIAS BIAS Operating Voltage (Note 6) VSHDN = VIN l4.5 5 5.5 V
VBIASUVLO BIAS Undervoltage Lockout l4.0 4.25 4.4 V
IBIAS BIAS Operating Current IOUT = 100μA, VSHDN = VIN l175 275 μA
BIAS Shutdown Current VSHDN = 0V 1 5 μA
VADJ Regulation Voltage (Note 4) 1mA ≤ IOUT ≤ 1.5A, 1.14V ≤ VIN ≤ 3.5V, VBST = 5V, VOUT = 0.8V
1mA ≤ IOUT ≤ 1.5A, 1.14V ≤ VIN ≤ 3.5V, VBST = 5V, VOUT = 0.8V l
0.397
0.395
0.4
0.4
0.403
0.405
V
V
OUT Programming Range l0.4 2.6 V
Dropout Voltage (Note 5) VIN = 1.5V, VADJ = 0.38, IOUT = 1.5A l100 250 mV
IADJ ADJ Input Current VADJ = 0.4V l–100 100 nA
IOUT Continuous Output Current VSHDN = VIN l1.5 A
ILIM Output Current Current Limit 3A
enOutput Voltage Noise f = 10Hz to 100kHz, IL = 800mA 110 μVRMS
VIHSHDN SHDN Input High Voltage 1.14V ≤ VIN ≤ 3.5V
3.5V ≤ VIN ≤ 5.5V
l
l
1.0
1.2
V
V
VILSHDN SHDN Input Low Voltage 1.14V ≤ VIN ≤ 5.5V l0.4 V
IIHSHDN SHDN Input High Current SHDN = VIN –1 1 μA
IILSHDN SHDN Input Low Current SHDN = 0V –1 1 μA
VOLPG PG Output Low Voltage IPG = 2mA l0.1 0.4 V
IOHPG PG Output High Leakage
Current
VPG = 5.5V 0.01 1 μA
PG Output Threshold (Note 3) PG High to Low
PG Low to High
–12
–10
–9
–7
–6
–4
%
%
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TJ = 25°C. (Note 7) VIN = 1.5V, VOUT = 1.2V, VBIAS = 5V, CIN = CBIAS = 1μF,
COUT = 10μF (all capacitors ceramic) unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. This IC has overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperatures will exceed 125°C when overtemperature is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: Minimum Operating Voltage required for regulation is:
V
IN ≥ VOUT(MIN) + VDROPOUT
Note 3: PG threshold expressed as a percentage difference from the
“VADJ Regulation Voltage” as given in the table.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: Dropout voltage is minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to VIN – VDROPOUT.
Note 6: To maintain correct regulation
V
OUT ≤ VBIAS – 2.4V
Note 7: The LTC3026-1 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3026E-1 is guaranteed to meet specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3026I-1 is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (PD, in Watts) according to the formula:
T
J = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
LTC3026-1
4
30261f
BIAS Supply Current IN Supply Current ADJ Voltage vs Temperature
IN Shutdown Current
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage vs Input Voltage VIN Ripple Rejection
VIN Ripple Rejection Shutdown Threshold Output Current Limit
30261 G01
VIN (V)
1.0
IBIAS (μA)
5.54.0 4.5 5.0
1.5 2.0 2.5 3.53.0
200
150
100
50
0
125°C
85°C
25°C
–40°C
VBIAS = 5V
30261 G02
VIN (V)
1.0 5.54.0 4.5 5.0
1.5 2.0 2.5 3.53.0
IIN (μA)
200
150
100
50
0
VBST = 5V
125°C
85°C
25°C
–40°C
VBIAS = 5V
30261 G03
TEMPERATURE (°C)
–50 –25
404
403
402
401
400
399
398
397
396
75 10005025 125
ADJUST VOLTAGE (mV)
1mA
1.5A
VBIAS = 5V
VIN = 1.5V
VOUT =1.2V
30261 G04
–50 –25 75 10005025 125
TEMPERATURE (°C)
INPUT CURRENT (μA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
01.2V
2.5V
3.5V
30261 G05
VIN (V)
1.2
200
180
160
140
120
100
80
60
40
20
02.2
1.4 1.6 1.8 2.42.0 2.6
DROPOUT (mV)
VFB = 0.38V
IOUT =1.5A
125°C
85°C
25°C
–40°C
30261 G06
VIN (V)
1.2
RIPPLE REJECTION (dB)
60
50
40
30
20
10
01.8 2.2
1.4 1.6 2.0 2.4 2.6
1MHz
100kHz
10kHz
VBIAS = 5V
VOUT =1.2V
IOUT = 800mA
COUT = 10μF
30261 G07
FREQUENCY (Hz)
100
70
60
50
40
30
20
10
0
100000
1000 10000 1000000 1E+07
RIPPLE REJECTION (dB)
VBIAS = 5V
VIN = 1.5V
VOUT =1.2V
IOUT = 800mA
COUT = 10μF
30261 G08
VIN (V)
1
VSHDN THRESHOLD (mV)
1200
900
600
300 23456
125°C
25°C
–40°C
RISE
RISE
RISE
FALL
FALL
FALL
30261 G09
VIN (V)
1.0
IOUT (A)
2.5 3.5
1.5 2.0 3.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
CURRENT LIMIT
THERMAL LIMIT
VOUT = 0V
TA = 25°C
LTC3026-1
5
30261f
BIAS to OUT Headroom Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
IN Supply Transient Response
Delay from Enable to PG
Output Load Transient Response
30261 G10
TEMPERATURE (°C)
–50
VBIAS – VOUT (V)
2.22
2.20
2.18
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02 050 75
–25 25 100 125
30261 G11
VIN (V)
1.0
DELAY (μs)
2.0 3.0 3.5 5.5
1.5 2.5 4.0 4.5 5.0
400
375
350
325
300
275
250
85°C
25°C
–40°C
VOUT = 0.8V
ROUT = 8Ω
30261 G12
IOUT
1.5A
2mA
OUT
AC 20mV/DIV
50μs/DIV
VOUT = 1.5V
COUT = 10μF
VIN = 1.7V
VBIAS = 5V
30261 G13
VIN
2V
1.5V
VOUT
AC
10mV/DIV
10μs/DIV
VOUT = 1.2V
IOUT = 800mA
COUT = 10μF
VBIAS = 5V
TA = 25°C
LTC3026-1
6
30261f
PIN FUNCTIONS
IN (Pins 1, 2): Input Supply Voltage. Output load current
is supplied directly from IN. The IN pin should be locally
bypassed to ground if the LTC3026-1 is more than a few
inches away from another source of bulk capacitance.
In general, the output impedance of a battery rises with
frequency, so it is usually advisable to include an input
bypass capacitor when supplying IN from a battery. A
capacitor in the range of 0.1μF to 4.7μF is usually sufficient.
GND (Pin 3, Exposed Pad Pin 11): Ground and Heat Sink.
Connect the exposed pad to the PCB ground plane or large
pad for optimum thermal performance.
GNDS (Pin 4): Ground Sense Pin. Tie directly to Pin 3
GND external to the part.
BIAS (Pin 5): BIAS Voltage Pin. Must be connected to an
external 5V supply. A 1μF low ESR ceramic capacitor is
recommended for bypassing the BIAS pin.
SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin is
used to put the LTC3026-1 into shutdown. The SHDN pin
current is typically less than 10nA. The SHDN pin cannot
be left floating and must be tied to a valid logic level (such
as IN) if not used.
PG (Pin 7): Power Good Pin. When PG is high impedance
OUT is in regulation, and low impedance when OUT is in
shutdown or out of regulation.
ADJ (Pin 8): Output Adjust Pin. This is the input to the error
amplifier. It has a typical bias current of 0.1nA flowing into
the pin. The ADJ pin reference voltage is 0.4V referenced
to ground. The output voltage range is 0.4V to 2.6V and is
typically set by connecting ADJ to a resistor divider from
OUT to GND. See Figure 3.
OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins
supply power to the load. A minimum output capacitance
of 5μF is required to ensure stability. Larger output capaci-
tors may be required for applications with large transient
loads to limit peak voltage transients. See the Applica-
tions Information section for more information on output
capacitance.
LTC3026-1
7
30261f
–
+
–
+
–
+
SHDN 0.4V
REFERENCE
6
7
5
8
UVLO
1,2
IN
OUT
BIAS
SHDN
ADJ
PG
4
GNDS
9,10
0.372V
30261 BD
GND
3, 11
+
–
OVERSHOOT DETECT
VOFF
BLOCK DIAGRAM
LTC3026-1
8
30261f
The LTC3026-1 is a VLDO (very low dropout) linear regula-
tor which operates from input voltages as low as 1.14V.
The LDO uses an internal NMOS transistor as the pass
device in a source-follower configuration. The BIAS pin
provides the higher supply necessary for the LDO circuitry
while the output current comes directly from the IN input
for high efficiency regulation.
The LTC3026-1 is the same as the LTC3026 but has the
boost converter disabled. The SW pin of the LTC3026
has been replaced with a GNDS pin. Because the boost
converter is disabled, an external 5V supply must be pres-
ent to drive the BIAS pin (formally BST on the LTC3026).
LDO Operation
An undervoltage lockout comparator (UVLO) senses the
BIAS pin voltage to ensure that the bias supply for the LDO
is greater than 4.2V before enabling the LDO. If BIAS is
below 4.2V, the UVLO shuts down the LDO, and OUT is
pulled to GND through the external divider.
The LDO provides a high accuracy output capable of sup-
plying 1.5A of output current with a typical dropout voltage
of only 100mV. A single ceramic capacitor as small as 10μF
is all that is required for output bypassing. A low reference
voltage allows the LTC3026-1 output to be programmed
to much lower voltages than available in common LDOs
(range of 0.4V to 2.6V).
The devices also include current limit and thermal overload
protection, and will survive an output short-circuit indefi-
nitely. The fast transient response of the follower output
stage overcomes the traditional trade-off between dropout
voltage, quiescent current and load transient response
inherent in most LDO regulator architectures, see Figure 1.
The LTC3026-1 also includes a soft-start feature to prevent
excessive current flow at VIN during start-up. When the
LDO is enabled, the soft-start circuitry gradually increases
the LDO reference voltage from 0V to 0.4V over a period
of approximately 200μs, see Figure 2.
Adjustable Output Voltage
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 3. The device servos the output
to maintain the ADJ pin voltage at 0.4V (referenced to
ground). Thus, the current in R1 is equal to 0.4V/R1. For
good transient response, stability and accuracy the current
in R1 should be at least 80μA, thus, the value of R1 should
be no greater than 5k. The current in R2 is the current in
R1 plus the ADJ pin bias current. Since the ADJ pin bias
current is typically <10nA it can be ignored in the output
voltage calculation. The output voltage can be calculated
using the formula in Figure 3. Note that in shutdown the
output is turned off and the divider current will be zero
once COUT is discharged.
OPERATION
Figure 1. Output Load Step Response
Figure 2. Soft-Start with Boost Disable
IOUT
1.5A
0mA
OUT
AC 20mV/DIV
100μs/DIV
VOUT = 1.5V
COUT = 10μF
VIN = 1.7V
VBIAS = 5V
30261 F01
SHDN
OUT
PG
HI
LO
100μs/DIV
TA = 25°C
ROUT = 1Ω
VIN = 1.7V
VBIAS = 5V
1.5V
1.5V
0V
0V 30261 F02
LTC3026-1
9
30261f
OPERATION
The LTC3026-1 operates at a relatively high gain of
270μV/A referred to the ADJ input. Thus, a load current
change of 1mA to 1.5A produces a 400μV drop at the ADJ
input. To calculate the change in the output, simply mul-
tiply by the gain of the feedback network (i.e. 1 + R2/R1).
For example, to program the output for 1.2V choose
R2/R1 = 2. In this example an output current change of
1mA to 1.5A produces –400μV • (1 + 2) = 1.2mV drop at
the output.
Power Good Operation
The LTC3026-1 includes an open-drain power good (PG)
output pin with hysteresis. If the chip is in shutdown or
under UVLO conditions (VBIAS < 4.25V typ.), PG is low
impedance to ground. PG becomes high impedance when
VOUT rises to 93% of its regulation voltage. PG stays high
impedance until VOUT falls back down to 91% of its regula-
tion value. A pull-up resistor can be inserted between PG
and a positive logic supply (such as IN, OUT, BIAS, etc.)
to signal a valid power good condition. VIN should be the
minimum operating voltage (1.14V) or greater for PG to
function correctly.
Output Capacitance and Transient Response
The LTC3026-1 is designed to be stable with a wide range
of ceramic output capacitors. The ESR of the output
capacitor affects stability, most notably with small ca-
pacitors. An output capacitor of 10μF or greater with an
ESR of 0.05Ω or less is recommended to ensure stability.
The LTC3026-1 is a micropower device and output tran-
sient response will be a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes. Note that bypass capacitors
used to decouple individual components powered by the
Figure 3. Programming the LTC3026-1
LTC3026-1 will increase the effective output capacitor
value. High ESR tantalum and electrolytic capacitors may
be used, but a low ESR ceramic capacitor must be in paral-
lel at the output. There is no minimum ESR or maximum
capacitor size requirements.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit strong voltage and tem-
perature coefficients as shown in Figures 4 and 5. When
used with a 2V regulator, a 10μF Y5V capacitor can exhibit
an effective value as low as 1μF to 2μF over the operating
temperature range. The X5R and X7R dielectrics result in
VOUT
ADJ
GND
COUT
R2
R1
LTC3026-1
30261 F03
VOUT =0.4V 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
Figure 4. Ceramic Capacitor DC Bias Characteristics
Figure 5. Ceramic Capacitor Temperature Characteristics
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
30261 F04
20
0
–20
–40
–60
–80
–100
X5R
Y5V
BOTH CAPACITORS ARE 10μF,
6.3V, 0805 CASE SIZE
0123456
TEMPERATURE (°C)
–50
20
0
–20
–40
–60
–80
–100 25 75
30261 F05
–25 0 50
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 10μF,
6.3V, 0805 CASE SIZE
LTC3026-1
10
30261f
OPERATION
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values.
A minimum capacitance of 5μF must be maintained at all
times on the LTC3026-1 LDO output.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
majority of the power dissipated in the device will be the
output current multiplied by the input/output voltage dif-
ferential: (IOUT)(VIN – VOUT). Note that the BIAS current
is less than 200μA even under heavy loads, so its power
consumption can be ignored for thermal calculations.
The LTC3026-1 has internal thermal limiting designed to
protect the device during momentary overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat-spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat gener-
ated by power devices.
A junction-to-ambient thermal coefficient of 40°C/W is
achieved by connecting the exposed pad of the MSOP or
DFN package directly to a ground plane of about 2500mm2.
Calculating Junction Temperature
Example: Given an output voltage of 1.2V, an input voltage
of 1.8V ±4%, an output current range of 0mA to 1A and
a maximum ambient temperature of 50°C, what will the
maximum junction temperature be?
The power dissipated by the device will be approximately:
I
OUT(MAX)(VIN(MAX) – VOUT)
where:
I
OUT(MAX) = 1A
V
IN(MAX) = 1.87V
so:
P = 1A(1.87V – 1.2V) = 0.67W
Even under worst-case conditions LTC3026-1’s BIAS pin
power dissipation is only about 1mW, thus can be ignored.
The junction to ambient thermal resistance will be on the
order of 40°C/W. The junction temperature rise above
ambient will be approximately equal to:
0.67W(40°C/W) = 26.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
A = 26.8°C + 50°C = 76.8°C
LTC3026-1
11
30261f
OPERATION
Short-Circuit/Thermal Protection
The LTC3026-1 has built-in output short-circuit current
limiting as well as overtemperature protection. During
short-circuit conditions, internal circuitry automatically
limits the output current to approximately 3A. At higher
temperatures, or in cases where internal power dissipa-
tion cause excessive self heating on-chip, the thermal
shutdown circuitry will shut down the boost converter and
LDO when the junction temperature exceeds approximately
150°C. It will reenable the converter and LDO once the
junction temperature drops back to approximately 140°C.
The LTC3026-1 will cycle in and out of thermal shutdown
without latchup or damage until the overstress condition
is removed. Long term overstress (TJ > 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
Reverse Input Current Protection
The LTC3026-1 features reverse input current protection to
limit current draw from any supplementary power source
at the output. Figure 6 shows the reverse output current
limit for constant input and output voltages cases. Note:
Positive input current represents current flowing into the
VIN pin of LTC3026-1.
With VOUT held at or below the output regulation voltage
and VIN varied, IN current flow will follow Figure 6’s curves.
IIN reverse current ramps up to about 16μA as the VIN
approaches VOUT. Reverse input current will spike up as
VIN approaches within about 30mV of VOUT as the reverse
current protection circuitry is disabled and normal opera-
tion resumes. As VIN transitions above VOUT the reverse
current transitions into short-circuit current as long as
VOUT is held below the regulation voltage.
Layout Considerations
Connection from BIAS and OUT pins to their respec-
tive ceramic bypass capacitor should be kept as short
as possible. The ground side of the bypass capacitors
should be connected directly to the ground plane for best
results or through short traces back to the GND pin of the
part. Long traces will increase the effective series ESR
and inductance of the capacitor which can degrade
performance.
Because the ADJ pin is relatively high impedance (depend-
ing on the resistor divider used), stray capacitance at this
pin should be minimized (<10pF) to prevent phase shift
in the error amplifier loop. Additionally special attention
should be given to any stray capacitances that can couple
external signals onto the ADJ pin producing undesirable
output ripple. For optimum performance connect the ADJ
pin to R1 and R2 with a short PCB trace and minimize all
other stray capacitance to the ADJ pin.
INPUT VOLTAGE (V)
IIN CURRENT (μA)
30261 F06
30
20
10
0
–10
–20
–30 00.6 0.9 1.2
0.3 1.5 1.8
IN CURRENT
LIMIT ABOVE 1.45V
Figure 6. Input Current vs Input Voltage
Figure 7. Suggested Layout
1
2
3
4
5
10
9
8
7
6
IN
IN
GND
GNDS
BIAS
OUT
OUT
ADJ
PG
SHDN
30261 F07
VIA CONNECTION TO GND PLANE
CIN COUT
CBIAS
R2
R1
LTC3026-1
12
30261f
TYPICAL APPLICATIONS
Using 1 Boost with Multiple Regulators
IN
SW
OUT
BST
GND
ADJ
PG
10μH
4.7μF
COUT1
10μF
VIN = 2.5V
VOUT1
1.8V, 1.5A
PG1 PG2
100k
14k
4.02k
LTC3026
30261 TA02
SHDN
LTC3026 WITH BOOST ENABLED FANOUT:
3-LTC3026-1 FOR VIN <1.4V
5-LTC3026-1 FOR VIN >1.4V
4.7μF
IN OUT
BIAS
GND
GNDS
ADJ
PG
1μF
COUT2
10μF
VOUT2
1.5V, 1.5A
100k
11k
4.02k
LTC3026-1
SHDN
1μF
TO ADDITIONAL
REGULATORS
LTC3026-1
13
30261f
TYPICAL APPLICATIONS
2.5V Output from 3.3V Supply with External 5V Bias
PG
3026 TA03
IN OUT
BIAS
GND
ADJ
PG
1μF
COUT
10μF
VOUT
2.5V, 1.5A
100k
21k
4.02k
LTC3026-1
SHDN
1μF
VBIAS = 5V
VIN = 3.3V
GNDS
LTC3026-1
14
30261f
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC3026-1
15
30261f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
MSOP (MSE) 0911 REV H
0.53 t0.152
(.021 t.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 t0.152
(.193 t.006)
0.497 t0.076
(.0196 t.003)
REF
8910
10
1
76
3.00 t0.102
(.118 t.004)
(NOTE 3)
3.00 t0.102
(.118 t.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0s – 6s TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 t0.127
(.035 t.005)
RECOMMENDED SOLDER PAD LAYOUT
1.68 t0.102
(.066 t.004)
1.88 t0.102
(.074 t.004)
0.50
(.0197)
BSC
0.305 t 0.038
(.0120 t.0015)
TYP
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.68
(.066)
1.88
(.074)
0.1016 t0.0508
(.004 t.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev H)
LTC3026-1
16
30261f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2012
LT 0812 • PRINTED IN USA
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ITH
RUN/SS
SYNC/FCB
VFB
GND
IN
SHDN
GND
BIAS
OUT
ADJ
PG
SW
SENSE–
VIN
TG
BG
LTC1773
10
9
8
7
6
1
2
3
4
5
RSENSE
0.04Ω
33pF
200pF
30k
0.1μF
1μF
1μF
80.6k
1%
100k
1%
CIN
47μF
10V COUT
10μF
CBUCK
47μF
10V
VBUCK
1.8V
2A
4.5V ) VIN ) 5.5V
Si9942DY
LTC3026-1
11k
100k 4.02k
VOUT
1.5V
1.5A
PG
L1
2.5μH
30261 TA04
CIN, CBUCK: TAIYO YUDEN LMK550BJ476MM
L1: CDRH5D28
RSENSE: IRC LR1206-01-R040-F
GNDS
