To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
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subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
Rev.2.13 Apr 17, 2009 Page 1 of 56
REJ03B0125-0213
DESCRIPTION
The 3850 group (spec.A QzROM version) is the 8-bit
microcomputer based on the 740 family core technology.
The 3850 group (spec.A QzROM version) is designed for the
household products and office automation equipment and
includes serial interface functions, 8-bit timer, and A/D
converter.
FEATURES
• Basic machine-language instructions ................................. 71
• Minimum instruction execution time .......................... 0.32 µs
(at 12.5 MHz oscillation frequency)
• Memory size
ROM ..................................................................... 16 K bytes
RAM ........................................................................ 512 bytes
• Programmable input /output ports .............. ............. ............ 34
• On-chip software pull-up resistor ................................ Built-in
• Interrupts ............................................. 15 sources, 14 vectors
• Timers ....................................................................... 8-bit × 4
• Serial interfa ce
Serial I/O1 ............. 8-bit × 1 (UART or Clock-synchronized)
Serial I/O2 ............................. 8-bit × 1 (Clock-synchronized)
• PWM ......................................................................... 8-bit × 1
• A/D converter .......................................... 10-bit × 9 channels
• Watchdog time r ............... ........................... ............. 16-bit × 1
• Clock generating circuit ............................. Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage
[In high-speed mode]
f(XIN) ≤ 12.5 MHz .............................................4.0 to 5.5 V
f(XIN) ≤ 6.0 MHz ...............................................2.7 to 5.5 V
f(XIN) ≤ 4.2 MHz ...............................................2.2 to 5.5 V
f(XIN) ≤ 2.1 MHz ...............................................2.0 to 5.5 V
[In middle-speed mode]
f(XIN) ≤ 12.5 MHz .............................................2.7 to 5.5 V
f(XIN) ≤ 8.4 MHz ...............................................2.2 to 5.5 V
f(XIN) ≤ 4.2 MHz ...............................................1.8 to 5.5 V
[In low-speed mode]
f(XCIN) ≤ 50 kHz................................................1.8 to 5.5 V
• Power dissipation
In high-speed mode ...... ............................. ........ 30 mW (typ.)
(at 12.5 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............... ............. ............. ... 45 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V powe r s ource volta g e)
• Operating temperature range ............................. −20 to 85 °C
APPLICATION
Household products, Consumer el ec tronics, etc.
Fig 1. Pin configuration
M38503G4A-XXXSP/FP
M38503G4ASP/FP
1
2
3
4
6
7
9
10
5
11
12
13
15
17
19
21
8
14
16
18
20
42
41
40
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
33
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P26/SCLK1
P25/TxD
P24/RxD
P23
P22
CNVSS
P21/XCIN
RESET
XIN
XOUT
VSS
P27/CNTR0/SRDY1
P20/XCOUT
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P04/AN5
P05/AN6
P06/AN7
P07/AN8
P10(LED0)
P11(LED1)
P12(LED2)
P14(LED4)
P15(LED5)
P16(LED6)
P17(LED7)
P03/SRDY2
P13(LED3)
Package type : SP ·········· PRDP0042BA-A (42P4B) (42-pin shrink plastic-molded SDIP)
Package type : FP ·········· PRSP0042GA-A/B (42P2R-A/E) (42-pin plastic-molded SSOP)•
PIN CONFIGURATION (TOP VIEW)
3850 Group (Spec.A QzROM version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0125-0213
Rev.2.13
Apr 17, 2009
Rev.2.13 Apr 17, 2009 Page 2 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 2. Functional block diagram
INT0-
CNTR0
CNTR1
VREF
AVSS
RAM ROM
C P U
A
X
Y
S
PCHPCL
PS
VSS
21
RESET
18
VCC
115
CNVSS
23
XIN
19 20
SI/O1 (8)
Reset input
Clock generating circuit
Main-clock
input
A/D
converter
(10)
Tim e r Y (8 )
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Pres caler Y ( 8)
Timer 1 (8)
Tim e r 2 (8 )
Sub-clock
input
XCIN
XOUT
Wa tc h do g tim e r Reset
P2(8)
P3(5)
P4(5)
I/O p o r t P4
INT3
468
5739 4138 40 42 911 13 17
10 12 1416
P1(8)
22 24 26 2823 25 27 29
P0(8)
30 31 32 33 34 35 36 37
PWM
(8)
XCIN
XCOUT
FUNCTIONAL BLOCK DIAGRAM
Main-clock
output
Sub-clock
output
XCOUT
I/O port P3 I/O p ort P 2 I/O p ort P 1 I/O p ort P 0
SI/O2 (8)
Rev.2.13 Apr 17, 2009 Page 3 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
PIN DESCRIPTION
Table 1 Pin description
Pin Name Function Function except a port function
VCC, VSS Power source Apply voltage of 1.8 V−5.5 V to VCC, and 0 V to VSS.
CNVSS CNVSS input • This pin controls the operation mode of the chip and is shared with the VPP pin which is the
power source input pin for programming the built-in QzROM.
• Normally connected to VSS.
VREF Reference
voltage Reference voltage input pin for A/D converter.
AVSS Analog power
source • Analog power source input pin for A/D converter.
• Connect to VSS.
RESET Reset input • Reset input pin for active “L”.
XIN Clock input • Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.
XOUT Clock output
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
I/O port P0 • 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a byte unit.
•P1
0 to P17 (8 bits) are enabled to output large current
for LED drive.
• Serial I/O2 function pin
P04/AN5−P07/AN8• A/D converter input pin
P10-P17I/O port P1
P20/XCOUT
P21/XCIN I/O port P2 • 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
•P2
0, P21, P24, to P27: CMOS3-state output structure.
•P2
2, P23: N-channel open-drain structure.
• Pull-up control of P20, P21, P24−P27 is enabled in a
byte unit.
• Sub-clock generating circuit I/O
pins (connect a resonator)
P22
P23
P24/RXD
P25/TXD
P26/SCLK1
• Serial I/O1 function pin
P27/CNTR0/SRDY1 • Serial I/O1 function pin
• Timer X function pin
P30/AN0−P34/AN4I/O port P3 • 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• A/D converter input pin
P40/CNTR1I/O port P4 • 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• Timer Y function pin
P41/INT0
P42/INT1• Interrupt input pins
P43/INT2/SCMP2 • Interrupt input pin
•S
CMP2 output pin
P44/INT3/PWM • Interrupt input pin
• PWM output pin
Rev.2.13 Apr 17, 2009 Page 4 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
PART NUMBERING
Fig 3. Part numbering
Product name M3850 3 G 4 A- XXX SP
Package type
SP : PRDP0042BA-A
FP : PRSP0042GA-A/B
ROM number
Omitted in blank version.
A- : High-speed version
“-” is omitted in the shipped in blank version.
QzROM memory size
1 : 4096 bytes 9 : 36864 bytes
2 : 8192 byt es A : 40960 bytes
3 : 12288 bytes B : 45056 bytes
4 : 16384 bytes C : 49152 bytes
5 : 20480 bytes D : 53248 bytes
6 : 24576 bytes E : 57344 bytes
7 : 28672 bytes F : 61440 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of RAM, and
1 byte of address FFDB16 are reserved areas; they
cannot be used as a user's ROM area.
Memory t ype
G : QzROM version
RAM size
0 : 192 bytes 5 : 768 bytes
1 : 256 bytes 6 : 896 bytes
2 : 384 bytes 7 : 1024 bytes
3 : 512 bytes 8 : 1536 bytes
4 : 640 bytes 9 : 2048 bytes
Rev.2.13 Apr 17, 2009 Page 5 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
GROUP EXPANSION
Renesas Technology expands the 3850 group (spec.A QzROM
version) as follows.
Memory Type
Support for QzROM version.
Memory Size
• ROM size ... ............. .............. ............. ............. ........ 16 K bytes
• RAM size ...................................................................512 bytes
Packages
• PRDP0042BA-A............... 42-pin shrink plastic-molded SDIP
• PRSP0042GA-A/B.......................42-pin plastic-molded SSOP
Fig 4. Memory expansion
NOTES:
1. This means a shipment of which User ROM has been programmed.
The user ROM area of a blank product is blank.
512
12K
16K
20K
24K
28K
32K
ROM
external
384 768640
8K
1024896 12801152 1408 20481536
ROM siz e (byte s)
M38503G4A
RAM size (bytes)
Memory Expansion
Table 2 Support products (spec.A QzROM version)
Product name ROM size (bytes)
ROM size for User in ( ) RAM size
(bytes) Package Remarks
M38503G4A-XXXSP 16384
(16253) 512 PRDP0042BA-A QzROM version
(Programmed shipment) (1)
M38503G4A-XXXFP PRSP0042GA-A/B
M38503G4ASP 16384
(16253) 512 PRDP0042BA-A QzROM version
(blank) (1)
M38503G4AFP PRSP0042GA-A/B
Rev.2.13 Apr 17, 2009 Page 6 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
GROUP DESCRIPTION
The QzROM version, mask ROM ver sion and the flash memor y version of 3850 group (Spec.A) are mass production. Currently
support products are listed below.
NOTES:
1. We are currently not receiving an new order for the standard version and Spec.H. We are currently receiving an new order for
Spec.A.
2. F or detail of the absolute maximum ratings, the electrical characteristics, and the recommended oper ating conditions, r efer t o each
datasheet.
Notes on differences among 3850 group (standard),
3850 group (spec.H), an d 38 5 0 grou p (s pe c.A)
(1) The absolute maximum ratings of 3850 group (spec.A) is
smaller than that of 3850 group (standard).
• Power source voltage VCC = −0.3 to 6.5 V
•CNV
SS input voltage VI = −0.3 to VCC +0.3 V (QzROM:
8.0V)
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT
may be some differences among 3850 group (standard),
3850 group (spec.H), and 3850 group (spec.A).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after reset. )
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
Table 3 Support products (mask ROM version and flash memory version of Spec.A)
Product name ROM size (bytes)
ROM size for User in ( ) RAM size
(bytes) Package Remarks
M38503M2A-XXXSP 8192
(8062) 512 PRDP0042BA-A Mask ROM version
M38503M2A-XXXFP PRSP0042GA-A/B
M38503M4A-XXXSP 16384
(16254) 512 PRDP0042BA-A
M38503M4A-XXXFP PRSP0042GA-A/B
M38504M6A-XXXSP 24576
(24446) 640 PRDP0042BA-A
M38504M6A-XXXFP PRSP0042GA-A/B
M38507M8A-XXXSP 32768
(32635) 1024 PRDP0042BA-A
M38507M8A-XXXFP PRSP0042GA-A/B
M38507F8ASP 32768 1024 PRDP0042BA-A Flash memory version
M38507F8AFP PRSP0042GA-A/B
Table 4 Differences among 3850 group (standard), 3850 group (spec.H), and 3850 group (spec.A)
3850 group (standard)(1) 3850 group (spec.H)(1) 3850 group (spec.A)
Mask ROM version
Flash memory version
QzROM version
Serial interface 1: Serial I/O
(UART1 or Clock-
synchronized)
2: Serial I/O1 (UART1 or
Clock-synchronized)
Serial I/O2 (Clock-
synchronized)
2: Serial I/O1 (UART1 or Clock-
synchronized)
Serial I/O2 (Clock-synchronized)
A/D converter Unserviceable in low-
speed mode
Analog input: 5 channels
Serviceable in low-speed
mode
Analog input: 5 channels
Serviceable in low-speed mode
Analog input: 9 channels
LED port 5: P13−P178: P10−P178: P10−P17
Software pull-up resistor Not available Not available Built-in (Port P0−P4)
Absolute
maximum
ratings
Power source
voltage −0.3 to 7.0 V −0.3 to 6.5 V −0.3 to 6.5 V
CNVSS
input voltage −0.3 to 13.0 V −0.3 to VCC + 0.3 V −0.3 to
VCC + 0.3 V −0.3 to 8.0 V
Maximum operat ing
frequency(2) 8.0 MHz 8.0 MHz 12.5 MHz
Minimum operating
power source voltage(2) 2.7 V 2.7 V 2.7 V 1.8 V
Rev.2.13 Apr 17, 2009 Page 7 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec.A) uses the standard 740 Family
instruction set. Refer to the table of 740 Family addressing
modes and machine instructions or the 740 Family Software
Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index regist er X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y
and specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates st art address of st ored area
(stack) for storing registers during subroutine calls and
interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit i s “0”, the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushi ng register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with
program when the user needs them during interrupts or
subroutine calls (see Table 5).
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig 5. 740 Family CPU register struct ure
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
b7 b0
b15 Program counter
Stack pointer
Index register Y
Index register X
Accumulator
A
X
Y
S
PCLPCH
CZIDBTVN
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Rev.2.13 Apr 17, 2009 Page 8 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 6. Register push and pop at interrupt generation and subroutine call
Interrupt request
(Note)
M(S)←(PCH)
(S)←(S) − 1
M(S)←(PCL)
(S)←(S) − 1
.....
Execute RTS
Subroutine
(S)←(S) + 1
(PCL)←M(S)
(S)←(S) + 1
(PCH)←M(S)
M(S)←(PCH)
(S)←(S) − 1
M(S)←(PCL)
(S)←(S) − 1
M(S)←(PS)
(S)←(S) − 1
Interrupt
Service Routine
(S)←(S) + 1
(PS)←M(S)
(S)←(S) + 1
(PCL)←M(S)
(S)←(S) + 1
(PCH)←M(S)
Execute JSR
.....
Execute RTI
Push return address
on stack
Push content s of processor
status register on stack
I Flag is set from “0” to “1”
Fetch the jump vector
POP contents of processor
status regi ster from stack
POP return
address from stack
POP return
address from
stack
Push return
address
on stack
Note : Condition for acceptance of an interrupt →Interrupt enable flag is “1”
Interrupt disable flag is “0”
On-going Routine
Table 5 Push and pop instruct ions of accumulator or processor status register
Push instruction to stack Pop instruction from stack
Accumulator PHA PLA
Processor status register PHP PLP
Rev.2.13 Apr 17, 2009 Page 9 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
Bit 3: Decimal mode flag (D)
The D flag de termines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it
is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal
arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”.
Bit 5: Index X mode flag (T)
When the T flag is “0” , arithmetic operations are performed
between accumulator and m emory. When the T flag is “ 1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to −
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instructi on is store d
in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithm etic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory locati on operated on by the
BIT instruction is stored in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction SEC −SEI SED −SET −−
Clear instruction CLC −CLI CLD −CLT CLV −
Rev.2.13 Apr 17, 2009 Page 10 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit,
the internal system clock control bits, etc.
The CPU mode register is allocated at address 003B16.
Fig 7. Structure of CPU mode register
CPU mode register
(CPUM: address 003B16)
b7 b0
Stack page selection bit
0 : 0 page
1 : 1 page
Processor mode bits
b1 b0
0 0 : Single-chip mode
01:
1 0 : Not available
11:
Main clock division ratio selection bits
b7 b6
00:φ = f(XIN)/2 (high-speed mode)
01:φ = f(XIN)/8 (middle-speed mode)
10:φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1:X
CIN-XCOUT oscillating function
Main clock (XIN-XOUT) stop bit
0 : Oscillating
0 : Stopped
1
Rev.2.13 Apr 17, 2009 Page 11 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
MEMORY
• Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O p orts and timers.
• RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
•ROM
The first 128 bytes and the last 2 bytes of ROM ar e reserved for
device testing and the rest is user area for storing programs.
In the QzROM version, 1 byte of address FFDB16 is also a
reserved area.
• Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
• Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
• Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
• ROM Code Protect Address (address FFDB16)
Address FFDB16, which is the reserved ROM area of QzROM, is
the ROM code protect address. “0016” is written into this a ddress
when selecting the prote ct bit write by using a serial programmer
or selecting protect enabled for writing shipment by Renesas
Technology corp.. When “0016” is set to the ROM code protect
address, the protect function is enabled, so that reading or writing
from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
As for the QzROM product shipped after writing, “00 16” (protect
enabled) or “FF16” (protect disabled) is writte n into the ROM
code protect address when Renesas Technology corp. performs
writing.
The writing of “0016” or “FF16” can be selected as ROM option
setup (“MASK option” written in the mask file converte r) when
ordering.
<Notes>
Since the contents of RAM are undefined at reset, be sure to set
an initial value before use.
Fig 8. Memory map diagram
Zero page
Special page
RAM area
RAM size
(bytes) Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
User ROM area
RAM
ROM
010016
000016
004016
FF0016
XXXX16
FFFE16
FFFF16
YYYY16
ZZZZ16
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
ROM area
RO M size
(bytes) Address
YYYY16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
Address
ZZZZ16
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
FFDC16
FFDB16
SFR area
Interrupt vector area
Reserved RO M area
Reserved RO M area
(128 bytes)
Reserved ROM area
(ROM code protect address)
Not used
Rev.2.13 Apr 17, 2009 Page 12 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 9. Memory map of special function register (SFR)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P0, P1, P2 pull-up control register (PULL012)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BR G )
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source selection register (TCSS)
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
AD control register (ADCON)
AD conversion low-order register (ADL)
AD conversion high-order register (ADH)
AD input selection registe r (ADSEL)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
* Reserved : Do not write any data to this addresses, because these areas are reserved.
0FFE16 Reserved *
Rev.2.13 Apr 17, 2009 Page 13 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
I/O PORTS
The I/O ports have direction registers which determine the
input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, and each pin can be set
to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pi n which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
By setting the port P0, P1, P2 pull-up control register (address
001216), the port P3 pull-up control register (address 001316), or
the port P4 pull-up control register (address 001416), ports can
control pull- up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
NOTES:
1. When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
Table 7 I/O port function
Pin Name Input/Out
put I/O Structure Non-Port Function Related SFRs Ref.No.
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
Port P0 Input/out
put,
individual
bits
CMOS compatible input
level
CMOS 3-state output
Serial I/O2 function I/O Serial I/O2 control register (1)
(2)
(3)
(4)
P04/AN5−
P07/AN8A/D converter input AD control register
AD input selection register (13)
P10−P17Port P1 (5)
P20/XCOUT
P21/XCIN Port P2 Sub-clock generating
circuit CPU mode register (6)
(7)
P22
P23CMOS compatible input
level
N-channel open-drain
output
(8)
P24/RXD
P25/TXD
P26/SCLK1
CMOS compatible input
level
CMOS 3-state output
Serial I/O1 function I/O Serial I/O1 control register (9)
(10)
(11)
P27/CNTR0/
SRDY1 Serial I/O1 function I/O
Timer X function I/O Serial I/O1 control register
Timer XY mode register (12)
P30/AN0−
P34/AN4Port P3(1) A/D converter input AD control register
AD input selection register (13)
P40/CNTR1Port P4(1) Timer Y function I/O Timer XY mode register (14)
P41/INT0
P42/INT1External interrupt input Interrupt edge selection register (15)
P43/INT2/
SCMP2 External interrupt input
SCMP2 output Interrupt edge selection register
Serial I/O2 control register (16)
P44/INT3/
PWM External interrupt input
PWM output Interrupt edge selection register
PWM control register (17)
Rev.2.13 Apr 17, 2009 Page 14 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 10. Port block diagram (1)
(5) Port P1
(7) Port P21
Port XC switch bit
Sub-clock generating circuit input
SRDY2 output enable bit
Serial I/O2 ready output
(4) Port P03
Data bus
Serial I/O2 input
(1) Port P00
(6) Port P20
Port XC switch bit
Port P21
Oscillator
Port XC switch bit
(2) Port P01
Serial I/O2 output
P01/SOUT2 P-channel output disable bit
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Serial I/O2 synchronous clock selection bit
(3) Port P02
Serial I/O2 clock output
Serial I/O2 external clock input
P02/SCLK2 P-channel output disable bit
Serial I/O2 port selection bit
(8) Ports P22, P23
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Port latch
Direction
register
Pull-up contro l bit
Pull-up control bit
Pull-up control bit
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Rev.2.13 Apr 17, 2009 Page 15 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 11. Port block diagram (2)
(11) Port P26
Serial I/O1 synchronous
clock selection bit
Serial I/O1 clock output
Serial I/O1 external clock input
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
Analog input pin selection bit
Analog input port selection switc h bit
(13) Ports P04-P07, P30-P34
A/D converter input
(14) Port P40
Pulse output mode
Timer output
CNTR1 interrupt input
(15) Ports P41, P42
Interrupt input
Serial I/O1 mode selection bit
Serial ready output
Pulse output mode
(12) Port P27
CNTR0
interrupt input
Timer output
Serial I/O1 enable bit
SRDY1 output enable bit
Pulse output mode
(9) Port P24
Serial I/O1 enable bit
Receive enable bit
Serial I/O1 input
(10) Port P25
Serial I/O1 enable bit
Transmit enable bit
Serial I/O1 output
P-channel output disable bit
Serial I/O2 I/O com pa r is on
signal output
Interrupt input
(16) Port P43
Serial I/O2 I/O comparison
signal control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Pull-up control bit
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Data bus Port la tch
Direction
register
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
Rev.2.13 Apr 17, 2009 Page 17 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 13. Structure of port registers (1)
b7 b0
Port P0, P1, P2 pull-up control register
(PULL012: address 001216)
P0 pull-up control bit
0: No pull-up
1: Pull-up
P1 pull-up control bit
0: No pull-up
1: Pull-up
P2 pull-up control bit
0: No pull-up
1: Pull-up
Not used (return “0” when read)
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (outpu t), pull-up cannot be set
to the port of which pull-up is selected.
b7 b0
Port P3 pull-up control register
(PULL3: address 001316)
P30 pull-up control bit
0: No pull-up
1: Pull-up
P31 pull-up control bit
0: No pull-up
1: Pull-up
P32 pull-up control bit
0: No pull-up
1: Pull-up
P33 pull-up control bit
0: No pull-up
1: Pull-up
P34 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (outpu t), pull-up cannot be set
to the port of which pull-up is selected.
Rev.2.13 Apr 17, 2009 Page 18 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 14. Structure of port registers (2)
b7 b0
Port P4 pull-up control register
(PULL4 : address 001416)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (outpu t), pull-up cannot be set
to the port of which pull-up is selected.
Rev.2.13 Apr 17, 2009 Page 19 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
eight internal, and one software.
• Interrupt Control
Each interrupt is controlled by an interrupt request bit, an
interrupt enable bit, and the interrupt disable flag except for the
software interrupt set by the BRK instruction. An interrupt
occurs if the corresponding interrupt request and enable bits are
“1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The
I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
When several interrupts occur at the same time, the inte rrupts are
received according to priori ty.
• Interrupt Operation
By acceptance of an interrupt, the following operations are
automatically performed:
1. The contents of the program counter and the processor sta-
tus register are automati c ally pushed onto the stack.
2. The interrupt disable flag is set and the corresponding inter-
rupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
<Notes>
When setting the followings, the interrupt request bit may be set
to “1”.
• When setting external interrupt active edge
Related register: Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address
003A16)
When not requiring for the interrupt occurrence synchronized
with these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit (the active edge selection
bit) or the interrupt source select.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Rev.2.13 Apr 17, 2009 Page 20 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority Vector
Addresses(1) Interrupt Request Generating
Conditions Remarks
High Low
Reset(2) 1FFFD16 FFFC16 At reset Non-maskable
INT02FFFB16 FFFA16 At detection of either rising or falling
edge of INT0 input External interrupt
(active edge selectable)
Reserved 3 FFF916 FFF816 Reserved
INT14 FFF716 FFF616 At detection of either rising or falling
edge of INT1 input External interrupt
(active edge selectable)
INT25 FFF516 FFF416 At detection of either rising or falling
edge of INT2 input External interrupt
(active edge selectable)
INT3/Serial I/O2 6 FFF316 FFF216 At detection of either rising or falling
edge of INT3 input/ At completion of
serial I/O2 data reception/transmission
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT3 interrupt
source bit
Reserved 7 FFF116 FFF016 Reserved
Timer X 8 FFEF16 FFEE16 At timer X underflow
Timer Y 9 FFED16 FFEC16 At timer Y underflow
Timer 1 10 FFEB16 FFEA16 At timer 1 underflow STP release timer underflow
Timer 2 11 FFE916 FFE816 At timer 2 underflow
Serial I/O1 reception 12 FFE716 FFE616 At completion of serial I/O1 data
reception Valid when serial I/O1 is selected
Serial I/O1
Transmission 13 FFE516 FFE416 At completion of serial I/O1 transfer
shift or when transmission buffer is
empty
Valid when serial I/O1 is selected
CNTR014 FFE316 FFE216 At detection of either rising or falling
edge of CNTR0 input External interrupt
(active edge selectable)
CNTR115 FFE116 FFE016 At detection of either rising or falling
edge of CNTR1 input External interrupt
(active edge selectable)
A/D converter 16 FFDF16 FFDE16 At completion of A/D conversion
BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Rev.2.13 Apr 17, 2009 Page 21 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 15. Interrupt control
Fig 16. Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
Serial I/O2 / INT3 interrupt source bit
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt request bit
Reserved
INT1 interrupt request bit
INT2 interrupt request bit
INT3 / Serial I/O2 interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interru pt requ est bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
Reserved (Do not write “1” to this bit.)
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 / Serial I/O2 interrupt enable bit
Reserved (Do not write “1” to this bit.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt control register 2
(ICON2 : address 003F16)
0 : Interrupts disabled
1 : Interrupts enabled
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interru pt ena ble bit
Serial I/O1 transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Rev.2.13 Apr 17, 2009 Page 22 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
TIMERS
The 3850 group (spec.A) has four timers: timer X, timer Y, timer
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig 17. Structure of timer XY mode register
Fig 18. Structure of timer count source selection regist er
• Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The
output of prescaler 12 is counted by timer 1 and timer 2, and a
timer underflow sets the interrupt request bit.
•Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count
source selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count
source selection bit. Whenever the contents of the ti mer reach
“0016”, the signal output from the CNTR0 (or CNTR1) pin is
inverted. If the CNTR0 (or CNTR1) active edge selection bit is
“0”, output begins at “H”.
If it is “1”, output starts at “L”. When using a timer in this mode,
set the corresponding port P27 (or port P40) direction register to
output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”,
the rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”,
the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the
timer counts the selected signals by the count source selection bit
while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or
CNTR1) active edge selection bit is “1”, the timer counts it while
the CNTR0 (or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer
Y) count stop bit in any mode. The corresponding interrupt
request bit is set each time a timer un derfl ows.
<Notes>
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count inpu t
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer
X/ timer Y interrupt request bits are set to “1”. Timer X/Timer Y
interrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the
instruction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer
underflow. When this interrupt is unnecessary, set “0” (disabled)
to the interrupt enable bit and the n se t “1” to the count stop bit.
b7 Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1 b0
0 0 : Timer mode
0 1: Pulse output mode
1 0 : Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1: Pulse output mode
1 0 : Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
b0
Timer count source selection register
(TCSS : address 002816)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN)
Not used (returns “0” when read)
b7 b0
Rev.2.13 Apr 17, 2009 Page 23 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 19. Block diagram of timer X, timer Y, timer 1, and timer 2
Q
Q
“1”
“0”
P27/CNTR0
Q
Q
P40/CNTR1
“0”
“1”
R
R
“1”
“0”
“0”
“1”
T
T
Prescaler X latch (8)
Prescaler X (8)
Timer X la tch (8)
Timer X (8) To timer X interrupt
request bit
Toggle flip-flop
Timer X count stop bit
Pulse width
measurement
mode
Event
counter
mode To CNTR0 interr up t
request bit
Pulse output mode
Port P27
latch
Port P27
direction register
CNTR0 active edge
selection bit
Timer X latch write pulse
Pulse out pu t m ode
Timer mode
Pulse output mode
Prescaler Y latch (8)
Prescaler Y (8)
Timer Y latch (8)
Timer Y (8) To timer Y interrupt
request bit
Toggle flip-flop
Timer Y count stop bit
To CNTR1 interrupt
request bit
Pulse output mode
Port P40
latch
Port P40
direction register
CNTR1 active edge
selection bit
Timer Y latch write pulse
Pulse output mode
Timer mode
Pulse output mode
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8) To timer 2 interrupt
request bit
To time r 1 interrupt
request bit
CNTR0 active edge
selection bit
CNTR1 active edge
selection bit
Pulse width
measurement
mode
Event
counter
mode
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
f(XIN)/2
(f(XCIN)/2 at low-speed mode)
Timer X count source
selection bit
Timer Y count source
selection bit
Timer 12 count source
selection bit
f(XCIN)
Data bus
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
f(XIN)/2
(f(XCIN)/2 at low-speed mode)
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Data bus
Rev.2.13 Apr 17, 2009 Page 24 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
SERIAL INTERFACE
• Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O1. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig 20. Block diagram of clock synchronous serial I/O1
Fig 21. Operation of clock synchronous serial I/O1 function
Serial I/O1 control register
Receive buffer register
Receive shift register
Clock control circuit
1/4
Baud rate generator
XIN
1/4
Clock control circuitFalling-edge detector
Transmit buffer register
Transmit shift register
Serial I/O1 status regi ster
F/F
Address 001816
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Serial I/O1 synchronous clock selection bit
Frequency division ratio 1/(n+1)
Address 001C16
BRG count source selection bit
Address 001816
Shift clock Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source sel e ction bit
Address 001916
Address 001A16
Data bus
Data bus
P26/SCLK1
P24/RXD
P25/TXD
P27/SRDY1
D7
D7
D0D1D2D3D4D5D6
D0D1D2D3D4D5D6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
Serial input RXD
Write pulse to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1: A s the tr ansmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended
(TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuo usly and serial data is outpu
t
continuously from the TXD pin.
3: The receive interru pt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Receive enable signal SRDY1
Rev.2.13 Apr 17, 2009 Page 25 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the s erial I/O1 mode se lection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig 22. Block diagram of UART serial I/O1
XIN
1/4
OE
PE FE
1/16
1/16
Data bus
Data bus
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Address 001C16
ST/SP/PA generator
Transmit buffer register
Transmit shift register
Address 001816
Transmit shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 001916
ST detector
SP detector UART control register
Address 001B16
Character length selection bit
Address 001A16
BRG count source selection bit
Transmit interrupt source sele ction bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 status regi ster
Serial I/O1 contro l register
P26/SCLK1
P24/RXD
P25/TXD
Rev.2.13 Apr 17, 2009 Page 26 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 23. Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are
located at the same a ddress. Th e transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bit s,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleare d to “0” when the
receive buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O1 status register clears all the error flags OE, PE, FE,
and SE (bit 3 t o b it 6, respec tiv ely). Writing “0” to the seri al I/ O1
enable bit SIOE (bit 7 of the serial I/O1 control register) also
clears all the stat us fla g s, inc ludi ng the error flags.
Bits 0 to 6 of the serial I/O1 s tatus register a re initialize d to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1
control register has been set to “1”, the transmit shift completion
flag (bit 2) and the transmit buf fe r empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for
the serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count so urce
by 1/(n + 1), where n is the value written to the baud rate
generator.
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
TBE=1 TSC=1*
STD0D1SP D0D1ST SP
Transmit or receive clock
Transmit buffer write
signal
Serial output TXD
Receive buffer read
signal
Serial input RXD
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Notes 1: Err or flag detection occurs at the same time that the RB F flag becom es “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the set ti ng of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
STD0D1SP D0D1ST SP
Rev.2.13 Apr 17, 2009 Page 27 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 24. Structure of serial I/O1 control re gisters
<Notes on serial interface>
When setting the transmit enable bit to “1”, the serial I/O1
transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the
transmission enabled, take the following sequence.
(1) Set the serial I/O1 transmit interrupt enable bit to “0”
(disabled).
(2) Set the transmi t ena ble bit to “1”.
(3) Set the serial I/O1 transmit interrupt request bit to “0” after
1 or more instructions have been executed.
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (P ARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
Serial I/O1 control register
(SIOCON : address 001A16)
Serial I/O1 status register
(SIOSTS : address 001916)
b0 b7 b0
b7 b0
Rev.2.13 Apr 17, 2009 Page 28 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
• Serial I/O2
The serial I/O2 can be operated only as the clock synchronous
type. As a synchronous clock for serial transfer, either internal
clock or external clock can be selected by the serial I/O2
synchronous clock selection bit (b6) of serial I/O2 control
register 1.
The internal clock incorporates a dedicated divider and permits
selecting 6 types of clock by the internal synchronous clock
selection bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pi ns, either CMOS
output format or N-channel open-drain output format can be
selected by the P01/SOUT2, P02/SCLK2 P-channel output disable
bit (b7) of serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After
completion of data transfer, the level of the SOUT2 pin goes to
high impedance automatically but bit 7 of the serial I/O2 control
register 2 is not set to “1” automatically.
When the external clock has been selected, the contents of the
serial I/O2 register is continuously shifted while transfer clocks
are input. Accordingly, control the clock externally. Note that the
SOUT2 pin does not go to high impedance after completion of
data transfer.
To cause the SOUT2 pin to go to high impedance in the case
where the external clock is selected, set bit 7 of the serial I/O2
control register 2 to “1” when SCLK2 is “H” after compl etion of
data transfer. After the next data transfer is started (the transfer
clock falls), bit 7 of the serial I/O2 control register 2 is set to “0”
and the SOUT2 pin is put into the activ e state.
Regardless of the internal clock to external clock, the interrupt
request bit is set after the number of bits (1 to 8 bits) selected by
the optional transfer bit is transferred. In case of a fractional
number of bits less than 8 bits as the last data, the received data
to be stored in the serial I/O2 register becomes a fractional
number of bits close to MSB if the transfer direction selection bit
of serial I/O2 control register 1 is LSB first, or a fractional
number of bits close to LSB if the transfer direction selection bit
is MSB first. For the remaining bits, the previously received data
is shifted.
At transmit operation using the clock synchronous serial I/O, the
SCMP2 signal can be output by comparing the state of the transmit
pin SOUT2 with the state of the receive pin SIN2 in
synchronization with a rise of the transfer clock. If the output
level of the SOUT2 pin is equal to the input level to the SIN2 pin,
“L” is output from the SCMP2 pin. If not, “H” is output. At this
time, an INT2 interrupt request can also be generated. Select a
valid edge by bit 2 of the interrupt edge selection register
(address 003A16).
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)]
0015
16
, 0016
16
The serial I/O2 control registers 1 and 2 are containing various
selection bits for serial I/O2 control as shown in Figure 25.
Fig 25. Structure of Serial I/O2 control registers 1, 2
Serial I/O2 control regi ster 1
(SIO2CON1 : address 001516)
Serial I/O2 control register 2
(SIO2CON2 : address 001616)
b7
Optional transfer bits
b2 b1 b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Not used (returns "0" when rea d)
Serial I/O2 I/O comparison signal control bit
0: P43 I/O
1: SCMP2 output
SOUT2 pin control bit (P01)
0: Output active
1: Output high-impedan ce
Internal synchronous clock selection bits
b2 b1 b0
000:f(X
IN)/8 (f(XCIN)/8 in low-speed mode)
001:f(X
IN)/16 (f(XCIN)/16 in low-speed mode)
010:f(X
IN)/32 (f(XCIN)/32 in low-speed mode)
011:f(X
IN)/64 (f(XCIN)/64 in low-speed mode)
110:f(X
IN)/128 f(XCIN)/128 in low-speed mode)
111:f(X
IN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2, SCLK2 output pin
SRDY2 output enable bit
0: P03 pin is normal I/O pin
1: P03 pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2, P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
b0
b7 b0
Rev.2.13 Apr 17, 2009 Page 29 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 26. Block diagram of Serial I/O2
Fig 27. Timing chart of Serial I/O2
XIN
Serial I/O counter 2 (3)
Serial I/O2 register (8)
Synchronous
circuit
“1”
“0”
“0”
“1”
“0”
“1”
SCLK2
“0”
“1”
Divider
1/8
1/16
1/32
1/64
1/128
1/256
Optional transfer bits (3)
“1”
“0”
XCIN
“10”
“00”
“01”
Data bus
Serial I/O2
interrupt request
Serial I/O2 port selection bit
Serial I/O2 port selection bit
Serial I/O2 synchronous
clock selection bit
SRDY2 output enable bit External clock
Internal synchronous
clock selection bits
P02/SCLK2
P01/SOUT2
P00/SIN2
P02 latch
P01 latch
P03 latch
P03/SRDY2
P43/SCMP2/INT2
Serial I/O2 I/O comparison
signal control bit
P43 latch
QD
Main clock division ratio
selection bits (Note)
Note: Either high-spee d, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Serial I/O2
synchronous clock
selection bit
SRDY2
D7D0D1D2D3D4D5D6
Transfer clock (Note 1)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
Receive enable signal SRDY2
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 interrupt request bit set
Notes1:When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode ) can be sele cted by
setting bits 0 to 2 of serial I/O2 control register 1.
2:When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Rev.2.13 Apr 17, 2009 Page 31 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
PWM (PWM: Pulse Width Modulation)
The 3850 group (spec.A) has a PWM function with an 8-bit
resolution, based on a signal that is the clock input XIN or that
clock input divided by 2.
• Data Setting
The PWM output pin also functions as port P44. Set the PWM
period by the PWM prescaler, and set the “H” term of output
pulse by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255):
PWM period = 255 × (n+1) / f(XIN)
= 31.875 × (n+1) µs
(when f(XIN) = 8 MHz, count source selection bit = “0”)
Output pulse “H” term = PWM period × m / 255
= 0.125 × (n+1) × m µs
(when f(XIN) = 8 MHz, count source selection bit = “0”)
• PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set
to “1”, operation starts by initializing the PWM output circuit,
and pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Fig 29. Timing of PWM period
Fig 30. Block diagram of PWM function
31.875 × m × (n+1)
255 µs
T = [31.875 × (n+1)] µs
PWM outp ut
m : Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz, count source
selection bit = “0”)
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch PWM
register pre-latch
PWM
prescaler latch PWM
register latch
Transfer control circuit
PWM register
1/2
XIN
(XCIN at low-speed mode)
Port P44 latch
PWM function enable bit
Port P44
PWM prescaler
Rev.2.13 Apr 17, 2009 Page 32 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 31. Structure of PWM control register
Fig 32. PWM output timing when PWM register or PWM prescaler is changed
<Notes>
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
b0 PWM control register
(PWMCON : address 001D16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
b7
PWM output
T T T2
B C
PWM register
write signal
PWM prescaler
write signal
(Changes “H” term from “A” to “ B”.)
(Changes PWM period from “T” to “T2”.)
B
TC
T2
=
When the contents of the PWM register or PWM prescaler have changed,
the PWM output will change from the next period after the change.
A
n1+
2×fXIN()
----------------------- sec
n1
+
fXIN()
---------------- sec
Rev.2.13 Apr 17, 2009 Page 33 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
A/D CONVERTER
[AD Conversion Registers (ADL, ADH)] 003516, 003616
The AD conversion registers are read-only registers that store the
result of an A/D conversion. Do not read these registers during
an A/D conversion.
[AD Control Register (ADCON)] 003416
The AD control register controls the A/D conversion process.
Bits 0 to 2 select a specific analog input pin. By setting a value to
these bits, when bit 0 of the AD input selection register (address
003716) is “0”, P30/AN0-P34/AN4 can be selected, and when bit
0 of the AD input selection register is “1”, P04/AN5-P07/AN8 can
be selected.
Bit 4 indicates the completion of an A/D conversion. The value
of this bit remains at “0” during an A/D conversion and changes
to “1” when an A/D conversion e nds. Writing “0” to this bit starts
the A/D conversion.
[AD Input Selection Register (ADSEL)] 003716
The analog input port selection switch bit is assigned to bit 0 of
the AD input selection register. When “0” is set to the analog
input port selection switch bit, P30/AN0-P34/AN4 can be selected
by the analog input pi n selection bits (b2, b1, b0) of the AD
control register (address 003416). When “1” is set to the analog
input port selection switch bit, P04/AN5-P07/AN8 can be selected
by the analog input pi n selection bits (b2, b1, b0) of the AD
control register (address 003416).
• Compari so n Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
• Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4,
P04/AN5 to P07/AN8 and inputs the voltage to the comparator.
• Compa rator and Contro l Circuit
The comparator and control circuit compare an analog input
voltage with the comparison voltage, and the result is stored in
the AD conversion registers. When an A/D conversion is
completed, the control circuit sets the AD conversion completion
bit and the AD interrupt request bit to “1” .
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A/D
conversion.
When the A/D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A/D converter has a built-in self-oscillation circuit.
Fig 33. Structure of AD control register
Fig 34. Structure of AD input selection register
Fig 35. Structure of AD conversion registers
AD control regis ter
(ADCON : address 003416)
Analog input pin selection bits
0 0 0: P30/AN0orP04/AN5
0 0 1: P31/AN1orP05/AN6
0 1 0: P32/AN2orP06/AN7
0 1 1: P33/AN3orP07/AN8
1 0 0: P34/AN4
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7 b0
b2 b1 b0 Note 1 Note 2
Notes 1:This is selected when bit 0 of the AD input selection register
(address 003716) is “0”.
2:This is selected when bit 0 of the AD input selection register
(address 003716) is “1”.
AD input selection register
(ADSEL: address 003716)
Analog input port selection switch bit
0: P30/AN0 to P34/AN4 is selected as
analog input pin.
1: P04/AN5 to P07/AN8 is selected as
analog input pin.
Not used (returns “0” when read)
Fix this bit to “0”.
Not used (returns “0” when read)
Fix this bit to “0”.
b7 b0
8-bit reading (Read only address 003516)
(Address 003516)
10-bit reading
(Read address 0 03 616 before 003516)
(Address 003616)
(Address 003516)
Note :The high-order 6 bits of addr ess 003616 become “0”
at reading.
b7 b0
b9 b8
b7
b7 b0
b6 b5 b4 b3 b2 b1 b0
b9
b7 b0
b8 b7 b6 b5 b4 b3 b2
Rev.2.13 Apr 17, 2009 Page 34 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 36. Block diagram of A/D converter
Channel selector
A/D control circuit
AD conversion low-order register
Resistor ladder
VREF AVSS
Comparator
A/D interrupt request
10
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P04/AN5
P05/AN6
P06/AN7
P07/AN8
b7 b0
3
Data bus
AD control register
(Address 003416)
AD conversion high-order register (Address 003616)
(Address 003516)
AD input selection register
(Address 003716)
b7 b0
Rev.2.13 Apr 17, 2009 Page 35 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit watchdog timer L and an 8-bit watchdog timer H.
• Initial value of watchd og timer
At reset or writing to the watchdog timer control register
(address 003916), each of watchdog timer H and L is set to
“FF16”. Any instruction which generates a write signal such as
the instructions of STA, LDM, CLB and others can be used to
write. The data of bits 6 and 7 are only valid when writing to the
watchdog timer control register. Each of watchdog timer is set to
“FF16” regardless of the written data of bits 0 to 5.
Bit 6 can be written to only once after reset release.
After this bit is written, it cannot rewritten because it is locked.
• Operation of Watchdog Timer
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register. An internal reset
occurs at an underflow of the watchdog timer H. The reset is
released after waiting for a reset release time and the program is
processed from the reset vector address. Accordingly,
programming is usually performed so that writing to the
watchdog timer control register may be started before an
underflow. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
• Bit 6 of Watchdog Timer Control Register
• When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting (Note). When executing the WIT instruction, the
watchdog timer does not stop.
• When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
The required time after writing to the watchdog timer control
register to an underflow of the watchdog timer H is shown as
follows.
When bit 7 of the watchdog timer control register is “0”:
32 s at XCIN = 32.768 kHz frequency and
83.886ms at XIN = 12.5 MHz frequency.
When bit 7 of the watchdog timer control register is “1”:
125 ms at XCIN = 32.768 kHz frequency and
327.68 µs at XIN = 12.5 MHz frequency.
Notes 1. The watchdog timer continues to count for waiting for a stop
mode release time. Do not generate an underflow of the watch-
dog timer H during that time.
2. The watchdog timer cannot be used in the middle-speed mode.
(The internal reset may not be generated correctly, depending on
the underflow timing of the watchdog timer.)
Fig 37. Bl ock diagram of Watchdog timer
Fig 38. Structure of Watchdog timer control register
XIN
Data bus
XCIN
“10”
“00”
“01”
Main clock division
ratio selection bits (Note)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction function selection bit
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
Watchdog timer L (8)
“FF16” is set when
watchdog timer
control register is
written to.
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
STP instruction
RESET
b7
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by exec ution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Watchdog timer control register
(WDTCON : address 003916)
b0
Rev.2.13 Apr 17, 2009 Page 36 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is
returned to an “H” level (the power source voltage must be
between 1.8 V and 5.5 V, and the oscillation must be stable),
reset is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-or der byte)
and address FFFC16 (low-order byte). Make sure that the reset
input voltage is less than 0.28 V for VCC of 1.8 V.
Fig 39. Reset circuit example
Fig 40. Reset sequence
(Note)
0.16VCC
0V
0V
Poweron
VCC
Power source
voltage detection
circuit
Power
source
voltage
Reset
input
voltage
Note : Reset release voltage; VCC = 1.8 V
RESET
VCC
RESET
RESET
Data
φ
Address
SYNC
XIN: 8 to 13 clock cycles
XIN
Notes1:The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 × f(φ).
2:The question marks (?) indicate an undefined state that depends on the previous state.
3:All signals except XIN and RESET are internals.
RESETOUT
? ? ? ? FFFC FFFC ADH,L
??? ADLADH?
Reset address from the vector table.
Rev.2.13 Apr 17, 2009 Page 37 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 41. I nternal status at reset
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P0, P1, P2 pull-upcontrolregister (PULL012)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source selection register (TCSS)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
Address Register contents
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
AD control register (ADCON)
AD conversion low-order register (ADL)
AD conversion high-order register (ADH)
AD input selection register (ADSEL)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Processor status register
Program counter
Address Register contents
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(PCH)
(PCL)
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
FF16
0116
0016
0016
FF16
FF16
FF16
FF16
0016
0016
0016
0016
0016
0016
0016
0016
FFFD16 contents
FFFC16 contents
00010000
XXXXXXXX
XX000000
1
011111
0
01001000
1XXXXXXX
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000111
10000000
11100000
Rev.2.13 Apr 17, 2009 Page 38 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
CLOCK GENERATING CIRCUIT
The 3850 group (spec. A QzROM version) has two built-in
oscillation circuits. An oscillation circuit can be formed by
connecting a resonator between XIN and XOUT (XCIN and
XCOUT). Use the circuit constants in accordance with the
resonator manufacturer ’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip.(An external feed-back resistor may be
needed depending on conditions.) However, an external feed-
back resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit
starts oscilla ting, and XCIN and XCOUT pins function as I/O ports.
• Fr eq uen cy Control
(1) Middle-speed mode
The internal clock φ is the freque ncy of XIN divided by 8. After
reset is released, this mode is selected.
(2) High-spee d mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
(4) Low power di ssipation mode
The low power consumption operation can be realized by
stopping the main clock XIN in low-speed mode. To stop the
main clock, set bit 5 of the CPU mode register to “1”. When the
main clock XIN is restarted (by setting the main clock stop bit to
“0”), set suff ic ient time for oscillation to stabilize .
The sub-clock XCIN-XCOUT oscillating circuit can not directly
input clocks that are generated externally. Accordingly, make
sure to cause an external resonator to oscillate.
<Note>
The internal reset may not be generated correctly in the middle-
speed mode, depending on the underflow timing of the watchdog
timer.
When using the watchdog timer, operate the MCU in any mode
other than the middle-speed mode.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the
oscillation stabilizing time set after STP instruction released bit
(bit 0 of address 00 3816) is “0”, the prescaler 12 is set to “FF16”
and timer 1 is set to “0116”. When the oscillation stabilizing time
set after STP instructi on releas ed bit is “1”, set the sufficient time
for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP
instruction, and the output of the prescaler 12 is connected to
timer 1. Oscillator restarts when an external interrupt is received,
but the internal clock φ is not supplied to the CPU (remains at
“H”) until timer 1 underflows. The internal clock φ is supplied
for the first time, when timer 1 underflows. This ensures time for
the clock oscillation using the ceramic resonators to be
stabilized. When the oscillator is resta rted by reset, apply “L”
level to the RESET pin until the oscillation is stable since a wait
time will not be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ
restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that the interrupts will be received to release the STP
or WIT state, their interrupt enable bits must be set to “1” before
executing of the STP or WIT instruction.
When releasing the STP state, the input of the prescaler and
timer 1 is connected to the count source which had set at
executing the STP instruction and the prescaler 12 and
timer 1 will start counti ng. Set the ti mer 1 interru pt enable
bit to “0” before executing the STP instruction.
<Notes>
• If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient
time is required for the sub-clock to stabilize, especially
immediately after power on and at returning from the stop
mode. When switching the mode between middle/high-speed
and low-speed, set the frequency on condition that f(XIN) > 3 ×
f(XCIN).
• When using the oscillation stabilizing time set after STP
instruction released bit set to “1”, evaluate time to stabilize
oscillation of the used oscillator and set the value to the tim er 1
and prescaler 12.
Fig 42. Ceramic re sonator circuit
Fig 43. External clock input circuit
CIN COUT
CCIN CCOUT
Rf Rd Rd (Note)
Notes : Insert a damping resistor if required.
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet specifies
to add a feedback resistor externally to the chip though a
feedback resistor exists on-chip , insert a feedb ack
resistor between XIN and XOUT following the instruction.
XCIN XCOUT XIN XOUT
XIN XOUT
External oscillation
circuit
VCC
VSS
Open
CCIN CCOUT
Rf Rd
XCIN XCOUT
Rev.2.13 Apr 17, 2009 Page 39 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
[MISRG (MISRG)] 003816
MISRG consists of three control bits (bits 1 to 3) for middle-
speed mode automatic switch and one control bit (bit 0) for
oscillation stabilizing time set after STP instruction relea s ed.
By setting the middle-speed mode automatic switch start bit to
“1” while operating in the low-speed mode and setting the
middle-speed mode automatic switch set bit to “1”, XIN
oscillation automatically starts and the mode is automatically
switched to the middle-speed mode.
Fig 44. Structure of MISRG
Fig 45. System clock genera ting circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 6.5 to 7.5 machine cycles
1: 4.5 to 5.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
b7 b0
Note: When the mode is automatically switched from the low-speed mode to the
middle-speed mode, the value of CPU mode register (address 003B16)
changes.
WIT
instruction STP
instruction
Timing φ (internal clock)
S
R
Q
S
R
Q
Main clock stop bit
S
R
Q
1/2 1/4
XIN XOUT
XCOUT
XCIN
Interrupt request
Interrupt disable flag lReset
1/2
Port XC
switch bit
“1” “0”
low-speed mode
High-speed or
middle-speed mode
Middle-speed mo de
High-speed or
Low-speed mode
Main clock division ratio
selection bits (Note 1)
Main clock division ratio
selection bits (Note 1)
Notes1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port XC switch bit (b4) to “1”.
2:f(X
IN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as th
e
count source at executing STP instruction.
3: When bit 0 of MISRG = “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”.
When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Prescaler 12 Timer 1
Reset or
STP instruction
(Note 2)
Reset
(Note 3)
Timer 12 count
source selection bit
(Note 4)
STP
instruction
Rev.2.13 Apr 17, 2009 Page 40 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 46. State transitions of system clock
CM4 : Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN-XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
00 :φ = f(XIN)/2 (High-speed mode)
01 :φ = f(XIN)/8 (Middle-speed mode)
10 :φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Reset
CM4
“1”←→”0”
CM
4
“0”←→”1”
CM
6
“1”←→”0”
CM
4
“1”←→”0”
CM
6
“1”←→”0”
CM7
“1”←→”0” CM4
“1”←→”0”
CM5
“1”←→”0”
CM6
“1”←→”0”
CM6
“1”←→”0”
CPU mode register
(CPUM : address 003B16)
b7 b4
CM
7
“0”←→”1”
CM
6
“1”←→”0”
High-speed mode
(f(φ) = 4 MHz)
CM7=0
CM6=0
CM5=0 (8 MHz oscillating)
CM4=0 (32 kHz stopped)
High-speed mode
(f(φ) = 4 MHz)
CM7=0
CM6=0
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer operates in the wait mode.
4: After STP instruction is released, the count source which had set by bit 2 (timer 12 count source selection bit) of the timer count source set register
at executing the STP instruction is supplied to timer 1. Accordingly, when bit 0 of MISRG is “0” and the timer 12 count source selection bit is “0”
(f(XIN)/16 or f(XCIN)/16), a delay of approximately 1 ms occurs automatically in the high/middle-speed mode. A delay of approximately 256 ms
occurs automatically in the l o w-speed mode (at f(XIN) = 8 MHz, f(XCIN) = 32 kHz). When the timer 12 count source selection bit is “1” (f(XCIN)), a
delay of approximately 16 ms occurs regardless of the operation mode .
5: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode .
6: When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set b y the
middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the midd le-speed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Middle-speed mode
automatic switch start bit
“1”
Middle-speed mode
automatic switch set bit
“1”
Middle-speed mode
(f(φ) = 1 MHz)
CM7=0
CM6=1
CM5=0 (8 MHz oscillating)
CM4=0 (32 kHz stopped)
Middle-speed mode
(f(φ) = 1 MHz)
CM7=0
CM6=1
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
Low-speed mode
(f(φ) = 16 kHz)
CM7=1
CM6=0
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
Low-speed mode
(f(φ) = 16 kHz)
CM7=1
CM6=0
CM5=1 (8 MHz stopped)
CM4=1 (32 kHz oscillating)
Rev.2.13 Apr 17, 2009 Page 41 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
NOTES:
1. The rating becomes 300mW at the PRSP0042GA-A/B package.
Table 9 Absolute maximum ratings
Symbol Parameter Conditions Ratings Unit
VCC Power source voltage All voltages are based on VSS.
When an input voltage is
measured, output transistors
are cut off.
−0.3 to 6.5 V
VIInput voltage P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44,
VREF
−0.3 to VCC + 0.3 V
VIInput voltage P22, P23−0.3 to 5.8 V
VIInput voltage RESET, XIN −0.3 to VCC + 0.3 V
VIInput voltage CNVSS −0.3 to 8.0 V
VOP00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44,
XOUT
−0.3 to VCC + 0.3 VOutput voltage
VOOutput voltage P22, P23−0.3 to 5.8 V
PdPower dissipation Ta=25°C1000(1) mW
Topr Operating temperature −−20 to 85 °C
Tstg Storage temperature −−40 to 125 °C
Rev.2.13 Apr 17, 2009 Page 42 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Recommended operating conditions
NOTES:
1. When the A/D converter is used, refer to the recommended operating condition for A/D conversion.
2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating
temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
3. When the oscillation frequency has a duty cycle of 50%.
4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Table 10 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter Conditions Limits Unit
Min. Typ. Max.
VCC Power source voltage(1) When start oscillating(2) 2.0 5.0 5.5 V
High-speed mode
f(φ) = f(XIN)/2 f(XIN) ≤ 12.5 MHz 4.0 5.0 5.5 V
f(XIN) ≤ 6.0 MHz 2.7 5.0 5.5 V
f(XIN) ≤ 4.2 MHz 2.2 5.0 5.5 V
f(XIN) ≤ 2.1 MHz 2.0 5.0 5.5 V
Middle-speed mode
f(φ) = f(XIN)/8 f(XIN) ≤ 12.5 MHz 2.7 5.0 5.5 V
f(XIN) ≤ 8.4 MHz 2.2 5.0 5.5 V
f(XIN) ≤ 4.2 MHz 1.8 5.0 5.5 V
Low-speed mode
f(φ) = f(XCIN)/2 f(XCIN) ≤ 50 kHz 1.8 5.0 5.5 V
VSS Power source voltage 0V
VIH “H” input voltage
P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44
1.8 ≤ VCC < 2.7 V 0.85 VCC VCC V
2.7 ≤ VCC < 5.5 V 0.8 VCC VCC
VIH “H” input voltage
P22, P231.8 ≤ VCC < 2.7 V 0.85 VCC 5.8 V
2.7 ≤ VCC ≤ 5.5 V 0.8 VCC 5.8
VIH “H” input voltage
RESET, XIN 1.8 ≤ VCC < 2.7 V 0.85 VCC VCC V
2.7 ≤ VCC ≤ 5.5 V 0.8 VCC VCC
VIH “H” input voltage
CNVSS 1.8 ≤ VCC < 2.7 V 0.85 VCC 8.0 V
2.7 ≤ VCC ≤ 5.5 V 0.8 VCC 8.0
VIL “L” input voltage
P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44
1.8 ≤ VCC < 2.7 V 0 0.16 VCC V
2.7 ≤ VCC ≤ 5.5 V 0 0.2 VCC
VIH “H” input voltage
P22, P231.8 ≤ VCC < 2.7 V 0 0.16 VCC V
2.7 ≤ VCC ≤ 5.5 V 0 0.2 VCC
VIL “L” input voltage
RESET 1.8 ≤ VCC < 2.7 V 0 0.16 VCC V
2.7 ≤ VCC ≤ 5.5 V 0 0.2 VCC
VIL “L” input voltage
XIN 1.8 ≤ VCC < 2.7 V 0 0.16 VCC V
VIL “L” input voltage
CNVSS 1.8 ≤ VCC < 2.7 V 0 0.16 VCC V
2.7 ≤ VCC ≤ 5.5 V 0 0.2 VCC
f(XIN) Main clock input oscillation
frequency(3) High-speed mode
f(φ) = f(XIN)/2
4.0 ≤ VCC ≤ 5.5 V 12.5 MHz
2.7 ≤ VCC ≤ 5.5 V 6.0 MHz
2.2 ≤ VCC ≤ 5.5 V 4.2 MHz
2.0 ≤ VCC ≤ 5.5 V 2.1 MHz
Middle-speed mode
f(φ) = f(XIN)/8
2.7 ≤ VCC ≤ 5.5 V 12.5 MHz
2.2 ≤ VCC ≤ 5.5 V 8.4 MHz
1.8 ≤ VCC ≤ 5.5 V 4.2 MHz
f(XCIN)Sub-clock input oscillation frequency(3, 4) 32.768 50 kHz
Rev.2.13 Apr 17, 2009 Page 43 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
NOTES:
1. The peak output current is the peak current flowing in each port.
2. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
Table 11 Recommended operatin g conditions (2) (VCC = 1.8 to 5.5 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
IOH(peak) “H” peak output current(1) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34,
P40-P44
−10 mA
IOL(peak) “L” peak output current(1) P00-P07, P20-P27, P30-P34, P40-P4410 mA
IOL(peak) “L” peak output current(1) P10-P1720 mA
IOH(avg) “H” average output current(2) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34,
P40-P44
−5mA
IOL(avg) “L” average output current(2) P00-P07, P20-P27, P30-P34, P40-P445mA
IOL(avg) “L” average output current(2) P10-P1715 mA
ΣIOH(peak) “H” total peak output current(3) P00-P07, P10-P17, P30-P34−80 mA
ΣIOH(peak) “H” total peak output current(3) P20, P21, P24-P27, P40-P44,−80 mA
ΣIOL(peak) “L” total peak output current(3) P00-P07, P30-P3480 mA
ΣIOL(peak) “L” total peak output current(3) P10-P17120 mA
ΣIOL(peak) “L” total peak output current(3) P20-P27, P40-P4480 mA
ΣIOH(peak) “H” total average output current(3) P00-P07, P10-P17, P30-P34−40 mA
ΣIOH(peak) “H” total average output current(3) P20, P21, P24-P27, P40-P44−40 mA
ΣIOL(avg) “L” total average output current(3) P00-P07, P30-P3440 mA
ΣIOL(avg) “L” total average output current(3) P10-P1760 mA
ΣIOL(avg) “L” total average output current(3) P20-P27, P40-P4440 mA
Rev.2.13 Apr 17, 2009 Page 44 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Electrical characteristics
NOTES:
1. P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Table 12 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
VOH “H” output voltage(1)
P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44
IOH = −10 mA
4.0 ≤ VCC ≤ 5.5 V VCC − 2.0 V
IOH = –1.0 mA
1.8 ≤ VCC ≤ 5.5 V VCC − 1.0
VOL “L” output voltage
P00-P07, P20-P27, P30-P34, P40-P44IOL = 10 mA
4.0 ≤ VCC ≤ 5.5 V 2.0 V
IOL = 1.0 mA
1.8 ≤ VCC ≤ 5.5 V 1.0
VOL “L” output voltage
P10-P17IOL = 20 mA
4.0 ≤ VCC ≤ 5.5 V 2.0 V
IOL = 10 mA
2.7 ≤ VCC ≤ 5.5 V 1.0
IOL = 1.6 mA
1.8 ≤ VCC ≤ 5.5 V 1.0
VT+ − VT−Hysteresis
CNTR0, CNTR1, INT0-INT30.4 V
VT+ − VT−Hysteresis
RxD, SCLK1, SCLK2, SIN2 0.5 V
VT+ − VT−Hysteresis
RESET 0.5 V
IIH “H” input current
P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44
VI = VCC
Pin floating,
Pull-up Transistor “off”
5.0 µA
IIH “H” input current
RESET, CNVSS VI = VCC 5.0 µA
IIH “H” input current
XIN VI = VCC 4.0 µA
IIL “L” input current
P00-P07, P10-P17, P20-P27
P30-P34, P40-P44
VI = VSS
Pin floating,
Pull-up Transistor “off”
−5.0 µA
IIL “L” input current
RESET, CNVSS VI = VSS −5.0 µA
IIL “L” input current
XIN VI = VSS −4.0 µA
IIL “L” input current (at Pull-up)
P00-P07, P10-P17, P20, P21,
P24-P27, P30-P34, P40-P44
VI = VSS
VCC = 5.0 V −25 −60 −120 µA
VI = VSS
VCC = 3.0 V −8−22 −40 µA
VRAM RAM hold voltage When clock stopped 1.8 V
Rev.2.13 Apr 17, 2009 Page 45 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
NOTES:
1. Output transistors are cut off.
Table 13 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
ICC Power source
current High-speed mode(1) f(XIN) = 12.5 MHz
f(XCIN) = 32.768 kHz 6.0 13.0 mA
f(XIN) = 8.0 MHz
f(XCIN) = 32.768 kHz 4.3 10.0 mA
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = 32.768 kHz 1.8 4.5 mA
f(XIN) = 8.0 MHz (in WIT state)
f(XCIN) = 32.768 kHz 1.4 4.2 mA
Middle-speed mode(1) f(XIN) = 12.5 MHz
f(XCIN) = stopped 2.8 7.0 mA
f(XIN) =8.0 MHz
f(XCIN) = stopped 2.0 6.5 mA
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = stopped 1.8 4.2 mA
f(XIN) = 8.0 MHz (in WIT state)
f(XCIN) = stopped 1.3 4.0 mA
Low-speed mode
(VCC = 5.0 V)(1) f(XIN) = stopped
f(XCIN) = 32.768 kHz 75 200 µA
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state) 65 100 µA
Low-speed mode
(VCC = 3.0 V)(1) f(XIN) = stopped
f(XCIN) = 32.768 kHz 15 55 µA
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state) 10 20 µA
Increment when A/D conversion is executed 300 µA
All oscillation stopped
(in STP state)(1) Ta = 25 °C 0.1 1.0 µA
Ta = 85 °C 10 µA
Rev.2.13 Apr 17, 2009 Page 46 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
A/D converter recommended operating co nditions
A/D converter char acteristics
Table 14 A/D converter recommended operating conditions
(VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = −20 to 85 °C, unless otherwise not ed)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
VCC Power source voltage
(When A/D converter is used) 2.2 5.0 5.5 V
VREF A/D convert reference voltage 2.0 VCC V
AVSS Analog power source voltage 0 V
VIA Analog input voltage AN0-AN8AVSS VCC V
f(XIN) Main clock input oscillation frequency
(When A/D converter is used) High-speed mode
f(φ) = f(XIN)/2 4.0 ≤ VCC ≤ 5.5 V 0.5 12.5 MHz
2.7 ≤ VCC ≤ 5.5 V 0.5 6.0 MHz
2.2 ≤ VCC ≤ 5.5 V 0.5 4.2 MHz
Middle-speed mode
f(φ) = f(XIN)/8 2.7 ≤ VCC ≤ 5.5 V 0.5 12.5 MHz
2.2 ≤ VCC ≤ 5.5 V 0.5 8.4 MHz
Table 15 A/D converter characteristics
(VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = −20 to 85 °C, unless otherwise not ed)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
−Resolution 10 bit
−Absolute accuracy 2.2 ≤ VCC < 2.7 V ±5 LSB
2.7 ≤ VCC ≤ 5.5 V ±4 LSB
tCONV Conversion time High-speed mode, Middle-speed mode 61 2tc(XIN)
Low-speed mode 40 µs
RLADDER Ladder resistor 35 kΩ
IVREF Reference power source input current VREF = 5.0 V VREF “on” 50 150 200 µA
VREF = 5.0 V VREF “off” 5.0 µA
II(AD) A/D port input current 0.5 5.0 µA
Rev.2.13 Apr 17, 2009 Page 47 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Timing Requirements
NOTES:
1. When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
NOTES:
1. When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Table 16 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tW(RESET) Reset input “L” pulse width 20 XIN cycle
tC(XIN) External clock input cycle time 80 ns
tWH(XIN) External clock input “H” pulse width 32 ns
tWL(XIN) External clock input “L” pulse width 32 ns
tC(CNTR) CNTR0, CNTR1 input cycle time 200 ns
tWH(CNTR) CNTR0, CNTR1 input “H” pulse width 80 ns
tWL(CNTR) CNTR0, CNTR1 input “L” pulse width 80 ns
tWH(INT) INT0 to INT3 input “H” pulse width 80 ns
tWL(INT) INT0 to INT3 input “L” pulse width 80 ns
tC(SCLK1)Serial I/O1 clock input cycle time(1) 800 ns
tWH(SCLK1)Serial I/O1 clock input “H” pulse width(1) 370 ns
tWL(SCLK1)Serial I/O1 clock input “L” pulse width(1) 370 ns
tsu(RxD-SCLK1) Serial I/O1 input setup time 220 ns
th(SCLK1-RxD) Serial I/O1 input hold time 100 ns
tC(SCLK2) Serial I/O2 clock input cycle time 1000 ns
tWH(SCLK2) Serial I/O2 clock input “H” pulse width 400 ns
tWL(SCLK2) Serial I/O2 clock input “L” pulse width 400 ns
tsu(SIN2-SCLK2) Serial I/O2 clock input setup time 200 ns
th(SCLK2-SIN2) Serial I/O2 clock input hold time 200 ns
Table 17 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tW(RESET) Reset input “L” pulse width 20 XIN cycle
tC(XIN) External clock input cycle time 166 ns
tWH(XIN) External clock input “H” pulse width 66 ns
tWL(XIN) External clock input “L” pulse width 66 ns
tC(CNTR) CNTR0, CNTR1 input cycle time 500 ns
tWH(CNTR) CNTR0, CNTR1 input “H” pulse width 230 ns
tWL(CNTR) CNTR0, CNTR1 input “L” pulse width 230 ns
tWH(INT) INT0 to INT3 input “H” pulse width 230 ns
tWL(INT) INT0 to INT3 input “L” pulse width 230 ns
tC(SCLK1)Serial I/O1 clock input cycle time(1) 2000 ns
tWH(SCLK1)Serial I/O1 clock input “H” pulse width(1) 950 ns
tWL(SCLK1)Serial I/O1 clock input “L” pulse width(1) 950 ns
tsu(RxD-SCLK1) Serial I/O1 input setup time 400 ns
th(SCLK1-RxD) Serial I/O1 input hold time 200 ns
tC(SCLK2) Serial I/O2 clock input cycle time 2000 ns
tWH(SCLK2) Serial I/O2 clock input “H” pulse width 950 ns
tWL(SCLK2) Serial I/O2 clock input “L” pulse width 950 ns
tsu(SIN2-SCLK2) Serial I/O2 clock input setup time 400 ns
th(SCLK2-SIN2) Serial I/O2 clock input hold time 300 ns
Rev.2.13 Apr 17, 2009 Page 48 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Switching characteristics
NOTES:
1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2. When the P0
1
/S
OUT2
and P0
2
/S
CLK2
P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 0015
16
) is “0”.
3. The XOUT pin is excluded.
NOTES:
1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2. When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0” .
3. The XOUT pin is excluded.
Fig 47. Circuit for measuring output switching characteristics
Table 18 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
tWH(SCLK1)Serial I/O1 clock output “H” pulse width Fig. 47 tC(SCLK1)/2−30 ns
tWL(SCLK1)Serial I/O1 clock output “L” pulse width tC(SCLK1)/2−30 ns
td(SCLK1-TXD) Serial I/O1 output delay time(1) 140 ns
tV(SCLK1-TXD) Serial I/O1 output valid time(1) −30 ns
tr(SCLK1)Serial I/O1 clock output rising time 30 ns
tf(SCLK1)Serial I/O1 clock output falling time 30 ns
tWH(SCLK2)Serial I/O2 clock output “H” pulse width tC(SCLK2)/2−160 ns
tWL(SCLK2)Serial I/O2 clock output “L” pulse width tC(SCLK2)/2−160 ns
td(SCLK2-SOUT2)Serial I/O2 output delay time(2) 200 ns
tV(SCLK2-SOUT2)Serial I/O2 output valid time(2) 0ns
tf(SCLK2)Serial I/O2 clock output falling time 30 ns
tr(CMOS) CMOS output rising time(3) 10 30 ns
tf(CMOS) CMOS output falling time(3) 10 30 ns
Table 19 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted)
Symbol Parameter Test conditions Limits Unit
Min. Typ. Max.
tWH(SCLK1)Serial I/O1 clock output “H” pulse width Fig. 47 tC(SCLK1)/2−50 ns
tWL(SCLK1)Serial I/O1 clock output “L” pulse width tC(SCLK1)/2−50 ns
td(SCLK1-TXD) Serial I/O1 output delay time(1) 350 ns
tV(SCLK1-TXD) Serial I/O1 output valid time(1) −30 ns
tr(SCLK1)Serial I/O1 clock output rising time 50 ns
tf(SCLK1)Serial I/O1 clock output falling time 50 ns
tWH(SCLK2)Serial I/O2 clock output “H” pulse width tC(SCLK2)/2−240 ns
tWL(SCLK2)Serial I/O2 clock output “L” pulse width tC(SCLK2)/2−240 ns
td(SCLK2-SOUT2)Serial I/O2 output delay time(2) 400 ns
tV(SCLK2-SOUT2)Serial I/O2 output valid time(2) 0ns
tf(SCLK2)Serial I/O2 clock output falling time 50 ns
tr(CMOS) CMOS output rising time(3) 20 50 ns
tf(CMOS) CMOS output falling time(3) 20 50 ns
Measurement output pin
100pF
CMOS output
Rev.2.13 Apr 17, 2009 Page 49 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 48. Timing diagram
tC(CNTR) tWL(CNTR)
tWH(CNTR)
0.8VCC 0.2VCC
CNTR0
CNTR1
INT0 to INT3
XIN
tWL(INT)tWH(INT)
0.8VCC 0.2VCC
0.8VCC
0.2VCC
tW(RESET)
tC(XIN)tWL(XIN)
tWH(XIN)
0.8VCC 0.2VCC
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
0.8VCC
0.2VCC
tWH(SCLK1), tWH(SCLK2)
tftf
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)th(SCLK1-RXD),
th(SCLK2-SIN2)
td(SCLK1-TXD), td(SCLK2-SOUT2)tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
0.2VCC
0.8VCC
SCLK1
SCLK2
RXD
SIN2
TXD
SOUT2
RESET
Rev.2.13 Apr 17, 2009 Page 50 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
*3*3
*2
*1
SEATING PLANE
22
21
1
42
b
2
b
p
b
3
D
e
AL
A
2
A
1
E
c
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
INCLUDE TRIM OFFSET.
2.0281.528
5.5
A1
b3
15°
e1.778
c
L3.0
0.51
0.9 1.0 1.3
A
E12.85 13.0 13.15
D36.5 36.7 36.9
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.22 0.27 0.34
P-SDIP42-13x36.72-1.78 4.1g
MASS[Typ.]
42P4BPRDP0042BA-A
RENESAS CodeJEITA Package Code Previous Code
bp0.35 0.45 0.55
15.2414.94 15.54
b20.63 0.73 1.03
A23.8
0°
e1
e
1
b
p
A
1
H
E
y0.15
e0.8
c
0°10°
L0.3 0.5 0.7
0.05
A2.4
11.63 11.93 12.23
A
2
2.0
E8.2 8.4 8.6
D17.3 17.5 17.7
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.25 0.3 0.4
0.13 0.15 0.2
P-SSOP42-8.4x17.5-0.80 0.6g
MASS[Typ.]
42P2R-EPRSP0042GA-B
RENESAS CodeJEITA Package Code Previous Code
0.65 0.95
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
121
2242
F
*1
*2
*3
E
H
E
D
ebp
A
c
Detail F
A2
L
A1
Rev.2.13 Apr 17, 2009 Page 51 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a
reset.
In particular, it is essential to initialize the T and D flags becaus e
they have an important effect on calculations.
<Reason>
After a re set, the c ont ents of the proc esso r sta tus re gist er (PS) are
undefined except for the I flag which is “1”.
Fig 49. Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS),
execute the PHP ins tructio n once the n read the co nten ts of (S+1).
If necessary, execute the PLP instruction to return the PS to its
original status.
Fig 50.
Stack memory conten ts after PHP instruction execution
2. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following
conditions satisfied, the interrupt execution is started from the
address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
3. D ecimal calcu lations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield
proper decimal notation, set the decimal mode flag (D) to “1”
with the SED instruction. After executing the ADC or SBC
instruction, execute another instruction before executing the
SEC, CLC, or CLD instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected , the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC
or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the
calculation, or is cleared to “0” if a borrow is generated. To
determine whether a calculati on has generated a carry, the C flag
must be initialized to “0” before each calcula tion. To chec k for a
borrow, the C flag must be initialized to “1” before each ca lculation .
Fig 51. Execution of decimal calculations
4. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
5. Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
• The execution of these instructions does not change the
contents of the processor status register.
6. Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction
register as an inde x
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
to a direction register.
Use instructions such as LDM and STA, etc., to set the port
direction registers.
7. In struction Execution Time
The instruction execution time can be obtained by multiplying
the frequency of the internal clock
φ
by the number of cycles
mentioned in the 740 Family Software Manual.
The frequency of the i nternal clock
φ
is the twice the XIN cyc le in
high-speed mode, 8 times the XIN cycle in middle-speed mode,
and the twice the XCIN in low-speed mode.
8. Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
9. CPU Mode Registe r
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
Reset
Initializing of flags
Main program
Stored PS
(S)
(S) + 1
Set D flag to “1”
ADC or SBC instruction
NOP instruction
SEC, CLC, or CLD instruction
Rev.2.13 Apr 17, 2009 Page 52 of 56
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NOTES ON PERIPHERAL FUNCTIONS
Notes on Input and Output Ports
1. Notes in standby state
In standby state*1, do not make input levels of an I/O port
“undefined”, especially for I/O ports of the N-channel open-
drain. When setting the N-channel o pen-drain po rt as an output ,
do not make input levels of an I/O port “undefined”, too.
Pull-up (connect the port to VCC) or pull-down (connect the port
to VSS) these ports through a resistor.
When determining a re sistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
<Reason>
When setting as an input port with its direction register, the
transistor becomes the OFF state, which causes the ports to be
the high-impedance state.
Accordingly, the potent ial which is input to the input buffer in a
microcomputer is unstable in the state that input levels of an I/O
port are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the
port latch are “1”, even if it is set as an output port with its
direction register, it becomes the same phenomenon as the case
of an input port.
NOTES:
4. Standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
2. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit
managing instruction*2, the value of the unspecified bit may be
changed.
<Reason>
The bit managing instructions are read-modify-write form
instructions for reading and writing data by a byte unit.
Accordingly, when these instructions are executed on a bit of the
port latch of an I/O port, the following is executed to all bits of
the port latch.
• As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after
bit managing.
• As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after
bit managing.
Note the following:
• Even when a port which is set as an output port is changed for
an input port, its port latch holds the output data.
• As for a bit of which is set for an input port, its value may be
changed even when not specified with a bit managing
instruction in case where the pin state differs from its port
latch contents.
NOTES:
5. Bit managing instructions: SEB and CLB instructions
Termination of Unused Pins
1. Terminate unused pins
(1) I/O ports:
• Set the I/O ports for the input mode and connect them to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ. In the port
which can select a internal pull-up resistor, the internal pull-up
resistor can be used.
Set the I/O ports for the output mode and open them at “L” or
“H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched
over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source
current may increase in the input mode. With regard to an
effects on the system, thoroughly perform system evaluation
on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
(2) The AVSS pin when not using the A/D converter:
• When not using the A/D converter, handle a power source pin
for the A/D converter, AVSS pin as follows:
AVSS: Connect to the VSS pin.
2. Termination remarks
(1) Input ports and I/O ports:
Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first-
stage circuit.
• An effect due to noise may be easily produced as compared
with proper termination (1) in 1 shown on the above.
(2) I/O ports:
When setting for the input mode, do not connect to VCC or VSS
directly.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between a port and VCC (or VSS).
(3) I/O ports:
When setting for the input mode, do not connect multiple ports in
a lump to VCC or VSS through a resistor.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between ports.
• At the termination of unused pins, perform wiring at the
shortest possible distance (20 mm or less) from
microcomputer pins.
Rev.2.13 Apr 17, 2009 Page 53 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Notes on Interrupts
1. Cha ng e of relevant register settings
When the setting of the following registers or bits is changed, the
interrupt request bit may be set to “1”. When not requiring the
interrupt occurrence synchronized with these setting, take the
following sequence.
• Interrupt edge selection register (address 003A16)
• Timer XY mode register (address 002316)
Set the above listed registers or bits as the following sequence.
Fig 52. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit may be set
to “1”.
• When setting external interrupt active edge
Concerned register:Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated.
Concerned register: Interrupt edge selection register (address
003A16)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt
request bit of an interrupt request register immediately after this bit
is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Fig 53. Sequence o f check of interrupt request bit
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit of an interrupt request register is cleared to
“0”, the value of the interrupt request bit before being cleared to
“0” is read.
3. In terrupt Request Register 1
Be sure to fix bits 1and 5 of the Interrupt request register 1
(address 003C16) to “0”.
Notes on Timer
• If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
• When switching the count source by the timer 12, X and Y
count source selection bits, the value of ti mer count is altered
in unconsiderable amount owing to generating of thin pulses in
the count input signals.
Therefore, select the timer count source before set the value to
the prescaler and the time r.
Notes on Serial Interface
1. Notes when selecting clock synchronous serial I/O
(Serial I/O1)
(1) Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0”
(Serial I/O1 and transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disa ble d ), or cl ear the
serial I/O1 enable bit to “0” (Serial I/O1 disabled).
(3) Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0”
simultaneously (transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception
cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and
reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission circuit
does not stop by clearing only the transmit enable bit to “0”
(transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O1 enable bit to “0” (Serial
I/O1 disabled) (refer to (1) in 1).
(4) SRDY1 output of reception side (Serial I/O1)
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
Set the interrupt edge select bit (active edge switch bit)
or the interrupt (source) select bit to “1”.
NOP (one or more instructions)
Set the corresponding interrupt enable bit to “0” (disabled).
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
Set the corresponding interrupt enable bit to “1” (enabled).
*Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
NOP (one or more instructions)
Clear the interrupt request bit to “0” (no interrupt issued)
Execute the BBC or BBS instruction
Rev.2.13 Apr 17, 2009 Page 54 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
2. N otes when selecting clock asy nchronous serial I/O
(Serial I/O1)
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transm it disa bled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receiv e disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transm it disa bled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to
“0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O1
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receiv e disabled).
3. Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission
and the reception circuits are re set by clearing both the transmit
enable bit and the receive enable bit to “0”.
Fig 54. Sequence of setting serial I/O1 control register
again
4. Data transmission control with referring to transmit
shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
5. Transmit interrupt request when transmit enable bit
is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt
enable bit to transmit enabled as shown in the following
sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB
instruction.
(2) Prepare serial I/O for transmission/reception .
(3) Set the interrupt request bit to “0” with CLB instruction
after 1 or more instruction has been executed.
(4) Set the interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable b it is set to “ 1”, the tr ansmit buf fer
empty flag and transmit shift register completion flag are set to
“1”.
The interrupt request is generated and the transmission interrupt
request bit is set re gardless of which of the two timings listed
below is selected as the timing for the transmission interrupt to
be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register com pletion flag is set to “1”
6. Transmission control when external clock is
selected (Serial I/O1 clock synchr on ou s mode)
When an external clock is used as the synchron ous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
SCLK1 input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the SCLK1 input
level.
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial
I/O2 register (serial I/O shift register) at “ H” of the transf er c lock
input level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and
“L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n + 1
2 × f(XIN) (s) (Count source selection bit = “0”,
where n is the value set in the prescaler)
n + 1
f(XIN) (s) (Count sou rce selection bit = “1”,
where n is the value set in the prescaler)
Can be set with the
LDM instruction at
the same time
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “ 0”
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
Rev.2.13 Apr 17, 2009 Page 55 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Notes on A/D Converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01
µ
F to 1
µ
F.
Further, be sure to verify the operation o f application produ cts on
the user side.
<Reason>
An analog input p in includes the capacitor for analog voltage
comparison. Accordingly, when signals from signal source with
high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion
precision to be worse.
2. A/D converter power source pin
The AVSS pin is A/D converter power source pin. Regardless of
using the A/D conversion function or not, connect it as following:
•AV
SS: Connect to the VSS line
<Reason>
If the AVSS pin is opened, the microcomputer may have a failure
because of noise or others.
3. Clock frequency durin g A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity wi ll be lost if the clock frequency is too low. Thus,
make sure the following during an A/D conversion.
•f(X
IN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A/D converter is operated at low-speed mode,
f(XIN) do not have the lower limit of frequency, because of the
A/D converter has a built-in self-oscillation circuit.
4. AD Input Selection Register
Be sure to fix bits 5 and 7 of the AD input selection register
(address 003716) to “0”.
Notes on Watchdog Timer
• Make sure that the watchdog timer does not underflow while
waiting Stop release, because the watchdog timer keeps
counting during that term.
• When the STP instruction function selection bit has be en set to
“1”, it is impossible to switc h it to “0” by a program.
• The watchdog timer cannot be used in the middle-speed mode.
(The internal reset may not be generated correctly, depending
on the underflow timing of the watchdog timer.)
Notes on RESET Pin
1. C on necting capacitor
In case where the RESET signal rise time is long, connect a
ceramic capacitor or others across the RESET pin and the VSS pin.
Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following:
• Make the length of the wiring which is connected to a
capacitor as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer
failure.
2. Reset release after power on
When releasing the reset after power on, such as power-on reset,
release reset after XIN passes more than 20 cycles in the state
where the power supply voltage is 1.8 V or more and the XIN
oscillation is stable.
<Reason>
To release reset, the RESET pin must be held at an “L” level for
20 cycles or more of XIN in the state where the power source
voltage is between 1.8 V and 5.5 V, and XIN oscillation is stable.
Notes on Using Stop Mode
1. Register setting
Since values of the prescaler 12 and Timer 1 are automati cally
reloaded when returning from the stop mode, set them again,
respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
When using the oscillation stabilizing time set after STP
instruction released bit set to “1”, evaluate time to stabilize
oscillation of the used oscillator and set the value to the timer 1
and prescaler 12.
2. Clock restoration
After restoration from the stop mode to the normal mode by an
interrupt request, the contents of the CPU mode register previous
to the STP instruction execution are retained. Accordingly, if
both main clock and sub clock were oscillating before execution
of the STP instruction, the oscillation of both clocks is resumed
at restoration.
In the above case, when the main clock side is set as a system
clock, the oscillation st abilizing time for approximately 8,000
cycles of the XIN input is reserved at restoration from the stop
mode. At this time, note that the oscillation on the sub clock side
may not be stabilized even after the lapse of the oscillation
stabilizing time of the main clock side.
Notes on W a it Mode
• Clock restoration
If the wait mode is released by a reset when XCIN is set as the
system clock and XIN oscillation is stopped during execution of
the WIT instruction, XCIN oscillation stops, XIN oscillations
starts, and XIN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the
oscillation is stabi lized.
Notes on Restarting Oscillation
• Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP
instruction and the STP instruction has been released by an
external interrupt source, the fixed values of Timer 1 and
Prescaler 12 (Timer 1 = “0116”, Prescaler 12 = “FF16”) are
automatically reloaded in order for the oscillation to stabiliz e.
The user can inhibit the automatic setting by writing “1” to bit 0
of MISRG (address 003816).
However, by setting this bit to “1”, the previous values, set just
before the STP instruction was executed, will remain in Timer 1
and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation
stabilizing time, before executing the STP instruction.
<Reason>
Oscillation will restart when an external interrupt is received.
However, internal clock
φ
is supplied to the CPU only when
Timer 1 starts to underflow. This ensures time for the clock
oscillation using the ceramic resonators to be stabilized.
Rev.2.13 Apr 17, 2009 Page 56 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin) and between power
source pin (VCC pin) and analog power source inpu t pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the
pins to be connected, a ceramic capacitor of 0.01
µ
F–0.1
µ
F is
recommended.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less
than the recommended operating conditions and design a system
not to cause errors to the system by this unstable operation.
Electric Characteristic Differences Between Flash
Memory, Mask ROM and QzROM Version MCUs
There are differences in the manufacturing processes and t he
mask pattern among f lash memory, mask ROM, and QzROM
version MCUs due to the differences of the ROM type. Even
when the ROM type is the same, when the memory size is
different, the manufacturing processes and the mask pattern
differ. For these reasons, the oscillation circuit constants and the
characteristics such as a characteristic value, operation margin,
noise immunity, and noise radiation within t he limi ts of elec trical
characteristics may differ.
When manufacturing an application system, please perform
sufficient evaluations in each product. Especially, when
switching a product (example: change from the mask ROM
version to QzROM version), please perform sufficient
evaluations by the switching product in the stage before mass-
producing an application system.
Product Shipped in Blank
As for the product s hipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and
foreign bodies on a socket, etc. because a writing environment
may cause some writing errors.
QzROM Version
Connect the CNVSS/VPP pin the shortest poss ible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series to
the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the VSS pin of the
microcomputer.
•Reason
The CNVSS/VPP pin is the power source input pin for the built-in
QzROM. When programming in the QzROM, the impedance of
the VPP pin is low to al low th e electr ic curre nt for writing to flow
into the built-in QzROM. Because of this, noise can enter easily.
If noise enters the VPP pin, abnormal instruction codes or data
are read from th e QzROM, wh ich may cause a pr ogram run away.
Fig 55. Wiring for the CNVSS/VPP
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask fi le (extension: .mask) which is made by the
mask file converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM
code protect is specified according to the ROM option data* in
the mask file which is submitted at ordering. Note that the
mask file which has nothing at the ROM option data* or has
the data other than “0016” and “FF16” can not be accepted.
•Set “FF16” to the ROM code protect address in ROM data
regardless of the presence or a bsence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be
submitted again.
* ROM option data: mask option noted in MM
DATA REQUIRED FOR QzROM WRITING ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
The shortest
CNVSS/VPP
VSS
Approx. 5kΩ
The shortest
(Note)
(Note)
Note. Shows the microcomputer’s pin.
(1/2)
REVISION HISTORY 3850 Group (Spec.A QzROM version) Data Sheet
Rev. Date Description
Page Summary
1.00 Dec. 10, 2004 −First edition issued
<Updating from Shortsheet (REJ03B0123-0100Z; Rev.1.00>
1• Power source voltage is revised.
• Power dissipation is partly revised.
APPLICATION is partly deleted.
5Table 2 is partly added. Note of Table 2 is added.
2.00 Sep. 09, 2005 −Delete the following: “PRELIMINARY”
1, 4-6 Package name of 42P4B is revised. 42P4B → PRDP0042BA-A
3Table 1 is partly revised.
4Fig.3 is partly revised.
6Table 4 is partly revised.
Notes on differences among 3850 group (standard), 3850 group (spec.H), and 3850 group
11 • ROM Code Protect Address (address FFDB16) is added.
Fig.8 is partly revised.
12 Fig.9 is partly revised.
13 Table 7 is partly revised.
16 Fig.12 is partly revised.
35 WATCHDOG TIMER is revised.
Fig.38 is partly revised.
38 Oscillation Control (1) Stop mode is partly revised.
41 Reserved Area is revised. Reserved Area → Reserved Area, Reserved bit
42 The followings are added;
Flash Memory Version / QzROM Version is deleted.
43 Table 9 is partly revised.
53 PACKAGE OUTLINE of 42P4B is revised.
2.01 Oct. 13, 2005 5 Note 1 of Table 2 is partly revised.
11 • ROM Code Protect Address (address FFDB16) is partly revised.
42 Notes On QzROM Writing Orders, Notes On ROM Code Protect are partly revised.
2.10 Nov. 14, 2005 35 Fig 37. Block diagram of Watchdog timer;
42 QzROM version; approximately 1 k to 5 kΩ resistor → approximately 5 kΩ resistor
53 Package Outline is revised
54-59 Appendix added
2.11 Dec. 19, 2008 1,4-6,43 Package name of 42P2R-A/E is revised. 42P2R-A/E → PRSP0042GA-A/B
11 Fig.8 is partly revised.
35 Initial value of watchdog timer is partly added.
When bit 7 of the watchd og ti mer control register is
“0”: 65.536ms at XIN = 1 6MHz f requen cy.→ 83.886ms at XIN = 12.5 MHz frequency.
“1”: 256µs at XIN = 16MHz frequ ency.→ 327.68µs at XIN = 12.5 MHz frequency.
REVISION HISTORY
(2/2)
REVISION HISTORY 3850 Group (Spec.A QzROM version) Data Sheet
2.11 Dec. 19, 2008 38 (2) Wait mode is partly revised.
41-42 Deleted
55 the STP instruction disable bit → the STP instruction f unction selection bit
56 Notes On QzROM Writing Orders is revised.
2.13 Apr. 17, 2009 −“MAEC TECHNICAL NEWS” reflected: M740-33-0211
35 Note 2 added
38 • Frequency Control <Note> added
56 Notes on W a tchdog Timer revised
Rev. Date Description
Page Summary
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2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
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4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
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result of errors or omissions in the information included in this document.
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(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
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Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
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9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
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