Gnd (Pin 1) (ground): All vo ltages are measured with re-
spect to Gnd. VCC and REF sh ould be bypassed di rectly
t o Gnd wi th an 0.1µF or larger ceramic capacitor. The tim-
in g capacitor di scharge curr ent als o retur ns to this pi n, so
the lead from the oscillator timing capacitor to Gnd should
also be as short and as direct as possibl e.
PKLMT (Pin 2) (peak limit): The threshold for PKLMT is
0.0V. Connect this input to the negative voltage on the
cur r ent sense r es i s t or as shown i n Figure 1. Use a resis-
tor to REF to offset the negative current sense sig nal up
to Gnd.
CA Out (Pin 3) (current amplifier output): This is the out-
put of a wide-band width op a mp that senses line current
and com m ands the pul se w idt h mo dulator (P WM) t o force
the co rrect curren t. T his output can swing close to Gnd,
allowing the PWM to force zero duty cycle when neces-
sary . The current amplif ier will remain active even if the IC
is dis able d. The curre nt amplifier output stage is an NPN
emitter follower pull-up and an 8k resistor to ground.
ISENSE (Pi n 4) (curr ent sense m inu s ): Thi s is the inv erting
input to the current amplifier. This input and the non-in-
ver t ing input M ul t Out r emain f unct ional down to and be-
low Gnd. Care should be taken to avoid taking these
inputs below –0.5V, because they are protected with di-
odes to Gnd.
Mult Out (Pin 5) (multiplier output and current sense
plus): The output of the analog multiplier and the non-in-
verting input of the current amplifier are connected to-
gether at Mult Out. The cautions about taking ISENSE
bel ow –0.5V als o apply to Mult Out. As t he m ul ti plier out -
put is a cu rrent , this is a high imp edance input similar to
ISENSE, so the current amplifier can be configured as a
differential amplifier to reject Gnd noise. Figure 1 shows
an exam ple of using the current amplifier dif fer entially .
IAC (Pin 6) (input AC current): This input to the analog
multiplier is a current. The multiplier is tailored for very
low distortion from this current input (IAC) to Mult Out, so
this is the only multiplier input that should be used for
sensing instantaneous line voltage. The nominal voltage
on IAC is 6V, so in addition to a resistor from IAC to recti -
f ied 60Hz , connect a resist or fr om I AC to REF. If the resis-
tor to REF is one fourth o f th e val ue of the resistor to the
rectifier, then the 6V offset will be cancel led, and the line
curr ent will have minimal cross-over distortion.
VA Ou t ( Pi n 7) ( voltage am pli fi er out put): This i s the out -
put of the op amp t hat regulates outpu t voltage. Like the
current amplifier, the voltage amplifier will stay active
even if the IC is disabled with either ENA or VCC. This
means that large feedback capacitor s across the amplifier
will stay ch ar ged thro ugh moment ary disable cycles. Volt -
age a mplifier output levels bel ow 1V will inhibit multiplier
out put . The volt age am plif ier output is i nternall y limi ted to
approximately 5.8V to prevent overshoot. The voltage
ampl ifier ou tpu t stage is an NPN emitt er follower p ull-up
and an 8k re sistor to ground.
VRMS (Pin 8) (RMS line voltage): The output of a boost
PWM is propor tional to the input voltage, so when the line
voltage into a low-bandwidth boost PWM voltage regula-
tor changes, the output will change immediately and
slowly recove r to the regula ted le vel. Fo r these devices,
t he VRMS input com pensat es for li ne volt age changes if it
is connected to a voltage proportional to the RMS input
line voltage. For best control, the VRMS voltage should
stay between 1.5V and 3.5V.
REF (Pin 9) (vol tag e reference output): R EF is the output
of an accurate 7.5V voltage reference. This output is ca-
pab le of delive ring 10mA to peripheral circuitry a nd is in-
ternally short circuit current limited. REF is disabled and
will remain at 0V when VCC is low or when ENA is low.
Byp ass REF to Gnd with an 0.1µF or l arger ceramic ca-
pacitor f or best st ability.
ENA (Pin 10) (enable): ENA is a logic input that will en-
able the PWM output, voltage reference, and oscillator.
ENA also wi ll r eleas e t he soft star t c lamp, all owin g SS to
rise. When unused, connect ENA to a +5V supply or pull
ENA high w it h a 22k r esist or. The ENA pin is not int ended
t o be used as a high speed shu tdow n to t he PWM output.
VSENSE (Pin 11) ( voltage ampl ifier inver ti ng input) : Thi s is
normally connected to a feedback network and to the
boost conver t er output through a divider network .
RSET (Pin 12) (oscillator charging current and multiplier
limit set): A resistor from RSET to gr ound w ill pro gram os-
cillator charging current and maximum multiplier output.
Multiplier output current will not exceed 3.75 V divided by
the resistor from RSET to ground.
SS ( Pi n 13) (soft start ): SS will r emain at Gnd as long as
the IC is disabled or VCC is too low. SS will pull up to over
8V by an internal 14µA current source when both VCC be-
com es vali d and t he I C is enabl ed. SS w il l act as t he r ef-
erence input to the vol tage amplifier if SS is below REF.
With a large capacitor from SS to Gnd, the reference to
the voltage regulating amplifier will rise slowly, and in-
crease the PWM duty cycle slowly. In the event of a dis-
able command or a supply dropout, SS will quickly
discharge to ground and disable the PWM.
CT (Pin 14) (osci llator timing capacitor): A capacitor from
CT to Gnd will set the P WM osci llator frequency accord-
ing to this relatio nship:
F
= 1.25
R
SET
×
C
T
VCC (Pin 15) (positive supply voltage) : Connect VCC to a
st abl e s our ce of at least 20m A above 17V for norm al op-
eration. Also bypass VCC directly to Gnd to absorb supply
cur r ent spikes re quired to charge ex te rnal M OSF ET gate
capacitances. To prevent inadequate GT Drv signals,
these devices will be inhibited unless VCC exceeds the
upper under-voltage lockout threshold and remains
above the low er threshol d.
PIN DESCRIPTIONS (Pin Number s Refer to DI L P ackages)
UC1854
UC2854
UC3854
4