
AX88796ALF
3-in-1 Local Bus Fast Ethernet Controller
Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
Table of Contents
1.0 INTRODUCTION ......................................................................................................................................................6
1.1 GENERAL DESCRIPTION: ............................................................................................................................................6
1.2 AX88796A BLOCK DIAGRAM: ..................................................................................................................................6
1.3 PIN CONNECTION DIAGRAM .....................................................................................................................................7
1.3.1 Pin Connection Diagram ............................................................................................................................7
1.3.2 Pin Connection Diagram with SPP Port Option ........................................................................................8
1.3.3 Pin Connection Diagram for ISA Bus Mode ...............................................................................................9
1.3.4 Pin Connection Diagram for 80x86 Mode ................................................................................................10
1.3.5 Pin Connection Diagram for MC68K Mode .............................................................................................11
1.3.6 Pin Connection Diagram for MCS-51 Mode ............................................................................................12
2.0 SIGNAL DESCRIPTION ........................................................................................................................................13
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ........................................................................................................13
2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP .............................................................................................14
2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..........................................................................................................14
2.4 EEPROM SIGNALS GROUP ......................................................................................................................................15
2.5 MII INTERFACE SIGNALS GROUP (OPTIONAL) .........................................................................................................15
2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL) ..................................................................16
2.7 GENERAL PURPOSE I/O PINS GROUP .......................................................................................................................16
2.8 MISCELLANEOUS PINS GROUP .................................................................................................................................17
2.9 GPIO/MII CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ....................................................................18
3.0 MEMORY AND I/O MAPPING .............................................................................................................................19
3.1 EEPROM MEMORY MAPPING .................................................................................................................................19
3.2 I/O MAPPING ...........................................................................................................................................................20
3.3 SRAM MEMORY MAPPING ......................................................................................................................................20
4.0 BASIC OPERATION ...............................................................................................................................................21
4.1 RECEIVER FILTERING ...............................................................................................................................................21
4.1.1 Unicast Address Match Filter ..........................................................................................................................21
4.1.2 Multicast Address Match Filter .......................................................................................................................22
4.1.3 Broadcast Address Match Filter ......................................................................................................................23
4.1.4 Aggregate Address Filter with Receive Configuration Setup ..........................................................................23
4.2 BUFFER MANAGEMENT OPERATION ........................................................................................................................24
4.2.1 Packet Reception ......................................................................................................................................24
4.2.2 Packet Transmission .................................................................................................................................28
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) ...................................................................30
4.2.4 Removing Packets from the Ring (Host read data from memory) ............................................................31
4.2.5 Other Useful Operations ...........................................................................................................................34
5.0 REGISTERS OPERATION ....................................................................................................................................35
5.1 MAC CORE REGISTERS ...........................................................................................................................................35
5.1.1 Command Register (CR) Offset 00H (Read/Write) .........................................................................................37
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write) .................................................................................37
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write) ...........................................................................................38
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .................................................................................38
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) ...........................................................................38
5.1.6 Transmit Status Register (TSR) Offset 04H (Read) ..........................................................................................39
5.1.7 Receive Configuration (RCR) Offset 0CH (Write) ...........................................................................................39
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ...........................................................................................39
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write) ..............................................................................................40
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) .......................................................................40
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) .......................................................................40
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) .....................................................40
5.1.13 Test Register (TR) Offset 15H (Write)...........................................................................................................40
5.1.14 Test Register (TR) Offset 15H (Read) ............................................................................................................41