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Characteristics subject to change without notice.
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Low Noise/Low Power/SPI Bus
X9410
Dual Digitally Controlled Potentiometer (XDCP
™
)
FEATURES
• Two potentiometers in one package
• SPI serial interface
• Register oriented format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
• High reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of nonvolatile EEPROM memory
• 10K
Ω
resistor arrays
• Resolution: 64 taps each pot
• 24-lead TSSOP, 24-lead SOIC and 24-pin plastic
DIP packages
DESCRIPTION
The X9410 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a ser ies array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments , and signal processing.
BLOCK DIAGRAM
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
CS
SCK
A0
A1
VH0/RH0
VL0/RL0
Data
8
VW0/RW0
VW1/RW1
SO
SI
HOLD
WP
Pot 0
VCC
VSS
V+
V-
Pot 1
A
PPLICATION
N
OTES
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
X9410
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PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the f alling edge of the serial cloc k.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9410.
Chip Select (CS)
When CS is HIGH, the X9410 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state . CS LOW enab les the X9410, placing it in
the active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any oper ation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD m ust be
brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
–
A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
—V
H1
/R
H1
), V
L
/R
L
(V
L0
/R
L0
—V
L1
/R
L1
)
The V
H
/R
H
and V
L
/R
L
inputs are equiv alent to the terminal
connections on either end of a mechanical potentiometer .
V
W
/R
W
(V
W0
/R
W0
—V
W1
/R
W1
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer .
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
VCC
VL0/RL0
VH0/RH0
WP
SI
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
V+
A0
SO
HOLD
SCK
DIP/SOIC
X9410
VSS
VW0/RW0
14
13
11
12
CS
VL1/RL1
VH1/RH1
VW1/RW1
V-
SI
A1
VL1/RL1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
CS
VW0/RW0
VH0/RH0
VL0/RL0
VCC
TSSOP
X9410
HOLD
VH1/RH1
14
13
11
12
VW1/RW1
SCK A0
SO
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
V+
V-
NC
NC
NC
X9410
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PIN NAMES
DEVICE DESCRIPTION
The X9410 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LO W and the HOLD and WP pins must be HIGH during
the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
s witch ma y be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable , one of sixty-f our s witches .
Wiper Counter Register (WCR)
The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon po wer-up .
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
diff erent from the v alue present at power-do wn.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or wr itten directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonv olatile oper ation and will tak e a
maximum of 10ms .
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user pref erence data.
Data Register Detail
Symbol Description
SCK Serial Clock
S
I
, S
O
Serial Data
A
0
-A
1
Device Address
V
H0
/R
H0
–V
H1
/R
H1
,
V
L0/RL0–VL1/RL1 Potentiometer Pins
(terminal equivalent)
VW0/RW0–VW1/RW1 Potentiometer Pin
(wiper equivalent)
WP Hardware Write Protection
V+,V- Analog Supplies
VCC System Supply Voltage
VSS System Ground
NC No Connection
(MSB) (LSB)
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
X9410
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Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received b y
the device. The progress of this inter nal wr ite operation
can be monitored by a Wr ite In Process bit (WIP). The
WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9410 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9410 this is fixed
as 0101[B] (ref er to Figure 2).
The two least significant bits in the ID b yte select one of
four devices on the bus. The physical device address is
defined by the state of the A0-A1 input pins. The X9410
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9410 to successfully continue the
command sequence. The A0–A1 inputs can be actively
driven b y CMOS input signals or tied to V CC or VSS.
The remaining two bits in the ID b yte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
f ormat is shown below in Figure 3.
100
0 0 A1 A0
Device Type
Identifier
Device Address
1
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
VH/RH
VL/RL
VW/RW
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
(One of Two Arrays)
X9410
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Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
aff ected by the instruction.
Four of the ten instr uctions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transf ers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transf ers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Counter Register—This
transf ers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register —
This transfers the contents of both Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data register
is a write to nonvolatile memor y and takes a minimum
of tWR to complete. The transfer can occur between
one of the two potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between both potentiometers and one
associated register .
Five instructions require a three-byte sequence to
complete. These instr uctions transfer data between the
host and the X9410; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
–Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
–Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK cloc k pulse while SI is LO W, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 7-8.
I1I2I3 I0 R1 R0 0 P0
Pot Select
Register
Select
Instructions
X9410
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Figure 4. Two-Byte Instruction Sequence
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
Figure 7. Increment/Decrement Instruction Sequence
010100A1A0I3 I2 I1 I0 R1 R0 0 P0
SCK
SI
CS
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0
SCL
SI
0 0 D5 D4 D3 D2 D1 D0
CS
00
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0
SCL
SI
CS
00
S0
0 0 D5 D4 D3 D2 D1 D0
Don’t Care
010100A1A0 I3 I2 I1 I0 0 0 P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
X9410
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Figure 8. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction Instruction Set OperationI3I2I1I0R1R0P1P0
Read Wiper Counter
Register 1001000P
0Read the contents of the Wiper Counter Register
pointed to by P0
Write Wiper Counter
Register 1010000P
0Write new value to the Wiper Counter Register
pointed to by P0
Read Data Register 1 0 1 1 R1R00P
0Read the contents of the Data Register pointed to
by P0 and R1–R0
Write Data Register 1 1 0 0 R1R00P
0Write new value to the Data Register pointed to
by P0 and R1–R0
XFR Data Register to
Wiper Counter Register 1101R
1R00P
0Transfer the contents of the Data Register pointed
to by R1–R0 to the Wiper Counter Register pointed
to by P0
XFR Wiper Counter
Register to Data Register 1110R
1R00P
0Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Register pointed
to by R1–R0
Global XFR Data Register
to Wiper Counter Register 0001R
1R00 0 Transfer the contents of the Data Registers
pointed to by R1–R0 of both pots to their
respective Wiper Counter Register
Global XFR Wiper
Counter Register to Data
Register
1000R
1R00 0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1–R0 of both pots
Increment/Decrement
Wiper Counter Register 0010000P
0Enable Increment/decrement of the Wiper
Counter Register pointed to by P0
Read Status (WIP bit) 0 1 0 10001Read the status of the internal write cycle, by
checking the WIP bit.
SCK
SI
VW/RW
INC/DEC CMD Issued
tWRID
Voltage Out
X9410
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Instruction Format
Notes: (1) “A1 ~ A0”: stands f or the de vice addresses sent b y the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands f or the increment oper ation, SI held HIGH during active SCK phase (high).
(3) “D”: stands f or the decrement oper ation, SI held LO W during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register(DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses wiper position
(sent by X9410 on SO) CS
Rising
Edge
010100A
1A
01001000P
000W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses Data Byte
(sent by Host on SI) CS
Rising
Edge
010100A
1A
01010000P
000W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses Data Byte
(sent by X9410 on SO) CS
Rising
Edge
010100A
1A
01011R
1R
00P
000W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses Data Byte
(sent by host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1A
01100R
1R
00P
000W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses CS
Rising
Edge
010100A
1A
01101R
1R
00P
0
X9410
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Read Status
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR and WCR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100D
A
1
D
A
01110R
1R
00P
0
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode WCR
addresses increment/decrement
(sent by master on SDA) CS
Rising
Edge
010100A
1A
00010XX0P
0I/
DI/
D....I/
DI/
D
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR
addresses CS
Rising
Edge
010100A
1A
00001R
1R
000
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode DR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1A
01000R
1R
000
CS
Falling
Edge
device type
identifier device
addresses instruction
opcode wiper
addresses Data Byte
(sent by X9410 on SO) CS
Rising
Edge
010100A
1A
0010100010000000W
I
P
X9410
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias....................–65°C to +135°C
Storage temperature.........................–65°C to +150°C
Voltage on SCK, SCL or any address
input with respect to VSS.........................–1V to +7V
Voltage on V+ (ref erenced to VSS) ........................10V
Voltage on V- (referenced to VSS).........................-10V
(V+) – (V-)..............................................................10V
Any VH/RH...............................................................V+
Any VL/RL................................................................. V-
Lead temperature (soldering, 10 seconds).........300°C
IW (10 seconds) ...............................................±12mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
aff ect de vice reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC) Limits
X9410 5V ±10%
X9410-2.7 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer .
(2) Relative Linearity is utilized to determine the actual change in voltage betw een tw o successive tap positions when used as a poten-
tiometer . It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH–VL)/63, single pot
(4) Individual arra y resolution.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
RTOTAL End to end resistance ±20 %
Power rating 50 mW 25°C, each pot
IW Wiper current ±6 mA
RWWiper resistance 150 250 ΩWiper Current = ± 1mA, VCC = 3V
40 100 ΩWiper Current = ± 1mA, VCC = 5V
Vv+ Voltage on V+ pin X9410 +4.5 +5.5 V
X9410-2.7 +2.7 +5.5
Vv- Voltage on V- pin X9410 -5.5 -4.5 V
X9410-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL pin V- V+ V
Noise -140 dBV Ref: 1kHz
Resolution (4) 1.6 %
Absolute linearity (1) ±1 MI(3) Vw(n)(actual)—Vw(n)(expected)
Relative linearity (2) ±0.2 MI(3) Vw(n + 1)—[Vw(n) + MI]
Temperature coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temperature Coefficient ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3
X9410
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
ICC1 VCC supply current (active) 400 µA fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2 VCC supply current (nonvolatile
write) 1mAf
SCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB VCC current (standby) 1 µA SCK = SI = VSS, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V
VIL Input LOW voltage –0.5 VCC x 0.1 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
Symbol Test Max. Unit Test Conditions
COUT(5) Output capacitance (SO) 8 pF VOUT = 0V
CIN(5) Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V
Symbol Parameter Min. Max. Unit
tPUR(6) Power-up to initiation of read operation 1 1 ms
tPUW(6) Power-up to initiation of write operation 5 5 ms
tRVCC VCC Power up ramp 0.2 50 V/msec
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-
down sequencing of the bias supplies VCC, V+, and V–
provided that all three supplies reach their final values
within 1msec of each other. However, at all times, the
voltages on the potentiometer pins must be less than
V+ and more than V–. The recall of the wiper position
from nonvolatile memory is not in effect until all
supplies reach their final v alue.
EQUIVALENT A.C. LOAD CIRCUIT
5V
1533Ω
100pF
SDA Output
2.7V
100pF
X9410
Characteristics subject to change without notice. 12 of 21
REV 1.1 10/6/00 www.xicor.com
A.C. TEST CONDITIONS
Notes: (5) This parameter is periodically sampled and not 100%
tested
(6) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
Test Circuit #3 SPICE Macro Model
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
AC TIMING
Symbol Parameter Min. Max. Unit
fSCK SSI/SPI clock frequency 2.0 MHz
tCYC SSI/SPI clock cycle time 500 ns
tWH SSI/SPI clock high time 200 ns
tWL SSI/SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable time 0 500 ns
tVSO output valid time 100 ns
tHO SO output hold time 0 ns
tRO SO output rise time 50 ns
tFO SO output fall time 50 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns
tCS CS deselect time 2 µs
tWPASU WP, A0 and A1 setup time 0 ns
tWPAH WP, A0 and A1 hold time 0 ns
X9410
Characteristics subject to change without notice. 13 of 21
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HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
TIMING DIAGRAMS
Input Timing
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
X9410
Characteristics subject to change without notice. 14 of 21
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Output Timing
Hold Timing
XDCP Timing (for All Load Instructions)
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
...
CS
SCK
SI MSB LSB
VW/RW
tWRL
...
SO High Impedance
X9410
Characteristics subject to change without notice. 15 of 21
REV 1.1 10/6/00 www.xicor.com
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
CS
SCK
SO
SI ADDR
tWRID
High Impedance
VW/RW
...
Inc/Dec Inc/Dec
...
...
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9410
Characteristics subject to change without notice. 16 of 21
REV 1.1 10/6/00 www.xicor.com
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
VW/RW
VR
I
Three terminal Potentiometer;
Variable v oltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
–
VSVO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9410
Characteristics subject to change without notice. 17 of 21
REV 1.1 10/6/00 www.xicor.com
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VSVO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = -R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
X9410
Characteristics subject to change without notice. 18 of 21
REV 1.1 10/6/00 www.xicor.com
PACKAGING INFORMATION
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.022 (0.56)
0.014 (0.36)
0.150 (3.81)
0.125 (3.18)
0.625 (15.87)
0.600 (15.24)
0.110 (2.79)
0.090 (2.29)
1.265 (32.13)
1.230 (31.24)
1.100 (27.94)
Ref.
Pin 1 Index
0.162 (4.11)
0.140 (3.56)
0.030 (0.76)
0.015 (0.38)
Pin 1
Seating
Plane
0.065 (1.65)
0.040 (1.02)
0.557 (14.15)
0.530 (13.46)
0.080 (2.03)
0.065 (1.65)
0°
15°
24-Lead Plastic Dual In-Line Package Type P
Typ. 0.010 (0.25)
NOTE:
X9410
Characteristics subject to change without notice. 19 of 21
REV 1.1 10/6/00 www.xicor.com
PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60) 0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7°
24-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0° – 8°
X 45°
X9410
Characteristics subject to change without notice. 20 of 21
REV 1.1 10/6/00 www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24-Lead Plastic, TSSOP Package Type V
.169 (4.3)
.177 (4.5).252 (6.4) BSC
.026 (.65) BSC
.303 (7.70)
.311 (7.90)
.002 (.06)
.005 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail “A”
.031 (.80)
.041 (1.05)
.010 (.25)
.020 (.50)
.030 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16)(7.72)
(1.78)
(0.42) (0.65)
ALL MEASUREMENTS ARE TYPICAL
0°–8°
X9410
Characteristics subject to change without notice. 21 of 21
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutor y, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement.
Xicor , Inc. makes no warranty of merchantability or fitness f or any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor , Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor , Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor , Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective o wners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. F oreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life , system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up f eatures to pre v ent such an occurrence .
Xicor’ s products are not authorized f or use in critical components in lif e support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonab ly expected to result in a significant injury to the user .
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to aff ect its safety or effectiv eness .
©Xicor, Inc. 2000 Patents Pending
REV 1.1 10/6/00 www.xicor.com
Ordering Information
Device VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
P otentiometer Or ganization
P ot 0 Pot 1
W = 10KΩ10KΩ
X9410 P T VY
