DS1744WP+120 - Hytronics - Product.Network

1 of 18 REV: 041105

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

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FEATURES

§ Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit, and

Lithium Energy Source

§ Clock Registers are Accessed Identically to

the Static RAM. These Registers are Resident

in the Eight Top RAM Locations.

§ Century Byte Register (i.e., Y2K Compliant)

§ Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

§ BCD-Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with

Automatic Leap-Year Compensation Valid

Up to the Year 2100

§ Battery Voltage-Level Indicator Flag

§ Power-Fail Write Protection Allows for ±10%

VCC Power-Supply Tolerance

§ Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

§ DIP Module Only

Standard JEDEC Byte-Wide 32k x 8 Static

RAM Pinout

§ PowerCapÒ Module Board Only

Surface-Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal

Replaceable Battery (PowerCap)

Power-On Reset Output

Pin-for-Pin Compatible with Other Densities

of DS174xP Timekeeping RAM

§ Also Available in Industrial Temperature

Range: -40°C to +85°C

§ UL recognized

PIN CONFIGURATIONS

PowerCap is a registered trademark of Dallas Semiconductor.

DS1744/DS1744P

Y2K-Compliant, Nonvolatile Timekeeping RAMs

www.maxim-ic.com

PDIP Module

(700-mil Extended)

VCC

DQ7

DQ6

DQ5

DQ4

DQ3

A14

A12

DQ0

DQ1

DQ2

GND

Dallas

Semiconductor

DS1744

N.C.

VCC

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

N.C.

34 N.C.

X1 GND VBAT X2

PowerCap Module Board

(Uses DS9034PCX PowerCap)

Dallas

Semiconductor

DS1744P

TOP VIEW

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PIN DESCRIPTION

PDIP PowerCap NAME FUNCTION

1 32 A14

2 30 A12

3 25 A7

4 24 A6

5 23 A5

6 22 A4

7 21 A3

8 20 A2

9 19 A1

10 18 A0

21 28 A10

23 29 A11

24 27 A9

25 26 A8

26 31 A13

Address Input

11 16 DQ0

12 15 DQ1

13 14 DQ2

15 13 DQ3

16 12 DQ4

17 11 DQ5

18 10 DQ6

19 9 DQ7

Data Input/Output

14 17 GND Ground

20 8 CE Active-Low Chip-Enable Input

22 7 OE Active-Low Output-Enable Input

27 6 WE Active-Low Write-Enable Input

28 5 VCC Power-Supply Input

— 4 RST Active-Low Reset Output, Open Drain. Requires a pullup resistor for

proper operation.

— 1, 2, 3, 33,

34 N.C. No Connection

— X1, X2,

VBAT Crystal Connection VBAT Battery Connection

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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ORDERING INFORMATION

PART VOLTAGE

RANGE (V) TEMP RANGE PIN-PACKAGE TOP MARK

DS1744-70+ 5.0 0°C to +70°C 32 EDIP (0.740a) DS1744+70

DS1744+100 5.0 0°C to +70°C 32 EDIP (0.740a) DS1744+100

DS1744-70 5.0 0°C to +70°C 32 EDIP (0.740a) DS1744-70

DS1744-70 IND 5.0 -40°C to +85°C 32 EDIP (0.740a) DS1744-70 IND

DS1744W-120+ 3.3 0°C to +70°C 32 EDIP (0.740a) DS1744W+120

DS1744W-120 3.3 0°C to +70°C 32 EDIP (0.740a) DS1744W-120

DS1744W-120 IND 3.3 -40°C to +85°C 32 EDIP (0.740a) DS1744W-120 IND

DS1744P-70+ 5.0 0°C to +70°C 34 PowerCap * DS1744P+70

DS1744P+100 5.0 0°C to +70°C 34 PowerCap * DS1744P+100

DS1744P-70 5.0 0°C to +70°C 34 PowerCap * DS1744P-70

DS1744P-70 IND 5.0 -40°C to +85°C 34 PowerCap * DS1744P-70 IND

DS1744WP+120 3.3 0°C to +70°C 34 PowerCap * DS1744WP+120

DS1744WP-120 3.3 0°C to +70°C 34 PowerCap * DS1744WP-120

DS1744WP-120 IND 3.3 -40°C to +85°C 34 PowerCap * DS1744WP-120 IND

*DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately).

A “+" indicates lead-free product. The top mark will include a “+" symbol on lead-free devices.

DESCRIPTION

The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8

NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as

shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations.

The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour

BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock

registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles.

The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by

access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the

device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from

unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Figure 1. Block Diagram

PACKAGES

The DS1744 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP

style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin

PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)

that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the

DS1744P after the completion of the surface-mount process. Mounting the PowerCap after the surface-

mount process prevents damage to the crystal and battery due to the high temperatures required for solder

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

CLOCK OPERATIONS—READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates

to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a 1 is written into the read bit, bit 6 of the century register (Table 2). As long as a

1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is,

day, date, and time that was current at the moment the halt command was issued. However, the internal

clock registers of the double-buffered system continue to update so that the clock accuracy is not affected

by the access of data. All the DS1744 registers are updated simultaneously after the internal clock-register

updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The

READ bit must be a 0 for a minimal of 500ms to ensure the external registers are updated.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 1. Truth Table

VCC CE OE WE MODE DQ POWER

VIH X X Deselect High-Z Standby

VIL X VIL Write Data In Active

VIL V

IL V

IH Read Data Out Active

VCC > VPF

VIL V

IH V

IH Read High-Z Active

VSO < VCC < VPF X X X Deselect High-Z CMOS Standby

VCC < VSO < VPF X X X Deselect High-Z Data-Retention Mode

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read

bit, halts updates to the DS1744 registers. The user can then load them with the correct day, date, and time

data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock

counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator can be stopped at any time. To increase the shelf life, the oscillator can be turned off

to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (Table

2). Setting it to a 1 stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to

logic 1 and the oscillator is running, the LSB of the seconds register toggles at 512Hz. When the seconds

valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable).

CLOCK ACCURACY (DIP MODULE)

The DS1744 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is

calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require

additional calibration. For this reason, methods of field clock calibration are not available and not

necessary. Clock accuracy is also affected by the electrical environment; caution should be taken to place

the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer to

Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

CLOCK ACCURACY (PowerCap MODULE)

The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module

typically keeps time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. Clock accuracy is

also affected by the electrical environment and caution should be taken to place the RTC in the lowest-

level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal

Considerations with Dallas Real-Time Clocks.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 2. Register Map

DATA

ADDRESS B7 B6 B5 B4 B3 B2 B1 B0

FUNCTION RANGE

7FFF 10 Year Year Year 00-99

7FFE X X X 10

Month Month Month 01-12

7FFD X X 10 Date Date Date 01-31

7FFC BF FT X X X Day Day 01-07

7FFB X X 10 Hour Hour Hour 00-23

7FFA X 10 Minutes Minutes Minutes 00-59

7FF9 OSC 10 Seconds Seconds Seconds 00-59

7FF8 W R 10 Century Century Century 00-39

OSC = Stop Bit R = Read Bit FT = Frequency Test

W = Write Bit X = See Note BF = Battery Flag

Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper

clock operation.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and

CE (chip enable) is low. The device architecture allows ripple-through access to any of the address

locations in the NV SRAM. Valid data is available at the DQ pins within tAA after the last address input is

stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and

states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access

time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA,

the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and

OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a

typical application, the OE signal is high during a write cycle. However, OE can be active provided that

care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the

data bus can become active with read data defined by the address inputs. A low transition on WE then

disables the output tWEZ after WE goes active.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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DATA-RETENTION MODE

The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.

However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. At this time the power-fail reset-output

signal ( RST ) is driven active and remains active until VCC returns to nominal levels. When VCC falls

below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the

backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to

nominal levels. The 3.3V device is fully accessible, and data can be written or read only when VCC is

greater than VPF. When VCC falls below VPF access to the device is inhibited. At this time the power-fail

reset-output signal ( RST ) is driven active and remains active until VCC returns to nominal levels. If VPF is

less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below

VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when

VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is

returned to nominal levels. The RST signal is an open-drain output and requires a pullup. Except for the

RST , all control, data, and address signals must be powered down when VCC is powered down.

BATTERY LONGEVITY

The DS1744 has a lithium power source that is designed to provide energy for clock activity and clock and

RAM data retention when the VCC supply is not present. The capability of this internal power supply is

sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For

specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running

in the absence of VCC power. Each DS1744 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than

VPF, the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the

DS1744 is much longer than 10 years since no lithium battery energy is consumed when VCC is present.

BATTERY MONITOR

The DS1744 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of

the day register is used to indicate the voltage-level range of the battery. This bit is not writable and should

always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated, and both

the contents of the RTC and RAM are questionable.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………..…….…..……………..-0.3V to +6.0V

Operating Temperature Range………………...…………………………..-40°C to +85°C (noncondensing)

Storage Temperature Range……………………………………………….-40°C to +85°C (noncondensing)

Soldering Temperature………………………………..See IPC/JEDEC J-STD-020 (DIP Package) (Note 7)

This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect

reliability.

OPERATING RANGE

RANGE TEMP RANGE VCC

Commercial 0°C to +70°C, Noncondensing 3.3V ±10% or 5V±10%

Industrial -40°C to +85°C, Noncondesnsing 3.3V ±10% or 5V±10%

RECOMMENDED DC OPERATING CONDITIONS

(TA = Over the operating range)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VIH 2.2 VCC + 0.3V V 1

Logic 1 Voltage (All Inputs)

VCC = 5V ±10%

VCC = 3.3V ±10% VIH 2.0 VCC + 0.3V V

VIL -0.3 0.8 V

Logic 0 Voltage (All Inputs)

VCC = 5V ±10%

VCC = 3.3V ±10% VIL 0.3 0.6 V 1

DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current ICC 75 mA 2, 3

TTL Standby Current

(CE = VIH) ICC1 6 mA 2, 3

CMOS Standby Current

(CE ³ VCC - 0.2V) Icc2 4 mA 2, 3

Input Leakage Current (Any

Input) IIL -1 +1

Output Leakage Current

(Any Output) IOL -1 +1

Output Logic 1 Voltage

(IOUT = -1.0mA) VOH 2.4 1

Output Logic 0 Voltage

(IOUT = +2.1mA) VOL 0.4 1

Write Protection Voltage VPF 4.25 4.50 V 1

Battery Switchover Voltage VSO V

BAT 1, 4

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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DC ELECTRICAL CHARACTERISTICS

(VCC = 3.3V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current ICC 30 mA 2, 3

TTL Standby Current

(CE = VIH) ICC1 2 mA 2, 3

CMOS Standby Current

(CE ³ VCC - 0.2V) ICC2 2 mA 2, 3

Input Leakage Current (Any

Input) IIL -1 +1

Output Leakage Current

(Any Output) IOL -1 +1

Output Logic 1 Voltage

(IOUT = -1.0mA) VOH 2.4 1

Output Logic 0 Voltage

(IOUT = +2.1mA) VOL 0.4 1

Write Protection Voltage VPF 2.80 2.97 V 1

Battery Switchover Voltage VSO

VBAT

VPF

V 1, 4

AC CHARACTERISTICS—READ CYCLE (5V)

(VCC = 5.0V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Read Cycle Time tRC 70 ns

Address Access Time tAA 70 ns

CE to DQ Low-Z tCEL 5 ns

CE Access Time tCEA 70 ns

CE Data Off Time tCEZ 25 ns

OE to DQ Low-Z tOEL 5 ns

OE Access Time tOEA 35 ns

OE Data Off Time tOEZ 25 ns

Output Hold from Address tOH 5 ns

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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AC CHARACTERISTICS—READ CYCLE (3.3V)

(VCC = 3.3V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Read Cycle Time tRC 120 ns

Address Access Time tAA 120 ns

CE to DQ Low-Z tCEL 5 ns

CE Access Time tCEA 120 ns

CE Data Off Time tCEZ 40 ns

OE to DQ Low-Z tOEL 5 ns

OE Access Time tOEA 100 ns

OE Data Off Time tOEZ 35 ns

Output Hold from Address tOH 5 ns

READ CYCLE TIMING DIAGRAM

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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AC CHARACTERISTICS—WRITE CYCLE (5V)

(VCC = 5.0V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Write Cycle Time tWC 70 ns

Address Setup Time tAS 0 ns

WE Pulse Width tWEW 50 ns

CE Pulse Width tCEW 60 ns

Data Setup Time tDS 30 ns

Data Hold Time tDH1 0 ns 8

Data Hold Time tDH2 0 ns 9

Address Hold Time tAH1 5 ns 8

Address Hold Time tAH2 5 ns 9

WE Data Off Time tWEZ 25 ns

Write Recovery Time tWR 5 ns

AC CHARACTERISTICS—WRITE CYCLE (3.3V)

(VCC = 3.3V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Write Cycle Time tWC 120

Address Setup Time tAS 0

120 ns

WE Pulse Width tWEW 100 ns

CE Pulse Width tCEW 110 ns

CE and CE2 Pulse Width tCEW 110 ns

Data Setup Time tDS 80

Data Hold Time tDH1 0

ns 8

Data Hold Time tDH2 0

ns 9

Address Hold Time tAH1 0

ns 8

Address Hold Time tAH2 10

ns 9

WE Data Off Time tWEZ 40 ns

Write Recovery Time tWR 10

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED

WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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POWER-UP/DOWN AC CHARACTERISTICS (5V)

(VCC = 5.0V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VIH Before Power-Down tPD 0

VCC Fall Time: VPF(MAX) to VPF(MIN) t

F 300

VCC Fall Time: VPF(MIN) to VSO t

FB 10

VCC Rise Time: VPF(MIN) to VPF(MAX) t

R 0

Power-Up Recover Time tREC 35 ms

Expected Data-Retention Time

(Oscillator ON) tDR 10 years 5, 6

POWER-UP/DOWN TIMING (5V DEVICE)

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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POWER-UP/DOWN CHARACTERISTICS (3.3V)

(VCC = 3.3V ±10%, TA = Over the operating range.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VIH, Before Power-

Down tPD 0

VCC Fall Time: VPF(MAX) to VPF(MIN) t

F 300

VCC Rise Time: VPF(MIN) to VPF(MAX) t

R 0

VPF to RST High tREC 35 ms

Expected Data-Retention Time

(Oscillator ON) tDR 10 years 5, 6

POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)

CAPACITANCE

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance On All Input Pins CIN 14 pF

Capacitance On All Output Pins CO 10 pF

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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AC TEST CONDITIONS

Output Load: 50pF + 1TTL Gate

Input Pulse Levels: 0 to 3.0V

Timing Measurement Reference Levels:

Input: 1.5V

Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

NOTES:

1) Voltages are referenced to ground.

2) Typical values are at +25°C and nominal supplies.

3) Outputs are open.

4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.

5) Data-retention time is at +25°C.

6) Each DS1744 has a built-in switch that disconnects the lithium source until the user first applies VCC.

The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative time

in the absence of VCC starting from the time power is first applied by the user.

7) RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques as

long as temperature exposure to the lithium energy source contained within does not exceed +85°C.

Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is

not used.

In addition, for the PowerCap:

a. ) Dallas Semiconductor recommends that PowerCap module bases experience one pass through

solder reflow oriented with the label side up (“live-bug”).

b.) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than

3 seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To

remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder

wick to remove solder.

8) tAH1, tDH1 are measured from WE going high.

9) tAH2, tDH2 are measured from CE going high.

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package

outline information, go to www.maxim-ic.com/DallasPackInfo.)

28-PIN

PKG DIM

MIN MAX

IN 1.470 1.490

A MM 37.34 37.85

IN 0.675 0.740

B MM 17.75 18.80

IN 0.335 0.355

C MM 8.51 9.02

IN 0.075 0.105

D MM 1.91 2.67

IN 0.015 0.030

E MM 0.38 0.76

IN 0.140 0.180

F MM 3.56 4.57

IN 0.090 0.110

G MM 2.29 2.79

IN 0.590 0.630

H MM 14.99 16.00

IN 0.010 0.018

J MM 0.25 0.45

IN 0.015 0.025

K MM 0.43 0.58

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PACKAGE INFORMATION (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package

outline information, go to www.maxim-ic.com/DallasPackInfo.)

NOTE: DALLAS SEMICONDUCTOR RECOMMENDS THAT POWERCAP MODULE BASE

EXPERIENCE ONE PASS THROUGH SOLDER REFLOW ORIENTED WITH THE LABE

SIDE UP (“LIVE-BUG”).

NOTE: HAND SOLDERING AND TOUCH-UP: DO NOT TOUCH OR APPLY THE

SOLDERING IRON TO LEADS FOR MORE THAN 3 SECONDS. TO SOLDER, APPLY FLUX

TO THE PAD, HE

T THE LEAD FRAME PAD, AND APPLY SOLDER. TO REMOVE THE

PART, APPLY FLUX, HEAT THE LEAD FRAME PAD UNTIL THE SOLDER REFLOWS, AND

USE A SOLDER WICK TO REMOVE SOLDER.

COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE TYPE.

34-PIN PowerCap

MODULE

PKG DIM

MIN NOM MAX

A IN 0.920 0.925 0.930

B IN 0.980 0.985 0.990

C IN — — 0.080

D IN 0.052 0.055 0.058

E IN 0.048 0.050 0.052

F IN 0.015 0.020 0.025

G IN 0.025 0.027 0.030

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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PACKAGE INFORMATION (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package

outline information, go to www.maxim-ic.com/DallasPackInfo.)

34-PIN

PKG DIM MIN NOM MAX

A IN 0.920 0.925 0.930

B IN 0.955 0.960 0.965

C IN 0.240 0.245 0.250

D IN 0.052 0.055 0.058

E IN 0.048 0.050 0.052

F IN 0.015 0.020 0.025

G IN 0.020 0.025 0.030

COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE TYPE.

DS1744P WITH DS9034PCX ATTACHED

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

PACKAGE INFORMATION (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For

the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)

PowerCap MODULE

PKG DIM MIN NOM MAX

A IN — 1.050 —

B IN — 0.826 —

C IN — 0.050 —

D IN — 0.030 —

E IN — 0.112 —

RECOMMENDED POWERCAP MODULE LAND PATTERN