TC358749XBG CMOS Digital Integrated Circuit Silicon Monolithic TC358749XBG TC358749XBG Mobile Peripheral Devices Overview The HDMI-RX to MIPI CSI-2-TX is a bridge device that converts HDMI(R) stream to MIPI(R) CSI-2 while providing de-interlacing (for test purpose) and auto-scaling features. TC358749XBG shares the same 80-pin package as that of TC358779XBG. P-VFBGA80-0707-0.65-001 Weight: 77mg (Typ.) Features HDMI-RX Interface HDMI 1.4b - Video Formats Support (Up to 1080p @60fps) RGB, YCbCr444: 24-bpp @60fps YCbCr422 24-bpp @60fps - Audio Supports Internal Audio PLL to track N/CTS value transmitted by the ACR packet. - 3D Support - HDCP1.4a Support (optional) - EDID Support Release A, Revision 1 (Feb 9, 2000) First 128 byte (EDID 1.3 structure) First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D) Embedded 1K-byte SRAM (EDID_SRAM) - Maximum HDMI clock speed: 165 MHz Does not support Audio Return Path and HDMI Ethernet Channels CSI-2 TX Interface MIPI CSI-2 compliant (Version 1.1 22 November 2011) Supports up to 4 data lanes @1Gbps/lane Supports video data formats - RGB888, RGB666, YCbCr422* 16 & 24bit and YCbCr444 I2C Slave Interface Support for normal (100 kHz), fast mode (400 kHz) and ultra-fast mode (2 MHz) Configure all TC358749 XBG internal registers Support 2 I2C Slave Addresses (7'h0F & 7'h1F) selected through boot-strap pin (INT) Audio Output Interface Any of the four audio interfaces are available: I2S, TDM, IEC60958 or SLIMbus (pins are multiplexed) I2S Audio Interface Up to 4 data lanes for 8-channel data Support Master Clock mode only Support 16, 18, 20 or 24-bit data (depend on HDMI input stream) Support Left or Right-justify with MSB first Support 32 bit-wide time-slot only Output Audio Over Sampling clock (256fs) (c) 2014-2017 Toshiba Electronic Devices & Storage Corporation Support IEC 60958 & 61937 formats (depending upon HDMI input stream) over I2S Supports HBR audio stream split across 4 I2S lines if bandwidth higher than 12 MHz TDM (Time Division Multiplexed) Audio Interface Fixed to 8 channels Support Master Clock mode only Support 16, 18, 20 or 24-bit PCM audio data word (depend on HDMI input stream) Support 32 bit-wide time slot only Output Audio OverSampling clock (256fs) Digital Audio Interface Supports 2 channels (any 2 of the total 8) (depend on HDMI input stream) Support IEC 60958 & 61937 formats (depending upon HDMI input stream) SLIMbus Audio Interface Up to 8-channel data (2, 4, 6 or 8) Supports Active Framer (Host) mode as well as active framer outside the chip Active Manager is not supported. Supports Isochronous, Pushed & Pulled protocols - Isochronous protocol supported only in Active manager scenario Supports up to 28.8 MHz Root Clock Frequency (in Active Framer mode) Supports up to 22 MHz clock frequency on Clk lane (in Active Framer mode) Video Processing Input formats accepted: - RGB or YCbCr422 - Interlaced or Progressive - 2D or 3D - Limited to 165 MHz PClk, 640x480, 720x480, 720x576, 1280x720, 1920x1080 or 1920x1200 are expected when scalar is used Output formats supported: - RGB888, RGB666,YCbCr444 or YCbCr422 - Interlaced (in case of no video processing) or Progressive - 2D or 3D - Limited by 4Gbps D-PHY bandwidth, 720x480, 1280x720, 1920x1080 or 1920x1200 note1 are expected when scalar is invoked 1 / 18 2017-11-13 Rev. 1.1 TC358749XBG Scaling: - Hardware performs scaling automatically based on input and output frame size HDMI Rx received input frame size and Panel size programmed in registers Can be overwritten by Software if necessary - Horizontal Scaling factors supported: 3-to-2, 1-to-2, 3-to-4, 3-to-8, 9-to-4 and 9-to16 2-to-3 and 1-to-3 - Vertical Scaling factors supported: 1-to-2, 3-to-2 and 3-to-4 2-to-1 and 3-to-1 2-to-3 and 4-to-9 4-to-5 and 8-to-15 - Special handling of 3D formats FP, SBS & T&B to avoid boundary artifacts. Color Space Conversion - RGB YCbCr - Two sets of coefficients provided - 1 set for each direction - Both color space convertors can be enabled/disabled independent of each other. InfraRed (IR) Support NEC InfraRed protocol. System Internal core has two power domains (VDDC1 and VDDC2) - VDDC1 is "always-on" power domain - VDDC2 can be shut-off during deep sleep mode Power supply inputs Core and MIPI D-PHY: 1.2V I/O: 1.8V - 3.3V HDMI: 3.3V AVDDPLL: 1.2V 2 / 18 2017-11-13 TC358749XBG Table of content REFERENCES ..................................................................................................................................................... 6 Overview .......................................................................................................................................................... 7 Features ........................................................................................................................................................... 8 External Pins .................................................................................................................................................. 11 3.1. TC358749XBG Pin Summary ................................................................................................................. 11 3.2. Pin Summary ........................................................................................................................................... 13 3.3. Pin Layout ................................................................................................................................................ 14 Package ......................................................................................................................................................... 15 4.1. TC358749XBG Package (80-pin, P-VFBGA80-0707-0.65-001) ............................................................ 15 Electrical Characteristics ................................................................................................................................ 16 5.1. Absolute Maximum Ratings..................................................................................................................... 16 5.2. Operating Condition................................................................................................................................. 16 Revision History ............................................................................................................................................. 17 RESTRICTIONS ON PRODUCT USE............................................................................................................... 18 Table of Figures Figure 1.1 TC358749XBG System Overview ............................................................................................ 7 Figure 3.1 TC358749XBG 80-Pin Layout Package (Top View) .............................................................. 14 List of Tables Table 2-1 Table 3-1 Table 3-2 Table 4-1 Table 6-1 Power Consumption................................................................................................................. 10 TC358749XBG Pin Name........................................................................................................ 11 Pin Count Summary - TC358749XBG .................................................................................... 13 Mechanical Dimension for TC358749XBG .............................................................................. 15 Revision History ....................................................................................................................... 17 3 / 18 2017-11-13 TC358749XBG HDMI is a trademark or registered trademark of HDMI Licensing, LLC in the United States and/or other countries. MIPI is registered trademarks of MIPI Alliance, Inc. 4 / 18 2017-11-13 TC358749XBG 1 2 3 4 5 6 7 8 9 NOTICE OF DISCLAIMER The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an "AS IS" basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. 10 11 12 13 14 All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. 15 16 17 18 19 20 21 22 23 24 25 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. 26 27 28 29 30 31 32 33 34 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. 35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 36 37 38 39 40 MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary 5 / 18 2017-11-13 TC358749XBG REFERENCES 1. 2. 3. 4. 5. 6. 7. MIPI D-PHY, "MIPI_D-PHY_specification_v01-00-00, May 14, 2009" MIPI CSI-2, "MIPI Alliance Specification for Display Serial Interface (CSI-2) Version 1.1 Revision 22 Nov 2011" HDMI, "High-Definition Multimedia Interface Specification Version 1.4b March 4, 2010" I2C bus specification, version 2.1, January 2000, Philips Semiconductor IEC 60958, Digital Audio Interface, First Edition, 1999 IEC 61937, Digital audio - Interface for non-linear PCM encoded audio bit streams MIPI SlimBus, "MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus (SLIMbus) Version 1.01.01 - 14 July 2008" 6 / 18 2017-11-13 TC358749XBG Overview The HDMI-RX to MIPI CSI-2-TX (H2C+) is a bridge device that converts HDMI stream to MIPI CSI-2 while providing de-interlacing (for test purpose) and auto-scaling features. System Overview block diagrams are shown below. TC358749XBG share the same 80-pin package as that of TC358779XBG. TC358749XBG INT IR IR REFCLK RESETN STBY DDC_SCL DDC_SDA CEC HPDo SYS DDC Slave CEC HPDi HDCP eFuse Keys Sequencer Authentication Engine IPC HDCP Decryption Engine HDMID0P/N (de-Interlacer) TMDS Rx Video FiFo X Audio De-Packet HDMICP/N Figure 1.1 Scaling YUV -> RGB I2S IEC60958 IEC61937 SLIMbus I2C_SCL I2C_SDA CSID0P/N RegFile & EDID_SRAM CSID1P/N CSI2 Tx RGB > YUV HDMID1P/N HDMID2P/N I2C Slave CSI2 Packetizer BaseBand/ Application Process CSID2P/N CSID3P/N CSICP/N Audio APLL I2S_BCLK / SLMB_CLK I2S_LRCLK I2S_DATA_0 / TDM / SLMB_DATA I2S_DATA_1 I2S_DATA_2 I2S_DATA_3 / SPDIF TC358749XBG System Overview 7 / 18 2017-11-13 TC358749XBG Features Below are the main features supported by TC358749XBG. HDMI-RX Interface HDMI 1.4b Video Formats Support (Up to 1080p @60fps) RGB, YCbCr444: 24-bpp @60fps YCbCr422 24-bpp @60fps Audio Supports Internal Audio PLL to track N/CTS value transmitted by the ACR packet. 3D Support HDCP1.4a Support (optional) EDID Support Release A, Revision 1 (Feb 9, 2000) First 128 byte (EDID 1.3 structure) First E-EDID Extension: 128 bytes of CEA Extension version 3 (specified in CEA-861-D) Embedded 1K-byte SRAM (EDID_SRAM) Maximum HDMI clock speed: 165 MHz Does not support Audio Return Path and HDMI Ethernet Channels CSI-2 TX Interface MIPI CSI-2 compliant (Version 1.1 22 November 2011) Supports up to 4 data lanes @1Gbps/lane Supports video data formats RGB888, RGB666, YCbCr422* 16 & 24bit and YCbCr444 I2C Slave Interface Support for normal (100 kHz), fast mode (400 kHz) and ultra-fast mode (2 MHz) Configure all TC358749XBG internal registers Support 2 I2C Slave Addresses (7'h0F & 7'h1F) selected through boot-strap pin (INT) Audio Output Interface Any of the four audio interfaces are available: I2S, TDM, IEC60958 or SLIMbus (pins are multiplexed) I2S Audio Interface Up to 4 data lanes for 8-channel data Support Master Clock mode only Support 16, 18, 20 or 24-bit data (depend on HDMI input stream) Support Left or Right-justify with MSB first Support 32 bit-wide time-slot only Output Audio Over Sampling clock (256fs) Support IEC 60958 & 61937 formats (depending upon HDMI input stream) over I2S Supports HBR audio stream split across 4 I2S lines if bandwidth higher than 12 MHz TDM (Time Division Multiplexed) Audio Interface Fixed to 8 channels Support Master Clock mode only Support 16, 18, 20 or 24-bit PCM audio data word (depend on HDMI input stream) Support 32 bit-wide time slot only Output Audio OverSampling clock (256fs) Digital Audio Interface Supports 2 channels (any 2 of the total 8) (depend on HDMI input stream) Support IEC 60958 & 61937 formats (depending upon HDMI input stream) 8 / 18 2017-11-13 TC358749XBG SLIMbus Audio Interface Up to 8-channel data (2, 4, 6 or 8) Supports Active Framer (Host) mode as well as active framer outside the chip Active Manager is not supported. Supports Isochronous, Pushed & Pulled protocols Isochronous protocol supported only in Active manager scenario Supports up to 28.8 MHz Root Clock Frequency (in Active Framer mode) Supports up to 22 MHz clock frequency on Clk lane (in Active Framer mode) Video Processing Input formats accepted: RGB or YCbCr422 Interlaced or Progressive 2D or 3D Limited to 165 MHz PClk, 640x480, 720x480, 720x576, 1280x720, 1920x1080 or 1920x1200 are expected when scalar is used Output formats supported: RGB888, RGB666,YCbCr444 or YCbCr422 Interlaced (in case of no video processing) or Progressive 2D or 3D Limited by 4Gbps D-PHY bandwidth, 720x480, 1280x720, 1920x1080 or 1920x1200 note1 are expected when scalar is invoked Scaling: Hardware performs scaling automatically based on input and output frame size HDMI Rx received input frame size and Panel size programmed in registers Can be overwritten by Software if necessary Horizontal Scaling factors supported: 3-to-2, 1-to-2, 3-to-4, 3-to-8, 9-to-4 and 9-to-16 2-to-3 and 1-to-3 Vertical Scaling factors supported: 1-to-2, 3-to-2 and 3-to-4 2-to-1 and 3-to-1 2-to-3 and 4-to-9 4-to-5 and 8-to-15 Special handling of 3D formats FP, SBS & T&B to avoid boundary artifacts. Color Space Conversion RGB YCbCr Two sets of coefficients provided - 1 set for each direction Both color space convertors can be enabled/disabled independent of each other. InfraRed (IR) Support NEC InfraRed protocol. System Internal core has two power domains (VDDC1 and VDDC2) VDDC1 is "always-on" power domain VDDC2 can be shut-off during deep sleep mode Power supply inputs Core and MIPI D-PHY: 1.2V I/O: 1.8V - 3.3V HDMI: 3.3V AVDDPLL: 1.2V Power Consumption during typical operation at room temperature 9 / 18 2017-11-13 TC358749XBG Table 2-1 Power Consumption VDDC1 VDDC2 VDDIO1 VDDIO2 VDDMIPI AVDD33 AVDD12 AVDDPLL 1.2V 1080p @ 60fps 720p 1080p @ 30fps 1.2V 3.3V 1.8V 1.2V 3.3V 1.2V 1.2V 0.80 0.89 20.50 72.80 67.82 0.01 Current (mA) 61.13 Power (mW) 73.36 2.64 1.60 24.60 240.24 81.38 0.01 Current (mA) 170.40 0.80 0.89 20.02 72.66 56.67 1.12 Power (mW) 204.48 Total Power (mW) 423.83 541.87 2.64 1.60 24.02 239.78 68.00 1.34 Note: TC358749XBG can support (includes scaling) most valid video stream resolutions; we only list some popular ones here. 10 / 18 2017-11-13 TC358749XBG External Pins 3.1. TC358749XBG Pin Summary Following table gives the signals of TC358749XBG and their function. Table 3-1 Group Pin Name RESETN REFCLK SYSTEM: RESET & TEST CLOCK (5) STBY I - N O L N H H H H H H H H H H - MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY HDMI-PHY - FS-SOD DDC Slave Clock 3.3V (Note1) - FS-SOD DDC Slave data 3.3V (Note1) - FS-SOD CEC signal L L L L LL L L - N N N N N N N N Sch - BIASDA O O O O O O O O O O I I I I I I I I O D O D O D I O IO O IO O O O I O D O D O DAOUT DDC_SCL DDC_SDA CEC HPD (2) HPDI HPDO A_SCK A_WFS A_SD[0] A_SD[2:1] A_SD[3] A_OSCK IR I2 C (2) APLL (4) POWER (11) Note 1.8V - 3.3V 1.8V - 3.3V N CEC IR Function System reset input, active low Reference clock input (27/26MHz or 42MHz range) TEST mode select 0: Normal mode 1: Test mode Standby pin, active low Interrupt Output signal - active high (Level) I2C Slv_Addr_Sel at boot-strap MIPI-CSI-2 clock positive MIPI-CSI-2 clock negative MIPI-CSI-2 Data 0 positive MIPI-CSI-2 Data 0 negative MIPI-CSI-2 Data 1 positive MIPI-CSI-2 Data 1 negative MIPI-CSI-2 Data 2 positive MIPI-CSI-2 Data 2 negative MIPI-CSI-2 Data 3 positive MIPI-CSI-2 Data 3 negative HDMI Clock channel positive HDMI Clock channel negative HDMI Data 0 channel positive HDMI Data 0 channel negative HDMI Data 1 channel positive HDMI Data 1 channel negative HDMI Data 2 channel positive HDMI Data 2 channel negative - CSICP CSICN CSID0P CSID0N CSI-2 TX CSID1P (10) CSID1N CSID2P CSID2N CSID3P CSID3N HDMICP HDMICN HDMID0P HDMI-RX HDMID0N (8) HDMID1P HDMID1N HDMID2P HDMID2N AUDIO (7) Type Sch N I INT DDC (2) I/O Init (O) I I - TC358749XBG Pin Name 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Hot Plug Detect Input Hot Plug Detect Output I2S/TDM Bit/SLIMbus Clock signal I2S Word Clock or TDM Frame Sync signal I2S (ch. 0,1)/TDM/SLIMbus data signal I2S (ch. 2,3,4,5) data signal I2S (ch. 6,7) data signal Audio Over Sampling Clock InfraRed signal 3.3V (Note1) 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V FS-SOD I2C serial clock 1.8V - 3.3V - FS-SOD I2C serial data 1.8V - 3.3V L - O H - PCKIN I - - PFIL O L - VDDC1 VDDC2 VDDIO1 VDDIO2 VDD_MIPI - - - I2C_SCL I2C_SDA BIAS signal Audio PLL clock Reference Output clock Please leave open when not used Audio PLL Reference Input clock Connect to AVSS through 0.1F when not used Audio PLL Low Pass Filter signal Connect to AVSS through 0.1F when not used VDD for Internal Core (always ON) (1) VDD for Internal Core (can be powered down) (2) VDDIO1 IO power supply (1) VDDIO2 IO power supply (1) VDD for the MIPI CSI-2 (1) 11 / 18 1.2V 1.2V 3.3V 1.8V - 3.3V 1.2V 2017-11-13 TC358749XBG Group Pin Name VDD_PLL11 AVDD12 AVDD33 GROUND VSS (25) REXT (Note2) MISC VPGM (Note3) I/O Init (O) - Type - Function VDD for PLL11 (1) HDMI Phy 1.2V power supply (2) HDMI Phy & APLL 3.3V power supply (2) Note 1.2V 1.2V 3.3V - - - Ground (25) - - - - External Reference Resistor eFuse program power supply - Total 80 pins Note1: These IO are 5V tolerant. Note2: Please connect to AVDD33 with a 2k resistor ( 1%). Note3: Please tie to ground. Buffer Type Abbreviation: N: Normal IO FS-SOD: Failed Safe Pseudo open-drain output, Schmidt input Sch: Schmidt input buffer MIPI-PHY: front-end analog IO for CSI-2 HDMI-PHY: front-end analog IO for HDMI 12 / 18 2017-11-13 TC358749XBG 3.2. Pin Summary Table 3-2 Pin Count Summary - TC358749XBG Group Name Pin Count SYSTEM CSI-2 TX HDMI RX DDC CEC Audio I2 C IR HPD APLL POWER GROUND TOTAL 5 11 13 2 1 7 2 1 2 4 7 25 80 Notes Include Power pins Include Power, External (Misc) Resistor pins. Audio PLL - Include Power pin IO, Core, eFuse IO, Core, Analog - 13 / 18 2017-11-13 TC358749XBG 3.3. Pin Layout Top View (through the die) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AVDD12 REXT VDDC2 BIASDA DAOUT PFIL VSS VDD_PLL11 CSID3N CSID3P B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 AVDD33 VSS VSS VSS VSS VSS PCKIN VSS CSID2N CSID2P C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 HDMICP HDMICN CSICN CSICP D1 D2 D9 D10 HDMID0P HDMID0N VSS VDD_MIPI E1 E2 E9 E10 HDMID1P HDMID1N CSID1N CSID1P F1 F2 F9 F10 HDMID2P HDMID2N CSID0N CSID0P G1 G2 G9 G10 AVDD33 VSS VSS A_OSCK H1 H2 H9 H10 AVDD12 CEC A_SD_0 A_WFS J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 DDC_SCL DDC_SDA HPDO INT I2C_SCL IR REFCLK VSS A_SCK A_SD_1 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 VDDC1 VDDIO1 HPDI STBY I2C_SDA RESETN VDDIO2 A_SD_3 A_SD_2 VDDC2 Figure 3.1 D3 E3 F3 G3 H3 D4 D5 D6 D7 VSS VSS VSS VSS E4 E5 E6 E7 VSS VSS VSS VSS F4 F5 F6 F7 VSS VSS VSS VSS G4 G5 G6 G7 VPGM TEST VSS VSS H4 H5 H6 H7 D8 E8 F8 G8 H8 TC358749XBG 80-Pin Layout Package (Top View) 14 / 18 2017-11-13 TC358749XBG Package 4.1. TC358749XBG Package (80-pin, P-VFBGA80-0707-0.65-001) Weight: 77 mg (Typ.) Table 4-1 Mechanical Dimension for TC358749XBG Dimension Solder ball pitch Package dimension Package height Min - Typ. 0.65 mm 7.0 x 7.0 mm2 - 15 / 18 Max 1.0 mm 2017-11-13 TC358749XBG Electrical Characteristics 5.1. Absolute Maximum Ratings VSS= 0V reference Parameter Supply voltage (1.8V - Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (1.2V - MIPI CSI-2 PHY) Supply voltage (3.3V - HDMIRX Phy) Supply voltage (1.2V - HDMIRX Phy) Input voltage (CSI-2 IO) Output voltage (CSI-2 IO) Input voltage (Digital IO) Output voltage (Digital IO) Junction temperature Storage temperature Symbol Rating Unit VDDIO -0.3 to +3.9 V VDDC -0.3 to +1.8 V VDD_MIPI -0.3 to +1.8 V AVDD33 -0.3 to +3.9 V AVDD12 -0.3 to +1.8 V VIN_CSI-2 -0.3 to VDD_MIPI+0.3 V VOUT_CSI2 -0.3 to VDD_MIPI+0.3 V VIN_IO -0.3 to VDDIO+0.3 V VOUT_IO -0.3 to VDDIO+0.3 V Tj Tstg 125 -40 to +125 oC oC 5.2. Operating Condition VSS= 0V reference Parameter Symbol Min Typ. Max Unit Supply voltage (1.8/3.3V - Digital IO) Supply voltage (3.3V - HDMI Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (3.3V - HDMIRX PHY) Supply voltage (1.2V - HDMIRX PHY) Supply voltage (1.2V - MIPI CSI-2 PHY) Operating temperature (ambient temperature with voltage applied) VDDIO2 VDDIO1 VDDC AVDD33 AVDD12 VDD_MIPI 1.65 3.0 1.1 3.135 1.15 1.1 1.8 3.3 1.2 3.3 1.2 1.2 3.6 3.6 1.3 3.465 1.25 1.3 V V V V V V Ta -30 +25 +70 oC VSN - - 100 mVpp Supply Noise Voltage 16 / 18 2017-11-13 TC358749XBG Revision History Table 6-1 Revision History Revision 0.8321 0.8322 0.85 0.87 1.0 1.1 Date Description 2015-12-18 Newly released Delete TC358747XBG's descriptions 2016-02-04 Typo Init(O) DAOUT pin in External Pins 2016-09-13 Added comment to De-Interlace function. 2016-11-02 Deleted comment in part of Features. Added comment to HDCP. 2017-10-10 Changed header, footer and the last page. Changed corporate name. 2017-11-13 Modified values in Table 2-1. 17 / 18 2017-11-13 TC358749XBG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". * TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. * PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. * Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. * Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. * The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 18 / 18 2017-11-13