LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
LM4947 Mono Class D and Stereo Audio Sub-System
with OCL Headphone Amplifier and TI 3D
Check for Samples: LM4947,LM4947TLEVAL
1FEATURES DESCRIPTION
The LM4947 is an audio subsystem capable of
2• I2C Control Interface efficiently delivering 500mW (Class D operation) of
• I2C Programmable Texas Instruments 3D continuous average power into a mono 8Ωbridged-
Audio tied load (BTL) with 1% THD+N, 37mW (Class AB
• I2C Controlled 32 Step Digital Volume Control operation) power channel of continuous average
power into stereo 32Ωsingle-ended (SE) loads with
(-59.5dB to +18dB) 1% THD+N, or an output capacitor-less (OCL)
• Three Independent Volume Channels (Left, configuration with identical specification as the SE
Right, Mono) configuration, from a 3.3V power supply.
• Eight Distinct Output Modes The LM4947 has six input channels: one pair for a
• Small, 25–Bump DSBGA Packaging two-channel stereo signal, the second pair for a
• “Click and Pop” Suppression Circuitry secondary two-channel stereo input, and the third pair
for a differential single-channel mono input.
• Thermal Shutdown Protection Additionally, the two sets of stereo inputs may be
• Low Shutdown Current (0.1μA, typ) configured as a single stereo differential input
• RF Suppression (differential left and differential right). The LM4947
features a 32-step digital volume control and eight
• Differential Mono and Stereo Inputs distinct output modes. The digital volume control, 3D
• Stereo Input Mux enhancement, and output modes are programmed
through a two-wire I2C compatible interface that
KEY SPECIFICATIONS allows flexibility in routing and mixing audio channels.
• THD+N at 1kHz, 500mW into 8ΩBTL (3.3V): The RF suppression circuitry in the LM4947 makes it
1.0% (typ) well-suited for GSM mobile phones and other
• THD+N at 1kHz, 37mW into 32ΩSE (3.3V): portable applications in which strong RF signals
1.0% (typ) generated by an antenna (and long output traces)
may couple audibly into the amplifier.
• Single Supply Operation (VDD): 2.7 to 5.5 V The LM4947 is designed for cellular phones, PDAs,
• I2C Single Supply Operation: 2.2 to 5.5 V and other portable handheld applications. It delivers
high quality output power from a surface-mount
APPLICATIONS package and requires only eight external components
• Mobile Phones in the OCL mode (two additional components in SE
mode).
• PDAs
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
8:
LS-
Loud
Speaker
Mixer
and
Output
Mode
Select National
3D
Volume Control
Volume Control
Volume Control
CO
+
32:
CO
100 PF32:
+
+
VDD
0.1 PF
CS1
1 PFceramic
CS2
+
-
MUX
Interface
I2CClick/Pop
Suppression
2.2 PF
+
CB
CBypass
LS+
VOC
LHP
RHP
optional
capacitors
RIN2 or R-
RIN1 or R+
LIN1 or L+
LIN2 or L-
SDA
SCL
ADDR
I2CVDD
1 PF
1 PF
0.22 PF
0.22 PF
0.22 PF
0.22 PF
MIN+
MIN-
-59.50 dB to +18 dB
-59.50 dB to +18 dB
-59.50 dB to +18 dB
100 PF
RHP3D2
RHP3D1
LHP3D2
LHP3D1
C3DR
C3DL
+6dB
8:
LS-
Loud
Speaker
Mixer
and
Output
Mode
Select National
3D
Volume Control
Volume Control
Volume Control
32:
32:
+
VDD
0.1 PF
CS1
1 PFceramic
CS2
+
-
MUX
I2C
Interface
Click/Pop
Suppression
2.2 PF
+
CB
CBypass
LS+
optional
capacitors
RIN2 or R-
RIN1 or R+
LIN1 or L+
LIN2 or L-
SDA
SCL
ADDR
I2CVDD
1 PF
1 PF
0.22 PF
0.22 PF
0.22 PF
0.22 PF
MIN+
MIN-
-59.50 dB to +18 dB
-59.50 dB to +18 dB
-59.50 dB to +18 dB
C3DR
C3DL
+6 dB
VOC
LHP
RHP
LHP3D2
LHP3D1
RHP3D1
RHP3D2
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL APPLICATION
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
Figure 2. Typical Audio Amplifier Application Circuit-Single Ended
2Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
1
2
3
4
5RHP3D2 LHP3D2 VOC RHP LHP
RHP3D1 LHP3D1 CBYPASS AVDD GND
MIN+ MIN- SCL I2CVDD LS+
SDALIN1 LSVDD
LIN2 GND
RIN2 RIN1 ADDR AVDD LS-
A B C D E
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
CONNECTION DIAGRAM
Top View
Figure 3. 25-Bump DSBGA Package
See Package Number YZR0025BBA
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
PIN DESCRIPTIONS
Bump Name Description
A1 RIN2 Right Input Channel 2 or Right Differential Input –
A2 LIN1 Left Input Channel 1 or Left Differential Input +
A3 MIN+ Mono Channel Non-inverting Input
A4 RHP3D1 Right Headphone 3D Input 1
A5 RHP3D2 Right Headphone 3D Input 2
B1 RIN1 Right Input Channel 1 or Right Differential Input +
B2 LIN2 Left Input Channel 2 or Left Differential Input–
B3 MIN- Mono Channel Inverting Input
B4 LHP3D1 Left Headphone 3D Input 2
B5 LHP3D2 Left Headphone 3D Input 1
C1 ADDR Address Identification
C2 SDA Serial Data Input
C3 SCL Serial Clock Input
C4 CBYPASS Half-Supply Bypass Capacitor
C5 VOC Headphone return bias output
D1 AVDD Analog Power Supply
D2 LSVDD Loudspeaker Power Supply
D3 I2CVDD I2C Interface Power Supply
D4 AVDD Analog Power Supply
D5 RHP Right Headphone Output
E1 LS- Loudspeaker Output Negative
E2 GND Ground
E3 LS+ Loudspeaker Output Positive
E4 GND Ground
E5 LHP Left Headphone Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3 to VDD +0.3
ESD Susceptibility(3) 2.0kV
ESD Machine model(4) 200V
Junction Temperature (TJ) 150°C
Solder Information Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
Thermal Resistance θJA (typ) - YZR0025BBA 65°C/W
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 100pF discharged through a 1.5kΩresistor.
(4) Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
OPERATING RATINGS
Temperature Range −40°C to 85°C
Supply Voltage (VDD) 2.7V ≤VDD ≤5.5V
Supply Voltage (I2C) 2.2V ≤VDD ≤5.5V
Supply Voltage (Loudspeaker VDD) 2.7V ≤VDD ≤5.5V
ELECTRICAL CHARACTERISTICS 3.3V(1)(2)
The following specifications apply for VDD = 3.3V, TA= 25°C, and all gains are set for 0dB unless otherwise specified.
Symbol Parameter Conditions LM4947 Units
(Limits)
Typical(3) Limits(4)
Output Modes 2, 4, 6
VIN = 0V; No load, 4.5 6.5 mA (max)
OCL = 0 (Table 2)
IDDQ Quiescent Supply Current Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL, 6.5 8 mA (max)
OCL = 0 (Table 2)
ISD Shutdown Current Output Mode 0 0.1 1 µA (max)
VIN = 0V, Mode 7, Mono 2 15 mV (max)
VOS Output Offset Voltage VIN = 0V, Mode 7, Headphones 2 15 mV (max)
MONO OUT; RL= 8Ω500 400 mW (min)
THD+N = 1%; f = 1kHz, BTL, Mode 1
POOutput Power ROUT and LOUT; RL= 32Ω37 33 mW (min)
THD+N = 1%; f = 1kHz, SE, Mode 4
MONOOUT
f = 1kHz, POUT = 250mW; 0.03 %
RL= 8Ω, BTL, Mode 1
THD+N Total Harmonic Distortion Plus Noise ROUT and LOUT
f = 1kHz, POUT = 12mW; 0.02 %
RL= 32Ω, SE, Mode 4
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA= 25°C, and all gains are set for 0dB unless otherwise specified.
Symbol Parameter Conditions LM4947 Units
(Limits)
Typical(3) Limits(4)
A-weighted, 0dB
inputs terminated, output referred
Speaker; Mode 1 39 μV
Speaker; Mode 3 39 μV
Speaker; Mode 5 42 μV
Speaker; Mode 7 38 μV
NOUT Output Noise Headphone; SE, Mode 2 15 μV
Headphone; SE, Mode 4 15 μV
Headphone; SE, Mode 6 17 μV
Headphone; OCL, Mode 2 12 μV
Headphone; OCL, Mode 4 15 μV
Headphone; OCL, Mode 6 17 μV
VRIPPLE = 200mVPP; f = 217Hz,
RL= 8Ω, CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply Rejection Ratio BTL, Output Mode 1 79 dB
Loudspeaker out BTL, Output Mode 3 78 dB
BTL, Output Mode 5 79 dB
BTL, Output Mode 7 80 dB
VRIPPLE = 200mVPP; f = 217Hz,
PSRR RL= 32Ω, CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
SE, Output Mode 2 78 dB
Power Supply Rejection Ratio SE, Output Mode 4 71 dB
ROUT and LOUT SE, Output Mode 6 71 dB
OCL, Output Mode 2 83 dB
OCL, Output Mode 4 74 dB
OCL, Output Mode 6 74 dB
ηClass D Efficiency Output Mode 1, 3, 5 86 %
f = 217Hz, VCM = 1Vpp,
CMRR Common-Mode-Rejection Ratio –49 dB
Mode 1, BTL, RL= 8Ω
Headphone, PO= 12mW, –58 dB
f = 1kHz, OCL, Mode 4, RL= 32Ω
XTALK Crosstalk Headphone, PO= 12mW, –73 dB
f = 1kHz, SE, Mode 4, RL= 32Ω
CB= 2.2µF, OCL, RL= 32Ω90 ms
TWU Wake-Up Time from Shutdown CB= 2.2µF, SE, RL= 32Ω115 ms
Volume Control Step Size Error ±0.2 dB
–60.25 dB (min)
Input referred maximum attenuation -59.5 –58.75 dB (max)
Digital Volume Range 17.25 dB (min)
Input referred maximum gain +18 18.75 dB (max)
Mute Attenuation Output Mode 1, 3, 5 87 dB (min)
8 kΩ(min)
Maximum gain setting 12 14 kΩ(max)
MONO_IN Input Impedance
RIN and LIN Input Impedance 75 kΩ(min)
Maximum attenuation setting 100 125 kΩ(max)
6Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS 5V(1)(2)
The following specifications apply for VDD = 5V, TA= 25°C and all gains are set for 0dB unless otherwise specified.
Symbol Parameter Conditions LM4947 Units
(Limits)
Typical(3) Limits(4)
Output Modes 2, 4, 6
VIN = 0V; No load, 5.4 7.5 mA
OCL = 0 (Table 2)
IDDQ Quiescent Supply Current Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL, 7.6 12 mA
OCL = 0 (Table 2)
ISD Shutdown Current Output Mode 0 0.1 1 µA (max)
VIN = 0V, Mode 7, Mono 2 15 mV
(max)
VOS Output Offset Voltage VIN = 0V, Mode 7, Headphones 2 15 mV
(max)
MONOOUT; RL= 8Ω1.19 W
THD+N = 1%; f = 1kHz, BTL, Mode 1
POOutput Power ROUT and LOUT; RL= 32Ω87 mW
THD+N = 1%; f = 1kHz, SE, Mode 4
MONOOUT
f = 1kHz, POUT = 500mW; 0.04 %
RL= 8Ω, BTL, Mode 1
THD+N Total Harmonic Distortion + Noise ROUT and LOUT
f = 1kHz, POUT = 30mW; 0.01 %
RL= 32Ω, SE, Mode 4
A-weighted, 0dB
inputs terminated, output referred
Speaker; Mode 1 38 μV
Speaker; Mode 3 38 μV
Speaker; Mode 5 39 μV
Speaker; Mode 7 36 μV
NOUT Output Noise Headphone; SE, Mode 2 21 μV
Headphone; SE, Mode 4 21 μV
Headphone; SE, Mode 6 24 μV
Headphone; OCL, Mode 2 16 μV
Headphone; OCL, Mode 4 16 μV
Headphone; OCL, Mode 6 19 μV
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS 5V(1)(2) (continued)
The following specifications apply for VDD = 5V, TA= 25°C and all gains are set for 0dB unless otherwise specified.
Symbol Parameter Conditions LM4947 Units
(Limits)
Typical(3) Limits(4)
VRIPPLE = 200mVPP; f = 217Hz,
RL= 8Ω, CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply Rejection Ratio BTL, Output Mode 1 70 dB
Loudspeaker out BTL, Output Mode 3 61 dB
BTL, Output Mode 5 64 dB
BTL, Output Mode 7 61 dB
VRIPPLE = 200mVPP; f = 217Hz,
PSRR RL= 32Ω, CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
SE, Output Mode 2 72 dB
Power Supply Rejection Ratio SE, Output Mode 4 70 dB
ROUT and LOUT SE, Output Mode 6 65 dB
OCL, Output Mode 2 76 dB
OCL, Output Mode 4 72 dB
OCL, Output Mode 6 70 dB
ηClass D Efficiency Output Mode 1, 3, 5 86 %
f = 1kHz, VCM = 1Vpp, 0dB gain,
CMRR Common-Mode Rejection Ratio –49 dB
Mode 1, BTL, RL= 8Ω
Headphone, PO= 30mW, f = 1kHz, –55 dB
OCL, Mode 4
XTALK Crosstalk Headphone, PO= 30mW, f = 1kHz, –72 dB
SE, Mode 4
CB= 2.2μF, OCL, RL= 32Ω116 ms
TWU Wake-Up Time from Shutdown CB= 2.2μF, SE, RL= 32Ω150 ms
Volume Control Step Size Error ±0.2 dB
Input referred maximum attenuation -59.5 dB
Digital Volume Range Input referred maximum gain +18 dB
Mute Attenuation Output Mode 1, 3, 5 90 dB (min)
kΩ(min)
Maximum gain setting 11 kΩ(max)
MONO_IN Input Impedance
RIN and LIN Input Impedance kΩ(min)
Maximum attenuation setting 100 kΩ(max)
8Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
I2C(1)(2)
The following specifications apply for VDD = 5V and 3.3V, TA= 25°C unless otherwise specified.
Symbol Parameter Conditions LM4947 Units
(Limits)
Typical(3) Limits(4)
t1Clock Period 2.5 µs (max)
t2Clock Setup Time 100 ns (min)
t3Data Hold Time 100 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
0.7xI2C
VIH SPI Input Voltage High V (min)
VDD
0.3xI2C
VIL SPI Input Voltage Low V (max)
VDD
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
I2C Protocol Information
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1= 0, if ID_ADDR is logic LOW; and X1= 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
Figure 4. I2C Bus Format
Figure 5. I2C Timing Diagram
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM4947 LM4947TLEVAL
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m 500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m 500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m 500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 8Ω, f = 1kHz VDD = 3.3V, RL= 8Ω, f = 1kHz
Mode 1, MONO Mode 3, MONO
Figure 6. Figure 7.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 8Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In
Mode 5, MONO Mode 2, OCL
Figure 8. Figure 9.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In
Mode 2, SE Mode 4, OCL
Figure 10. Figure 11.
10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
210m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m
210m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m
210m 100m 1
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
200m 500m20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
10m 100m20m 50m
OUTPUT POWER (W)
THD+N (%)
70m30m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In
Mode 4, SE Mode 6, OCL
Figure 12. Figure 13.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz, Diff In VDD = 5V, RL= 8Ω, f = 1kHz
Mode 6, SE Mode 1, MONO
Figure 14. Figure 15.
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 8Ω, f = 1kHz VDD = 5V, RL= 8Ω, f = 1kHz
Mode 3, MONO Mode 5, MONO
Figure 16. Figure 17.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM4947 LM4947TLEVAL
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.1
1
10
THD + N (%)
20m 50m2m 5m
0.02
0.2
2
0.05
0.5
5
200m
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz, Diff In VDD = 5V, RL= 32Ω, f = 1kHz, Diff In
Mode 2, OCL Mode 2, SE
Figure 18. Figure 19.
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz, Diff In VDD = 5V, RL= 32Ω, f = 1kHz, Diff In
Mode 4, OCL Mode 4, SE
Figure 20. Figure 21.
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz, Diff In VDD = 5V, RL= 32Ω, f = 1kHz, Diff In
Mode 6, OCL Mode 6, SE
Figure 22. Figure 23.
12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
20 100 200 500 1k
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
2k 5k 10k 20k50
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
20 100 200 500 1k 2k 5k 10k 20k50
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
20 100 200 500 1k 2k 5k 10k 20k50
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
20 100 200 500 1k 2k 5k 10k 20k50
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 8Ω, PO= 250mW VDD = 3.3V, RL= 8Ω, PO= 250mW
Diff In, Mode 1 Diff In, Mode 5
Figure 24. Figure 25.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 8Ω, PO= 250mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Diff In, Mode 3 Mode 2, OCL
Figure 26. Figure 27.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 2, SE Mode 4,7, OCL
Figure 28. Figure 29.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM4947 LM4947TLEVAL
20 100 200 500 1k
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
2k 5k 10k 20k50
20 100 200 500 1k
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
2k 5k 10k 20k50
20 100 200 500 1k
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
2k 5k 10k 20k50
20 100 200 500 1k
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
THD + N (%)
2
5
0.2
0.5
0.02
0.05
0.002
0.005
2k 5k 10k 20k50
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 4,7, SE Mode 6, OCL
Figure 30. Figure 31.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 5V, RL= 8Ω, PO= 500mW
Mode 6, SE Diff In, Mode 1
Figure 32. Figure 33.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 8Ω, PO= 500mW VDD = 5V, RL= 8Ω, PO= 500mW
Diff In, Mode 3 Diff In, Mode 5
Figure 34. Figure 35.
14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 32Ω, PO= 30mW
Diff In, Mode 2, OCL Diff In, Mode 2, SE
Figure 36. Figure 37.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 32Ω, PO= 30mW
Diff In, Mode 4,7, OCL Diff In, Mode 4,7, SE
Figure 38. Figure 39.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 32Ω, PO= 30mW
Diff In, Mode 6, OCL Diff In, Mode 6, SE
Figure 40. Figure 41.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4947 LM4947TLEVAL
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, AV= 0dB VDD = 3.3V, AV= 0dB
Mode 1, MONO Mode 2, OCL
Figure 42. Figure 43.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, AV= 0dB VDD = 3.3V, AV= 0dB
Mode 2, SE Mode 3, MONO
Figure 44. Figure 45.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, AV= 0dB VDD = 3.3V, AV= 0dB
Mode 4, OCL Mode 4, SE
Figure 46. Figure 47.
16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, AV= 0dB VDD = 3.3V, AV= 0dB
Mode 5, MONO Mode 6, OCL
Figure 48. Figure 49.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, AV= 0dB VDD = 3.3V, AV= 0dB
Mode 6, SE Mode 7, MONO
Figure 50. Figure 51.
PSRR vs Frequency PSRR vs Frequency
VDD = 5V, AV= 0dB VDD = 5V, AV= 0dB
Mode 1, MONO Mode 2, OCL
Figure 52. Figure 53.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM4947 LM4947TLEVAL
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 5V, AV= 0dB VDD = 5V, AV= 0dB
Mode 2, SE Mode 3, MONO
Figure 54. Figure 55.
PSRR vs Frequency PSRR vs Frequency
VDD = 5V, AV= 0dB VDD = 5V, AV= 0dB
Mode 4, OCL Mode 4, SE
Figure 56. Figure 57.
PSRR vs Frequency PSRR vs Frequency
VDD = 5V, AV= 0dB VDD = 5V, AV= 0dB
Mode 5, MONO Mode 6, OCL
Figure 58. Figure 59.
18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 50
250
50
100
150
200
10 20 30 40
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00
120
100 200 300 400 500
20
40
60
80
100
600 700
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00
250
10 20 30 40
50
100
150
200
5 15 25 35 45 50
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 50
10
20
30
40
50
60
70
80
90
100
5 10 15 20 25 30 35 40 45
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 5V, AV= 0dB VDD = 5V, AV= 0dB
Mode 6, SE Mode 7, MONO
Figure 60. Figure 61.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 7, OCL Mode 7, SE
Figure 62. Figure 63.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.3V, RL= 8Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 1, 3, 5, MONO Mode 2, 4, 6, OCL
Figure 64. Figure 65.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM4947 LM4947TLEVAL
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 120
500
40 60 80 100
50
100
150
200
250
300
350
400
450
20
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 120
200
40 60 80 10020
20
40
60
80
100
120
140
160
180
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 50
160
80
100
120
140
10 20 30 40
20
40
60
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00
300
1600
50
100
150
200
250
400 800 1200
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00
10
20
30
40
50
60
70
10 20 30 40
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
00 50
350
10 20 30 40
50
100
150
200
250
300
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz VDD = 5V, RL= 32Ω, f = 1kHz
Mode 2, 4, 6, SE Mode 7, OCL
Figure 66. Figure 67.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz VDD = 5V, RL= 8Ω, f = 1kHz
Mode 7, SE Mode 1, 3, 5, MONO
Figure 68. Figure 69.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz VDD = 5V, RL= 32Ω, f = 1kHz
Mode 2, 4, 6, OCL Mode 2, 4, 6, SE
Figure 70. Figure 71.
20 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
0
14
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2
4
6
8
10
12
0
2
4
6
8
10
12
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
FREQUENCY (Hz)
+0
20 100 200 500 1k 2k 5k 10k 20k50
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
Left to right
Right to left
CROSSTALK (dB)
FREQUENCY (Hz)
+0
20 100 200 500 1k 2k 5k 10k 20k50
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
Right to left
Left to right
CROSSTALK (dB)
FREQUENCY (Hz)
+0
CROSSTALK (dB)
20 100 200 500 1k 2k 5k 10k 20k50
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
Left to right
Right to left
FREQUENCY (Hz)
+0
20 100 200 500 1k 2k 5k 10k 20k50
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
Right to left
Left to right
CROSSTALK (dB)
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 4, OCL Mode 4, SE
Figure 72. Figure 73.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 32Ω, PO= 30mW
Mode 4, OCL Mode 4, SE
Figure 74. Figure 75.
Supply Current vs Supply Voltage Supply Current vs Supply Voltage
No Load, Mode 7, OCL No Load, Mode 7, SE
Figure 76. Figure 77.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4947 LM4947TLEVAL
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
20
40
60
80
100
120
140
160
180
THD+N = 10%
THD+N = 1%
0
180
3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
20
40
60
80
100
120
140
160
THD+N = 10%
THD+N = 1%
2.5
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
500
1000
1500
2000
2500
THD+N = 10%
THD+N = 1%
1
2
3
4
5
6
7
8
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
0
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1
2
3
4
5
6
7
8
9
0
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1
2
3
4
5
6
7
8
9
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Supply Current vs Supply Voltage Supply Current vs Supply Voltage
No Load, Mode 1, 3, 5, MONO No Load, Mode 2, 4, 6, OCL
Figure 78. Figure 79.
Supply Current vs Supply Voltage Output Power vs Supply Voltage
No Load, Mode 2, 4, 6, Headphone SE RL= 8Ω, Mode 1, 3, 5, MONO
Figure 80. Figure 81.
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 32Ω, Mode 2, 4, 6, OCL RL= 32Ω, Mode 2, 4, 6, SE
Figure 82. Figure 83.
22 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
0
0.2
0.4
0.6
0.8
1
0 200 400 600 800
OUTPUT POWER (mW)
EFFICIENCY (%)
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000 120014001600
EFFICIENCY (%)
OUTPUT POWER (mW)
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
20
40
60
80
100
120
140
160
180
THD+N = 10%
THD+N = 1%
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
20
40
60
80
100
120
140
160
180
THD+N = 10%
THD+N = 1%
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 32Ω, Mode 7, OCL RL= 32Ω, Mode 7, SE
Figure 84. Figure 85.
Efficiency vs Output Power Efficiency vs Output Power
VDD = 3.3V, RL= 8Ω, Mode 1, 3, 5, BTL VDD = 5V, RL= 8Ω, Mode 1, 3, 5, BTL
Figure 86. Figure 87.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
APPLICATION INFORMATION
I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I2C COMPATIBLE INTERFACE
The LM4947 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4947.
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1= 0, if ID_ADDR is logic LOW; and X1= 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 4. The bus format diagram is broken up into six major
sections:
1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the
clock. Each address bit must be stable while the clock level is HIGH.
3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up
resistor). Then the master sends an acknowledge clock pulse. If the LM4947 has received the address
correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the
acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4947.
4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
5. After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received
the data.
6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is
HIGH. The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4947's I2C interface is powered up through the I2CVDD pin. The LM4947's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Table 1. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 1 1 1 1 1 0 EC 0
ID_ADDR = 0 1 1 1 1 1 0 0 0
ID_ADDR = 1 1 1 1 1 1 0 1 0
24 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
Table 2. Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
Mode Control 0 0 SE/Diff 0 OCL (select) MC2 MC1 MC0
(select)
Programmable 3D 0 1 L2R2 L1R1 (select) N3D3 N3D2 N3D1 N3D0
(select)
Mono Volume Control 1 0 0 MVC4 MVC3 MVC2 MVC1 MVC0
Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0
Right Volume Control 1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0
Table 3. Programmable Texas Instruments 3D Audio
N3D3 N3D2
Low 0 0
Medium 0 1
High 1 0
Maximum 1 1
Table 4. Input/Output Control
L2R2 L1R1 SE/DIFF
Select LIN1 and RIN1 Stereo Pair 0 1 0
Select LIN2 and RIN2 Stereo Pair 1 0 0
Select LIN1+LIN2 and RIN1+RIN2 Stereo Pair 1 1 0
Sets Stereo Inputs to Differential x x 1
Table 5. Output Volume Control Table
Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain, dB
1 0 0 0 0 0 –59.50
2 0 0 0 0 1 –48.00
3 0 0 0 1 0 –40.50
4 0 0 0 1 1 –34.50
5 0 0 1 0 0 –30.00
6 0 0 1 0 1 –27.00
7 0 0 1 1 0 –24.00
8 0 0 1 1 1 –21.00
9 0 1 0 0 0 –18.00
10 0 1 0 0 1 –15.00
11 0 1 0 1 0 –13.50
12 0 1 0 1 1 –12.00
13 0 1 1 0 0 –10.50
14 0 1 1 0 1 –9.00
15 0 1 1 1 0 –7.50
16 0 1 1 1 1 –6.00
17 1 0 0 0 0 –4.50
18 1 0 0 0 1 –3.00
19 1 0 0 1 0 –1.50
20 1 0 0 1 1 0.00
21 1 0 1 0 0 1.50
22 1 0 1 0 1 3.00
23 1 0 1 1 0 4.50
24 1 0 1 1 1 6.00
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM4947 LM4947TLEVAL
LM4947
LHP3D1
LHP3D2
RHP3D1
RHP3D2
C3DR
C3DL
C3DL C3DR
20 k:
(internal resistors)
20 k:
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
Table 5. Output Volume Control Table (continued)
Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain, dB
25 1 1 0 0 0 7.50
26 1 1 0 0 1 9.00
27 1 1 0 1 0 10.50
28 1 1 0 1 1 12.00
29 1 1 1 0 0 13.50
30 1 1 1 0 1 15.00
31 1 1 1 1 0 16.50
32 1 1 1 1 1 18.00
Table 6. Output Mode Selection
Output Mode MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output
Number
0 0 0 0 SD SD SD
1 0 0 1 2 x GMx M MUTE MUTE
2 0 1 0 SD GMx M GMx M
3 0 1 1 GLx L + GRx R MUTE MUTE
4 1 0 0 SD GRx R GLx L
5 1 0 1 GLx L + GRx R + 2(GMx M) MUTE MUTE
6 1 1 0 SD GRx R + GMx M GLx L + GMx M
7 1 1 1 GRx R + GLx L GRx R GLx L
TI 3D ENHANCEMENT
The LM4947 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo
headphone listening. The LM4947 can be programmed for a “narrow” or “wide” soundstage perception. The
narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial,
theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:
low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The
difference between each level is 3dB.
The external capacitors, shown in Figure 88, are required to enable the 3D effect. The value of the capacitors set
the cutoff frequency of the 3D effect, as shown by Equation 1 and Equation 2. Note that the internal 20kΩ
resistor is nominal (±25%).
Figure 88. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π* 20kΩ* C3DL (1)
f3DR(-3dB) = 1 / 2π* 20kΩ* C3DR (2)
Optional resistors R3DL and R3DR can also be added (Figure 89) to affect the -3dB frequency and 3D magnitude.
26 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947
LHP3D1
LHP3D2
RHP3D1
RHP3D2
C3DR
C3DL
R3DL R3DR
20 k:
(internal resistors)
20 k:
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
Figure 89. External RC Network with Optional R3DL and R3DR Resistors
f3DL(-3dB) = 1 / 2π* (20kΩ+ R3DL) * C3DL (3)
f3DR(-3dB) = 1 / 2π* 20kΩ+ R3DR) * C3DR (4)
ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ(see
example below).
f3dB (3D) = 1 / 2π(1 + M)(20kΩ* C3D) (5)
CEquivalent (new) = C3D / 1 + M (6)
Table 7. Pole Locations
R3D (kΩ) C3D (nF) M ΔAV (dB) f-3dB (3D) Value of C3D new Pole
(optional) (Hz) to keep same Location
pole location (Hz)
(nF)
0 68 0 0 117
1 68 0.05 –0.4 111 64.8 117
5 68 0.25 –1.9 94 54.4 117
10 68 0.50 –3.5 78 45.3 117
20 68 1.00 –6.0 59 34.0 117
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8ΩLOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ωload from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
POWER DISSIPATION AND EFFICIENCY
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required
to produce it with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For
audio systems, the energy delivered in the audible bands is considered useful including the distortion products of
the input signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between
the power flowing from the power supply and the audio band power being transduced is dissipated in the
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
LM4947 and in the transducer load. The amount of power dissipation in the LM4947 is very low. This is because
the ON resistance of the switches used to form the output waveforms is typically less than 0.25Ω. This leaves
only the transducer load as a potential "sink" for the small excess of input power over audio band output power.
The LM4947 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to
act as a heat sink.
The LM4947 also has a pair of single-ended amplifiers driving stereo headphones, RHP and LHP. The maximum
internal power dissipation for RHP and LHP is given by Equation 7 and Equation 8. From Equation 7 and
Equation 8, assuming a 5V power supply and a 32Ωload, the maximum power dissipation for LHP and RHP is
40mW, or 80mW total.
PDMAX-LHP = (VDD)2/ (2π2RL): Single-ended Mode (7)
PDMAX-RHP = (VDD)2/ (2π2RL): Single-ended Mode (8)
The maximum internal power dissipation of the LM4947 occurs when all 3 amplifiers pairs are simultaneously on;
and is given by Equation 9.
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LHP + PDMAX-RHP (9)
The maximum power dissipation point given by Equation 9 must not exceed the power dissipation given by
Equation 10:
PDMAX = (TJMAX - TA) / θJA (10)
The LM4947's TJMAX = 150°C. In the ITL package, the LM4947's θJA is 65°C/W. At any given ambient
temperature TA, use Equation 10 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 10 and substituting PDMAX-TOTAL for PDMAX' results in Equation 11. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4947's
maximum junction temperature.
TA= TJMAX - PDMAX-TOTAL θJA (11)
For a typical application with a 5V power supply and an 8Ωload, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104°C
for the ITL package.
TJMAX = PDMAX-TOTAL θJA + TA(12)
Equation 12 gives the maximum junction temperature TJMAX. If the result violates the LM4947's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 9 is greater than that of Equation 10,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC,θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the
TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation information at lower output power
levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.1µF tantalum bypass capacitance connected
between the LM4947's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4947's power supply pin and ground as short as possible. Connecting a 2.2µF capacitor, CB,
between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's
PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however,
increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass
capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as
explained in the section, SELECTING EXTERNAL COMPONENTS), system cost, and size constraints.
28 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ciin Figure 1 and
Figure 2). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In
many cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using large input capacitor.
The internal input resistor (Ri), nominal 20kΩ, and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation 13.
fc= 1 / (2πRiCi) (13)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 13 is 0.053µF. The
0.22µF Cishown in Figure 1 allows the LM4947 to drive high efficiency, full range speaker whose response
extends below 40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS bump. Since CBdetermines how fast the LM4947 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4947's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CBequal to 1.0µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Cino larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4947 resumes operation after shutdown.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
DEMO BOARD SCHEMATIC
Figure 90.
30 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4947 LM4947TLEVAL
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
REVISION HISTORY
Rev Date Description
1.0 06/16/06 Initial release.
1.1 06/19/06 Changed the Class D Efficiency (n) on Typical limit (from 79 to 86) on the 5V
specification table.
1.2 06/22/06 Added more Typ Perf curves.
1.3 07/18/06 Replaced some of the curves.
1.4 08/29/06 Text edits.
1.5 10/18/06 Edited DSBGA pkg drawing, Figure 1 and Figure 2.
Changed IDDQ typical and limit values on the 3.3V and 5.0V specification table.
Removed CMRR SE condition and changed typical values for CMRR BTL on
3.3V and 5.0V specification table.
Changed Mute Attenuation typical value on 5.0V specification table.
1.6 03/02/07 Edited the 3.3V and 5V EC tables.
1.7 03/02/07 Composed (CONFIDENTIAL) D/S for customer (SAMSUNG).
1.8 09/06/07 Edited Table 4.
1.9 11/09/07 Text edits.
D 05/03/13 Changed layout of National Data Sheet to TI format.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: LM4947 LM4947TLEVAL
PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4947TL/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GH1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2014
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4947TL/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4947TL/NOPB DSBGA YZR 25 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
MECHANICAL DATA
YZR0025xxx
www.ti.com
TLA25XXX (Rev D)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215055/A 12/12
D: Max =
E: Max =
2.532 mm, Min =
2.532 mm, Min =
2.472 mm
2.472 mm
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM4947TL/NOPB LM4947TLX/NOPB