LM4947, LM4947TLEVAL www.ti.com LM4947 SNAS349D - JUNE 2006 - REVISED MAY 2013 Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifier and TI 3D Check for Samples: LM4947, LM4947TLEVAL FEATURES 1 * * 2 * * * * * * * * * * 2 I C Control Interface I2C Programmable Texas Instruments 3D Audio I2C Controlled 32 Step Digital Volume Control (-59.5dB to +18dB) Three Independent Volume Channels (Left, Right, Mono) Eight Distinct Output Modes Small, 25-Bump DSBGA Packaging "Click and Pop" Suppression Circuitry Thermal Shutdown Protection Low Shutdown Current (0.1A, typ) RF Suppression Differential Mono and Stereo Inputs Stereo Input Mux KEY SPECIFICATIONS * * * * THD+N at 1kHz, 500mW into 8 BTL (3.3V): 1.0% (typ) THD+N at 1kHz, 37mW into 32 SE (3.3V): 1.0% (typ) Single Supply Operation (VDD): 2.7 to 5.5 V I2C Single Supply Operation: 2.2 to 5.5 V APPLICATIONS * * Mobile Phones PDAs DESCRIPTION The LM4947 is an audio subsystem capable of efficiently delivering 500mW (Class D operation) of continuous average power into a mono 8 bridgedtied load (BTL) with 1% THD+N, 37mW (Class AB operation) power channel of continuous average power into stereo 32 single-ended (SE) loads with 1% THD+N, or an output capacitor-less (OCL) configuration with identical specification as the SE configuration, from a 3.3V power supply. The LM4947 has six input channels: one pair for a two-channel stereo signal, the second pair for a secondary two-channel stereo input, and the third pair for a differential single-channel mono input. Additionally, the two sets of stereo inputs may be configured as a single stereo differential input (differential left and differential right). The LM4947 features a 32-step digital volume control and eight distinct output modes. The digital volume control, 3D enhancement, and output modes are programmed through a two-wire I2C compatible interface that allows flexibility in routing and mixing audio channels. The RF suppression circuitry in the LM4947 makes it well-suited for GSM mobile phones and other portable applications in which strong RF signals generated by an antenna (and long output traces) may couple audibly into the amplifier. The LM4947 is designed for cellular phones, PDAs, and other portable handheld applications. It delivers high quality output power from a surface-mount package and requires only eight external components in the OCL mode (two additional components in SE mode). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2013, Texas Instruments Incorporated LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL APPLICATION VDD 0.1 PF ceramic 1 PF + optional capacitors CS2 CS1 Loud Speaker 1 PF + MIN+ LS+ Volume Control -59.50 dB to +18 dB 1 PF +6 dB 8: - MIN- LS- 0.22 PF LIN1 or L Mixer Volume Control -59.50 dB to +18 dB 0.22 PF LIN2 or L - 32: Output Mode VOC National 3D Select 0.22 PF RIN1 or R RHP and + MUX + RIN2 or R LHP Volume Control -59.50 dB to +18 dB 0.22 PF - 32: CB Click/Pop Suppression 2 CBypass 2.2 PF RHP3D2 RHP3D1 LHP3D1 SCL ADDR LHP3D2 I C Interface + 2 I CVDD SDA C 3DL C 3DR Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less VDD 0.1 PF ceramic 1 PF + optional capacitors CS1 Loud CS2 Speaker 1 PF + MIN+ LS+ Volume Control -59.50 dB to +18 dB 1 PF +6dB 8: - MIN- LSMixer 0.22 PF + LIN2 or L - 100 PF Mode VOC National MUX 3D + RIN2 or R - CO L HP Volume Control -59.50 dB to +18 dB 0.22 PF 32: + RIN1 or R Output Select 0.22 PF 32: + Volume Control -59.50 dB to +18 dB 0.22 PF CO R HP and 100 PF CB 2 R HP3D1 Interface CBypass R HP3D2 Click/Pop Suppression LHP3D2 SCL ADDR 2 I C L HP3D1 I CVDD SDA + LIN1 or L 2.2 PF C 3DL C 3DR Figure 2. Typical Audio Amplifier Application Circuit-Single Ended 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 CONNECTION DIAGRAM Top View A B C D E 5 RHP3D2 LHP3D2 VOC RHP LHP 4 RHP3D1 LHP3D1 CBYPASS AVDD GND 3 MIN+ MIN- SCL I2CVDD LS+ 2 LIN1 LIN2 SDA LSVDD GND 1 RIN2 RIN1 ADDR AVDD LS- Figure 3. 25-Bump DSBGA Package See Package Number YZR0025BBA Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 3 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com PIN DESCRIPTIONS Bump Name Description A1 RIN2 Right Input Channel 2 or Right Differential Input - A2 LIN1 Left Input Channel 1 or Left Differential Input + A3 MIN+ A4 RHP3D1 Right Headphone 3D Input 1 A5 RHP3D2 Right Headphone 3D Input 2 B1 RIN1 Right Input Channel 1 or Right Differential Input + B2 LIN2 Left Input Channel 2 or Left Differential Input- B3 MIN- Mono Channel Inverting Input B4 LHP3D1 Left Headphone 3D Input 2 B5 LHP3D2 Left Headphone 3D Input 1 C1 ADDR Address Identification C2 SDA Serial Data Input C3 SCL Serial Clock Input C4 CBYPASS Half-Supply Bypass Capacitor C5 VOC Headphone return bias output D1 AVDD Analog Power Supply D2 LSVDD Loudspeaker Power Supply D3 I2CVDD I2C Interface Power Supply D4 AVDD D5 RHP Right Headphone Output E1 LS- Loudspeaker Output Negative E2 GND Ground E3 LS+ Loudspeaker Output Positive E4 GND Ground E5 LHP Mono Channel Non-inverting Input Analog Power Supply Left Headphone Output These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage 6.0V Storage Temperature -65C to +150C Input Voltage -0.3 to VDD +0.3 ESD Susceptibility (3) ESD Machine model 2.0kV (4) 200V Junction Temperature (TJ) 150C Solder Information Vapor Phase (60 sec.) 215C Infrared (15 sec.) (1) (2) (3) (4) 220C JA (typ) - YZR0025BBA Thermal Resistance 65C/W Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 100pF discharged through a 1.5k resistor. Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50). OPERATING RATINGS -40C to 85C Temperature Range Supply Voltage (VDD) 2.7V VDD 5.5V Supply Voltage (I2C) 2.2V VDD 5.5V Supply Voltage (Loudspeaker VDD) 2.7V VDD 5.5V ELECTRICAL CHARACTERISTICS 3.3V (1) (2) The following specifications apply for VDD = 3.3V, TA = 25C, and all gains are set for 0dB unless otherwise specified. Symbol Parameter Conditions LM4947 Typical IDDQ ISD Quiescent Supply Current Shutdown Current VOS Output Offset Voltage PO Output Power THD+N (1) (2) (3) (4) Total Harmonic Distortion Plus Noise (3) Limits (4) Units (Limits) Output Modes 2, 4, 6 VIN = 0V; No load, OCL = 0 (Table 2) 4.5 6.5 mA (max) Output Modes 1, 3, 5, 7 VIN = 0V; No load, BTL, OCL = 0 (Table 2) 6.5 8 mA (max) Output Mode 0 0.1 1 A (max) VIN = 0V, Mode 7, Mono 2 15 mV (max) VIN = 0V, Mode 7, Headphones 2 15 mV (max) MONO OUT; RL = 8 THD+N = 1%; f = 1kHz, BTL, Mode 1 500 400 mW (min) ROUT and LOUT; RL = 32 THD+N = 1%; f = 1kHz, SE, Mode 4 37 33 mW (min) MONOOUT f = 1kHz, POUT = 250mW; RL = 8, BTL, Mode 1 0.03 % ROUT and LOUT f = 1kHz, POUT = 12mW; RL = 32, SE, Mode 4 0.02 % Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25C and represent the most likely parametric norm. Tested limits are specified to AOQL (Average Outgoing Quality Level). Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 5 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS 3.3V(1)(2) (continued) The following specifications apply for VDD = 3.3V, TA = 25C, and all gains are set for 0dB unless otherwise specified. Symbol Parameter Conditions LM4947 Typical (3) Limits (4) Units (Limits) A-weighted, 0dB inputs terminated, output referred NOUT Output Noise Speaker; Mode 1 39 V Speaker; Mode 3 39 V Speaker; Mode 5 42 V Speaker; Mode 7 38 V Headphone; SE, Mode 2 15 V Headphone; SE, Mode 4 15 V Headphone; SE, Mode 6 17 V Headphone; OCL, Mode 2 12 V Headphone; OCL, Mode 4 15 V Headphone; OCL, Mode 6 17 V BTL, Output Mode 1 79 dB BTL, Output Mode 3 78 dB BTL, Output Mode 5 79 dB BTL, Output Mode 7 80 dB SE, Output Mode 2 78 dB SE, Output Mode 4 71 dB SE, Output Mode 6 71 dB OCL, Output Mode 2 83 dB OCL, Output Mode 4 74 dB OCL, Output Mode 6 74 dB VRIPPLE = 200mVPP; f = 217Hz, RL = 8, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Power Supply Rejection Ratio Loudspeaker out VRIPPLE = 200mVPP; f = 217Hz, RL = 32, CB = 2.2F, BTL All audio inputs terminated to GND; output referred PSRR Power Supply Rejection Ratio ROUT and LOUT Class D Efficiency Output Mode 1, 3, 5 86 % CMRR Common-Mode-Rejection Ratio f = 217Hz, VCM = 1Vpp, Mode 1, BTL, RL = 8 -49 dB Headphone, PO = 12mW, f = 1kHz, OCL, Mode 4, RL = 32 -58 dB Headphone, PO = 12mW, f = 1kHz, SE, Mode 4, RL = 32 -73 dB CB = 2.2F, OCL, RL = 32 90 ms 115 ms XTALK TWU Crosstalk Wake-Up Time from Shutdown CB = 2.2F, SE, RL = 32 Volume Control Step Size Error 0.2 Input referred maximum attenuation -59.5 Input referred maximum gain +18 17.25 18.75 Output Mode 1, 3, 5 87 Maximum gain setting 12 8 14 k (min) k (max) Maximum attenuation setting 100 75 125 k (min) k (max) Digital Volume Range Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance 6 Submit Documentation Feedback dB -60.25 -58.75 dB (min) dB (max) dB (min) dB (max) dB (min) Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 ELECTRICAL CHARACTERISTICS 5V (1) (2) The following specifications apply for VDD = 5V, TA = 25C and all gains are set for 0dB unless otherwise specified. Symbol Parameter Conditions LM4947 Typical IDDQ ISD Quiescent Supply Current Shutdown Current VOS Output Offset Voltage PO Output Power THD+N Total Harmonic Distortion + Noise (3) Limits (4) Units (Limits) Output Modes 2, 4, 6 VIN = 0V; No load, OCL = 0 (Table 2) 5.4 7.5 mA Output Modes 1, 3, 5, 7 VIN = 0V; No load, BTL, OCL = 0 (Table 2) 7.6 12 mA Output Mode 0 0.1 1 A (max) VIN = 0V, Mode 7, Mono 2 15 mV (max) VIN = 0V, Mode 7, Headphones 2 15 mV (max) MONOOUT; RL = 8 THD+N = 1%; f = 1kHz, BTL, Mode 1 1.19 W ROUT and LOUT; RL = 32 THD+N = 1%; f = 1kHz, SE, Mode 4 87 mW MONOOUT f = 1kHz, POUT = 500mW; RL = 8, BTL, Mode 1 0.04 % ROUT and LOUT f = 1kHz, POUT = 30mW; RL = 32, SE, Mode 4 0.01 % Speaker; Mode 1 38 V Speaker; Mode 3 38 V Speaker; Mode 5 39 V Speaker; Mode 7 36 V Headphone; SE, Mode 2 21 V Headphone; SE, Mode 4 21 V Headphone; SE, Mode 6 24 V Headphone; OCL, Mode 2 16 V Headphone; OCL, Mode 4 16 V Headphone; OCL, Mode 6 19 V A-weighted, 0dB inputs terminated, output referred NOUT (1) (2) (3) (4) Output Noise Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25C and represent the most likely parametric norm. Tested limits are specified to AOQL (Average Outgoing Quality Level). Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 7 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS 5V(1)(2) (continued) The following specifications apply for VDD = 5V, TA = 25C and all gains are set for 0dB unless otherwise specified. Symbol Parameter Conditions LM4947 Typical (3) Limits (4) Units (Limits) VRIPPLE = 200mVPP; f = 217Hz, RL = 8, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Power Supply Rejection Ratio Loudspeaker out Power Supply Rejection Ratio ROUT and LOUT CMRR XTALK TWU 70 dB BTL, Output Mode 3 61 dB BTL, Output Mode 5 64 dB BTL, Output Mode 7 61 dB SE, Output Mode 2 72 dB SE, Output Mode 4 70 dB SE, Output Mode 6 65 dB OCL, Output Mode 2 76 dB OCL, Output Mode 4 72 dB VRIPPLE = 200mVPP; f = 217Hz, RL = 32, CB = 2.2F, BTL All audio inputs terminated to GND; output referred PSRR BTL, Output Mode 1 OCL, Output Mode 6 70 dB Class D Efficiency Output Mode 1, 3, 5 86 % Common-Mode Rejection Ratio f = 1kHz, VCM = 1Vpp, 0dB gain, Mode 1, BTL, RL = 8 -49 dB Headphone, PO = 30mW, f = 1kHz, OCL, Mode 4 -55 dB Headphone, PO = 30mW, f = 1kHz, SE, Mode 4 -72 dB CB = 2.2F, OCL, RL = 32 116 ms CB = 2.2F, SE, RL = 32 150 ms 0.2 dB Input referred maximum attenuation -59.5 dB Input referred maximum gain +18 dB Output Mode 1, 3, 5 90 dB (min) Maximum gain setting 11 k (min) k (max) Maximum attenuation setting 100 k (min) k (max) Crosstalk Wake-Up Time from Shutdown Volume Control Step Size Error Digital Volume Range Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance 8 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 I2C (1) (2) The following specifications apply for VDD = 5V and 3.3V, TA = 25C unless otherwise specified. Symbol Parameter Conditions LM4947 Typical (3) Limits (4) Units (Limits) t1 Clock Period 2.5 s (max) t2 Clock Setup Time 100 ns (min) t3 Data Hold Time 100 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) V (min) V (max) VIH SPI Input Voltage High 0.7xI2C VDD VIL SPI Input Voltage Low 0.3xI2C VDD (1) (2) (3) (4) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25C and represent the most likely parametric norm. Tested limits are specified to AOQL (Average Outgoing Quality Level). I2C Protocol Information The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can be changed to avoid any possible address conflicts. Figure 4. I2C Bus Format Figure 5. I2C Timing Diagram Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 9 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 3, MONO 10 10 5 5 2 2 1 1 THD + N (%) THD + N (%) THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 1, MONO 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 1m 2m OUTPUT POWER (W) OUTPUT POWER (W) Figure 6. Figure 7. THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 5, MONO THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 2, OCL 10 10 5 5 2 1 THD + N (%) THD + N (%) 2 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 1m 5m 10m 20m 50m 100m 200m 500m 1 2m 10m 20m 50m 100m Figure 8. Figure 9. THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 2, SE THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 4, OCL 10 10 5 5 2 2 1 THD + N (%) THD + N (%) 5m OUTPUT POWER (W) OUTPUT POWER (W) 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m 50m 100m 1m OUTPUT POWER (W) Submit Documentation Feedback 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 10. 10 5m 10m 20m 50m 100m 200m 500m 1 Figure 11. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 6, OCL 10 10 5 5 2 2 1 THD + N (%) THD + N (%) THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 4, SE 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m 50m 100m 1m OUTPUT POWER (W) 10m 20m 50m 100m OUTPUT POWER (W) Figure 13. THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 6, SE THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 1, MONO 10 10 5 5 2 2 THD + N (%) THD+N (%) 5m Figure 12. 1 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 10m 0.01 20m 30m 2m 50m 70m 100m OUTPUT POWER (W) 5m 10m 20m 50m 100m 200m 500m 1 Figure 15. THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 3, MONO THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 5, MONO 10 10 5 5 2 2 1 0.5 0.2 2 OUTPUT POWER (W) Figure 14. THD + N (%) THD + N (%) 2m 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m10m 20m 50m100m 200m 500m 1 2 1m 2m 5m10m 20m 50m100m 200m 500m 1 2 OUTPUT POWER (W) OUTPUT POWER (W) Figure 16. Figure 17. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 11 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 5 5 2 2 1 THD + N (%) THD + N (%) 10 THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 2, OCL 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 2, SE 50m 100m 200m 1m 2m OUTPUT POWER (W) OUTPUT POWER (W) Figure 19. THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 4, OCL THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 4, SE 10 5 5 2 2 1 1 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m 50m 100m 200m 1m 2m OUTPUT POWER (W) 50m 100m 200m OUTPUT POWER (W) Figure 21. THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 6, OCL THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 6, SE 10 5 5 2 2 1 0.5 0.2 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 1m 2m 5m 10m 20m 50m 100m 200m 1m OUTPUT POWER (W) Submit Documentation Feedback 2m 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) Figure 22. 12 5m 10m 20m Figure 20. THD + N (%) THD + N (%) 10 50m 100m 200m Figure 18. THD + N (%) THD + N (%) 10 5m 10m 20m Figure 23. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 5 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 1 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 50 100 200 500 1k 2k 20 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Figure 25. THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 3 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 2, OCL 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 0.02 0.01 0.005 0.002 0.001 20 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 0.002 0.001 20 50 100 200 500 1k 2k 20 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Figure 27. THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 2, SE THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4,7, OCL 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 0.2 0.1 0.05 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 28. Figure 29. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL 5k 10k 20k Submit Documentation Feedback 13 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4,7, SE 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.002 0.001 10 5 50 100 200 500 1k 2k 20 5k 10k 20k FREQUENCY (Hz) Figure 31. THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 6, SE THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 1 10 5 2 1 0.5 THD + N (%) THD + N (%) 5k 10k 20k Figure 30. 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. Figure 33. THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 3 THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 5 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 50 100 200 500 1k 2k FREQUENCY (Hz) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 14 0.2 0.1 0.05 0.02 0.01 0.005 20 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 6, OCL 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 34. Figure 35. Submit Documentation Feedback 5k 10k 20k Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 5 THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 2, OCL 10 5 2 1 0.5 THD + N (%) THD + N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 50 100 200 500 1k 2k 20 5k 10k 20k FREQUENCY (Hz) Figure 36. Figure 37. THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 4,7, OCL THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 4,7, SE 10 5 2 1 0.5 THD + N (%) THD + N (%) 50 100 200 500 1k 2k FREQUENCY (Hz) 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 20 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 38. Figure 39. THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 6, OCL THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 6, SE 10 5 2 1 0.5 THD + N (%) 2 1 0.5 THD + N (%) 0.02 0.01 0.005 5k 10k 20k 2 1 0.5 10 5 0.2 0.1 0.05 0.002 0.001 20 10 5 THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 2, SE 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 40. Figure 41. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL 5k 10k 20k Submit Documentation Feedback 15 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) -20 -20 -30 -30 -50 -60 PSRR (dB) -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k FREQUENCY (Hz) Figure 42. Figure 43. PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 2, SE PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 3, MONO -10 -20 -20 -30 -30 PSRR (dB) +0 -10 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 44. Figure 45. PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 4, OCL PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 4, SE +0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) +0 +0 16 PSRR (dB) -10 -40 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 2, OCL +0 -10 PSRR (dB) PSRR (dB) PSRR (dB) +0 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 1, MONO 50 100 200 500 1k 2k 5k 10k 20k -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 46. Figure 47. Submit Documentation Feedback 5k 10k 20k Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) +0 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k FREQUENCY (Hz) Figure 48. Figure 49. PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 6, SE PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 7, MONO +0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) PSRR (dB) PSRR (dB) PSRR (dB) +0 -10 +0 PSRR (dB) PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 6, OCL 50 100 200 500 1k 2k -100 20 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 50. Figure 51. PSRR vs Frequency VDD = 5V, AV = 0dB Mode 1, MONO PSRR vs Frequency VDD = 5V, AV = 0dB Mode 2, OCL +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) PSRR (dB) PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 5, MONO -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 52. Figure 53. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL 5k 10k 20k Submit Documentation Feedback 17 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 18 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 3, MONO +0 -10 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) +0 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 54. Figure 55. PSRR vs Frequency VDD = 5V, AV = 0dB Mode 4, OCL PSRR vs Frequency VDD = 5V, AV = 0dB Mode 4, SE +0 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) +0 -10 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 56. Figure 57. PSRR vs Frequency VDD = 5V, AV = 0dB Mode 5, MONO PSRR vs Frequency VDD = 5V, AV = 0dB Mode 6, OCL +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) PSRR (dB) PSRR (dB) PSRR (dB) PSRR vs Frequency VDD = 5V, AV = 0dB Mode 2, SE -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 58. Figure 59. Submit Documentation Feedback 5k 10k 20k Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) PSRR vs Frequency VDD = 5V, AV = 0dB Mode 7, MONO +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 PSRR (dB) PSRR (dB) PSRR vs Frequency VDD = 5V, AV = 0dB Mode 6, SE -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 60. Figure 61. Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 7, OCL Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 7, SE 250 100 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 90 200 150 100 50 80 70 60 50 40 30 20 10 0 0 5 0 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 OUTPUT POWER (mW) OUTPUT POWER (mW) Figure 62. Figure 63. Power Dissipation vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 1, 3, 5, MONO Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 2, 4, 6, OCL 120 250 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 100 80 60 40 20 0 0 100 200 300 400 500 600 700 200 150 100 50 0 0 OUTPUT POWER (mW) Figure 64. 10 20 30 40 50 OUTPUT POWER (mW) Figure 65. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 19 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 7, OCL 70 350 60 300 POWER DISSIPATION (mW) POWER DISSIPATION (mW) Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 2, 4, 6, SE 50 40 30 20 10 0 250 200 150 100 50 10 0 20 30 0 40 0 10 50 Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 7, SE Power Dissipation vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 1, 3, 5, MONO 300 250 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 40 Figure 67. 140 120 100 80 60 40 0 200 150 100 50 20 0 10 20 30 40 0 50 0 400 OUTPUT POWER (mW) 800 1200 1600 OUTPUT POWER (mW) Figure 68. Figure 69. Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 2, 4, 6, OCL Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 2, 4, 6, SE 500 200 450 180 400 160 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 30 Figure 66. 160 350 300 250 200 150 100 0 140 120 100 80 60 40 20 50 0 20 40 60 80 100 120 0 0 OUTPUT POWER (mW) Submit Documentation Feedback 20 40 60 80 100 120 OUTPUT POWER (mW) Figure 70. 20 20 OUTPUT POWER (mW) OUTPUT POWER (mW) Figure 71. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 Left to right Right to left 20 50 100 200 500 1k 2k Crosstalk vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4, SE CROSSTALK (dB) CROSSTALK (dB) Crosstalk vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4, OCL +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 Right to left Left to right 20 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 72. Figure 73. Crosstalk vs Frequency VDD = 5V, RL = 32, PO = 30mW Mode 4, OCL Crosstalk vs Frequency VDD = 5V, RL = 32, PO = 30mW Mode 4, SE +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 CROSSTALK (dB) CROSSTALK (dB) FREQUENCY (Hz) Left to right Right to left 20 50 100 200 500 1k 2k +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 5k 10k 20k Right to left Left to right 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 75. Supply Current vs Supply Voltage No Load, Mode 7, OCL Supply Current vs Supply Voltage No Load, Mode 7, SE 12 10 SUPPLY CURRENT (mA) 12 SUPPLY CURRENT (mA) 5k 10k 20k Figure 74. 14 10 8 6 4 8 6 4 2 2 0 5k 10k 20k 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 76. Figure 77. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL 5.5 6.0 Submit Documentation Feedback 21 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Supply Current vs Supply Voltage No Load, Mode 2, 4, 6, OCL 10 10 9 9 8 8 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) Supply Current vs Supply Voltage No Load, Mode 1, 3, 5, MONO 7 6 5 4 3 7 6 5 4 3 2 2 1 1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 2.5 6.0 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 78. Figure 79. Supply Current vs Supply Voltage No Load, Mode 2, 4, 6, Headphone SE 5.5 6.0 Output Power vs Supply Voltage RL = 8, Mode 1, 3, 5, MONO 8 2500 OUTPUT POWER (mW) SUPPLY CURRENT (mA) 7 6 5 4 3 2 2000 1500 THD+N = 10% 1000 THD+N = 1% 500 1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 2.5 3.0 SUPPLY VOLTAGE (V) 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 81. Output Power vs Supply Voltage RL = 32, Mode 2, 4, 6, OCL Output Power vs Supply Voltage RL = 32, Mode 2, 4, 6, SE 180 160 160 140 140 120 THD+N = 10% 100 80 60 THD+N = 1% 40 20 0 2.5 120 THD+N = 10% 100 80 60 THD+N = 1% 40 20 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 2.5 SUPPLY VOLTAGE (V) Submit Documentation Feedback 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 82. 22 4.0 Figure 80. OUTPUT POWER (mW) OUTPUT POWER (mW) 180 3.5 Figure 83. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Output Power vs Supply Voltage RL = 32, Mode 7, OCL 160 160 140 140 120 THD+N = 10% 100 80 60 THD+N = 1% 40 120 100 THD+N = 10% 80 60 THD+N = 1% 40 20 20 0 Output Power vs Supply Voltage RL = 32, Mode 7, SE 180 OUTPUT POWER (mW) OUTPUT POWER (mW) 180 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 2.5 3.0 SUPPLY VOLTAGE (V) 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 84. Figure 85. Efficiency vs Output Power VDD = 3.3V, RL = 8, Mode 1, 3, 5, BTL Efficiency vs Output Power VDD = 5V, RL = 8, Mode 1, 3, 5, BTL 100 1 90 80 EFFICIENCY (%) EFFICIENCY (%) 0.8 0.6 0.4 70 60 50 40 30 20 0.2 10 0 0 0 200 400 600 800 0 200 400 600 800 1000 1200 1400 1600 OUTPUT POWER (mW) OUTPUT POWER (mW) Figure 86. Figure 87. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 23 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com APPLICATION INFORMATION I2C PIN DESCRIPTION SDA: This is the serial data input pin. SCL: This is the clock input pin. ID_ENB: This is the address select input pin. I2C COMPATIBLE INTERFACE The LM4947 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4947. The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 4. The bus format diagram is broken up into six major sections: 1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. 2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. 3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4947 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4947. 4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. 5. After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received the data. 6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM4947's I2C interface is powered up through the I2CVDD pin. The LM4947's I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. Table 1. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 1 1 1 1 1 0 EC 0 ID_ADDR = 0 1 1 1 1 1 0 0 0 ID_ADDR = 1 1 1 1 1 1 0 1 0 24 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 Table 2. Control Registers D7 D6 D5 D4 D3 D2 D1 D0 Mode Control 0 0 SE/Diff (select) 0 OCL (select) MC2 MC1 MC0 Programmable 3D 0 1 L2R2 (select) L1R1 (select) N3D3 N3D2 N3D1 N3D0 Mono Volume Control 1 0 0 MVC4 MVC3 MVC2 MVC1 MVC0 Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0 Right Volume Control 1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0 Table 3. Programmable Texas Instruments 3D Audio N3D3 N3D2 Low 0 0 Medium 0 1 High 1 0 Maximum 1 1 Table 4. Input/Output Control L2R2 L1R1 SE/DIFF Select LIN1 and RIN1 Stereo Pair 0 1 0 Select LIN2 and RIN2 Stereo Pair 1 0 0 Select LIN1+LIN2 and RIN1+RIN2 Stereo Pair 1 1 0 Sets Stereo Inputs to Differential x x 1 Table 5. Output Volume Control Table Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain, dB 1 0 0 0 0 0 -59.50 2 0 0 0 0 1 -48.00 3 0 0 0 1 0 -40.50 4 0 0 0 1 1 -34.50 5 0 0 1 0 0 -30.00 6 0 0 1 0 1 -27.00 7 0 0 1 1 0 -24.00 8 0 0 1 1 1 -21.00 9 0 1 0 0 0 -18.00 10 0 1 0 0 1 -15.00 11 0 1 0 1 0 -13.50 12 0 1 0 1 1 -12.00 13 0 1 1 0 0 -10.50 14 0 1 1 0 1 -9.00 15 0 1 1 1 0 -7.50 16 0 1 1 1 1 -6.00 17 1 0 0 0 0 -4.50 18 1 0 0 0 1 -3.00 19 1 0 0 1 0 -1.50 20 1 0 0 1 1 0.00 21 1 0 1 0 0 1.50 22 1 0 1 0 1 3.00 23 1 0 1 1 0 4.50 24 1 0 1 1 1 6.00 Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 25 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com Table 5. Output Volume Control Table (continued) Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain, dB 25 1 1 0 0 0 7.50 26 1 1 0 0 1 9.00 27 1 1 0 1 0 10.50 28 1 1 0 1 1 12.00 29 1 1 1 0 0 13.50 30 1 1 1 0 1 15.00 31 1 1 1 1 0 16.50 32 1 1 1 1 1 18.00 Table 6. Output Mode Selection Output Mode Number MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output 0 0 0 0 SD SD SD 1 0 0 1 2 x GM x M MUTE MUTE 2 0 1 0 SD GM x M GM x M 3 0 1 1 GL x L + GR x R MUTE MUTE 4 1 0 0 SD GR x R GL x L 5 1 0 1 GL x L + GR x R + 2(GM x M) MUTE MUTE 6 1 1 0 SD GR x R + GM x M GL x L + GM x M 7 1 1 1 GR x R + GL x L GR x R GL x L TI 3D ENHANCEMENT The LM4947 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo headphone listening. The LM4947 can be programmed for a "narrow" or "wide" soundstage perception. The narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial, theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed: low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The difference between each level is 3dB. The external capacitors, shown in Figure 88, are required to enable the 3D effect. The value of the capacitors set the cutoff frequency of the 3D effect, as shown by Equation 1 and Equation 2. Note that the internal 20k resistor is nominal (25%). 20 k: C3DL RHP3D2 RHP3D1 LHP3D1 LM4947 LHP3D2 20 k: (internal resistors) C3DR C3DL C3DR Figure 88. External 3D Effect Capacitors f3DL(-3dB) = 1 / 2 * 20k * C3DL f3DR(-3dB) = 1 / 2 * 20k * C3DR (1) (2) Optional resistors R3DL and R3DR can also be added (Figure 89) to affect the -3dB frequency and 3D magnitude. 26 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 20 k: C3DL RHP3D2 RHP3D1 LHP3D1 LM4947 LHP3D2 20 k: (internal resistors) C3DR R3DL R3DR Figure 89. External RC Network with Optional R3DL and R3DR Resistors f3DL(-3dB) = 1 / 2 * (20k + R3DL) * C3DL f3DR(-3dB) = 1 / 2 * 20k + R3DR) * C3DR (3) (4) AV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20k (see example below). f3dB (3D) = 1 / 2 (1 + M)(20k * C3D) CEquivalent (new) = C3D / 1 + M (5) (6) Table 7. Pole Locations R3D (k) (optional) C3D (nF) M AV (dB) f-3dB (3D) (Hz) 0 68 0 0 117 1 68 0.05 -0.4 5 68 0.25 -1.9 10 68 0.50 20 68 1.00 Value of C3D to keep same pole location (nF) new Pole Location (Hz) 111 64.8 117 94 54.4 117 -3.5 78 45.3 117 -6.0 59 34.0 117 PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8 LOAD Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by an 8 load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. POWER DISSIPATION AND EFFICIENCY In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it with the difference being the power dissipated, typically, in the IC. The key here is "useful" work. For audio systems, the energy delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band power being transduced is dissipated in the Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 27 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com LM4947 and in the transducer load. The amount of power dissipation in the LM4947 is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less than 0.25. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output power. The LM4947 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a heat sink. The LM4947 also has a pair of single-ended amplifiers driving stereo headphones, RHP and LHP. The maximum internal power dissipation for RHP and LHP is given by Equation 7 and Equation 8. From Equation 7 and Equation 8, assuming a 5V power supply and a 32 load, the maximum power dissipation for LHP and RHP is 40mW, or 80mW total. PDMAX-LHP = (VDD)2 / (22 RL): Single-ended Mode PDMAX-RHP = (VDD)2 / (22 RL): Single-ended Mode (7) (8) The maximum internal power dissipation of the LM4947 occurs when all 3 amplifiers pairs are simultaneously on; and is given by Equation 9. PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LHP + PDMAX-RHP (9) The maximum power dissipation point given by Equation 9 must not exceed the power dissipation given by Equation 10: PDMAX = (TJMAX - TA) / JA (10) The LM4947's TJMAX = 150C. In the ITL package, the LM4947's JA is 65C/W. At any given ambient temperature TA, use Equation 10 to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation 10 and substituting PDMAX-TOTAL for PDMAX' results in Equation 11. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4947's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL JA (11) For a typical application with a 5V power supply and an 8 load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104C for the ITL package. TJMAX = PDMAX-TOTAL JA + TA (12) Equation 12 gives the maximum junction temperature TJMAX. If the result violates the LM4947's 150C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation 9 is greater than that of Equation 10, then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce JA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the JA is the sum of JC, CS, and SA. (JC is the junction-to-case thermal impedance, CS is the case-to-sink thermal impedance, and SA is the sink-to-ambient thermal impedance). Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation information at lower output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1F in parallel with a 0.1F filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 1.1F tantalum bypass capacitance connected between the LM4947's supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4947's power supply pin and ground as short as possible. Connecting a 2.2F capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, SELECTING EXTERNAL COMPONENTS), system cost, and size constraints. 28 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 1 and Figure 2). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri), nominal 20k, and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation 13. fc = 1 / (2RiCi) (13) As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 13 is 0.053F. The 0.22F Ci shown in Figure 1 allows the LM4947 to drive high efficiency, full range speaker whose response extends below 40Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS bump. Since CB determines how fast the LM4947 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4947's outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0F along with a small value of Ci (in the range of 0.1F to 0.39F), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated when power is first applied or the LM4947 resumes operation after shutdown. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 29 LM4947, LM4947TLEVAL SNAS349D - JUNE 2006 - REVISED MAY 2013 www.ti.com DEMO BOARD SCHEMATIC Figure 90. 30 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL LM4947, LM4947TLEVAL www.ti.com SNAS349D - JUNE 2006 - REVISED MAY 2013 REVISION HISTORY Rev Date 1.0 06/16/06 Initial release. Description 1.1 06/19/06 Changed the Class D Efficiency (n) on Typical limit (from 79 to 86) on the 5V specification table. 1.2 06/22/06 Added more Typ Perf curves. 1.3 07/18/06 Replaced some of the curves. 1.4 08/29/06 Text edits. 1.5 10/18/06 Edited DSBGA pkg drawing, Figure 1 and Figure 2. Changed IDDQ typical and limit values on the 3.3V and 5.0V specification table. Removed CMRR SE condition and changed typical values for CMRR BTL on 3.3V and 5.0V specification table. Changed Mute Attenuation typical value on 5.0V specification table. 1.6 03/02/07 Edited the 3.3V and 5V EC tables. 1.7 03/02/07 Composed (CONFIDENTIAL) D/S for customer (SAMSUNG). 1.8 09/06/07 Edited Table 4. 1.9 11/09/07 Text edits. D 05/03/13 Changed layout of National Data Sheet to TI format. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links: LM4947 LM4947TLEVAL Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) LM4947TL/NOPB ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YZR 25 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 85 GH1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM4947TL/NOPB Package Package Pins Type Drawing SPQ DSBGA 250 YZR 25 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 8.4 Pack Materials-Page 1 2.69 B0 (mm) K0 (mm) P1 (mm) 2.69 0.76 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4947TL/NOPB DSBGA YZR 25 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0025xxx 0.6000.075 D E TLA25XXX (Rev D) D: Max = 2.532 mm, Min =2.472 mm E: Max = 2.532 mm, Min =2.472 mm 4215055/A NOTES: A. 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