© Copyright 2000 Advanced Micro Devices, Inc. All rights reserved Publication# 22024 Rev: BAmendment/0
Issue Date: May 200 0
Am186™CH
High-Performance, 80C186-Compatible
16-Bit Embedded HDLC Microcontroller
DISTINCTIVE CHARACTERISTICS
■E86™ family of x86 embedded processors
offers improved time-to-market
– Software migration (backwards- and upwards-
compatible)
– World-class development tools, applications, and
system software
■Serial Communications Peripherals
– Two H igh -l evel Da ta Li nk C on trol ( HDLC ) ch annels
– Two independent Time Slot Assigners (TSAs)
– Physical interface for HDLC channels can be raw
DCE or PCM Highway
– High-Speed UART with autobaud
–UART
– Synchronous serial interface (SSI)
– SmartDMA™ channels (4) to support HDLC
■System Peripherals
– Three programmable 16-bit timers
– Hardware watchdog timer
– General-purpose DMA (4 channels)
– Programmable I/O (48 PIO signals)
– Interrupt Controller (36 maskable interrupts)
■Memory and Peripheral Interface
– Integr at ed DRAM contr oller
– Glueless interface to RAM/ROM/Flash memory
(55-ns Flash memory required for zero-wait-state
operation at 50 MHz)
– Fourteen chip selects (8 peripherals, 6 memory)
– External bus mastering support
– Multiple xed and nonm ultiplex ed address/ data b us
– Programmable bus sizing
– 8-bit boot option
■Available in the following package:
– 160-pin plastic quad flat pack (PQFP)
– 25-, 40-, and 50-MHz operating frequencies
– Low-voltage operation, VCC = 3.3 V ± 0.3 V
– Commercial and industrial temperature rating
– 5-V-tolerant I/O (3.3-V output levels)
GENERAL DESCRIPTION
The Am186™CH HDLC microcontroller is a member of
AMD’s Comm86™ family of communications-specific
microcontrollers. The microcontroller is a derivative of
the Am186CC communications controller and is pin-
compatible with that device.
The Am186CH HDLC microcontroller is a cost-
effective, high-performance microcontroller solution for
communications applications. This highly integrated
microcontroller enables customers to save system
costs and increase performance over 8-bit
microcontrollers and other 16-bit microcontrollers.
The microcontroller offers the advantages of the x86
development environment’s widely available native
develo pment tools, appl ications, and system software.
Additionally, the microcontroller uses the industry-
standard 186 instruction set that is part of the AMD
E86™ family, which continually offers instruction-set-
compatible upgrades. Built into the Am186CH HDLC
microcontroller is a wide range of communications
features required in many communications
applications, including High-level Data Link Control
(HDLC).
Comprehensive development support is available from
AMD and its FusionE86SM partners. A customer
develo pment platfor m board is available. AMD and its
FusionE86 partners also offer boards, schematics,
driv ers, protocol stacks, and routing software to enable
fast time to market.
2Am186™CH HDLC Microcontroller Data Sheet
ORDERING INFORMATION
–25 = 25 MHz
–40 = 40 MHz
–50 = 50 MHz
TEMPERATURE RANGE
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
LEAD FORMING
\W=Trimmed and Formed
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PACKAGE TYPE
K=160-Pin Plastic Quad Flat Pack (PQFP)
Am186CH high-performance 80C186-compatible
16-bit embedded HDLC microcontroller
–50 K C \W
Valid Combinations
Am186CH–25
Am186CH–40
Am186CH–50 KC\W
Am186CH–25
Am186CH–40 KI\W
Am186CH
C = Am186CH Commercial (TC=0C to +100C)
I = Am186CH Industrial (TA=–40C to +85C)
where: TC= case temperature
where: TA= ambient tempera ture
Am186™CH HDLC Microcontroller Data Sheet 3
TA BLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Ordering Information .................................................................................................................... 2
Table of Contents ........ ....... .................... .................... ........ ....... ....... ........ ....... ............................ 3
List of Figures .............................................................................................................................. 4
List of Tables ............................................................................................................................... 5
Logic Diagram By Interface ......................................................................................................... 6
Logic Diagram By Defaul t Pin Function ...... ......... ......... ......... .. ......... ......... .. ......... ......... .. ......... ... 7
Pin Connection Diagram—160-Pi n PQFP Package ................ .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .... 8
Pin and Signal Tables .................................................................................................................. 9
Signal Descriptions ............................................................................................................... 12
Architectural Overview ............................................................................................................... 24
Detailed Description .............................................................................................................. 24
Am186™ Embedded CPU .................................................................................................... 25
Memor y Or ga n i za t i on .. ............. .. .. .............. .. .. ....... .. .. ............. .. ... ............. .. .. .............. .. .. .......25
I/O Space .............................................................................................................................. 25
Serial Communications Support ...... .................. ......... .. ......... ......... .. ......... ......... .. ......... .. ...... 26
Two HDLC Channels and Two TSAs.......... .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. . 26
Four SmartDMA™ Channels.......... .. ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ......... 26
Two Asynchronous Serial Ports......... ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ....... 26
Synchronous Serial Port................................................................................................... 27
System Peripher als .... ............................ ......... .. ......... ......... .. ......... ......... .. ......... .. ......... ........ 27
Interrupt Controller ........................................................................................................... 27
Four General-Pur pose DMA Channels ....... ....... ......... ............................ .. ......... ......... .. ... 27
48 Programmable I/O Signals........ .................. ............................ ......... .. ......... ......... .. ..... 27
Three Programmable Timers ........................................................................................... 27
Hardware Watchdog Timer .............................................................................................. 28
Memory and Peripheral Interface .......................................................................................... 28
System Interfaces............................................................................................................. 28
DRAM Support................................................................................................................. 30
Chip Selects..................................................................................................................... 30
Clock Control ................................................................................................................. ........ 31
In-Circ uit Emulator Support .................... .. ......... ......... .. ......... ......... .. ......... .................. ......... . 31
Applications ............................................................................................................................... 31
Clock Generati on and Control ....... ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ......... ............33
Features ................................................................................................................................ 33
System Clock ........................................................................................................................ 33
Crystal-Driven Clock Source ................................................................................................. 34
External Clock Source ........................................................................................................... 35
Static Operation .................................................................................................................... 35
PLL Bypass Mode ................. .. .. .. .. .. .............. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .... 35
UART Baud Clock .......... .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............. 35
Power Supply Operation ............................................................................................................ 36
Power Supply Connections ................................................................................................... 36
Input/Out put Circuitry .................. .. ......... ......... .. ......... ......... .. ......... ......... .. ......... ................... 36
PIO Supply Current Limit ................. .. ......... .. ......... ......... .. ......... ............................ ......... .. .... 36
Absolute Maximum Ratings .......................................................................................................37
Operating Ranges .......... ....... ....... ........ ....... .................... ....... ........ ....... .................... ....... .......... 37
DC Characteristics over Commercial and Industrial Operating Ranges .................................... 37
Maximum Load Derating ............................................................................................................ 38
Capacitance ............................................................................................................................... 38
Power Supply Current ................................................................................................................ 38
4Am186™CH HDLC Microcontroller Data Sheet
Thermal Charact eristics—PQFP Package ...... ............................ .. ......... ......... .. ......... ......... .. .... 39
Commercial and Industrial Switching Characteristics and Waveforms ...................................... 40
Switching Characteristics over Commercial and Industrial Operating Ranges ....................... ...............47
Appendix A—Pin Tables............................................................................................................A-1
CPU PLL Modes.............................................................................................................. A-7
Pin List Table Column Definitions ......................................................................................A-10
Appendix B—Physical Dimensions: PQR160, Plastic Quad Flat Pack (PQFP) .. ......................B-1
Appendix C—Customer Support ............................................................................................... C -1
Related AMD Products—E86™ Family Devices ..................................................................C -1
Related Documents ..............................................................................................................C-2
Am18 6 CC /CH/CU Mic r o co ntrolle r C u st o m er D e v el o p m en t P la tf o rm .... .. ............. .. ... ..........C -2
Third-Party Development Support Products .......... .. ..... ... ... ..... ... ..... .. ... ..... ... ..... ... ... ..... .. ...... .. ... ...C-2
Customer Service .................................................................................................................C-2
Hotline and World Wide Web Support. ............................................................................ C-2
Corporate Applications Hotline........................................................................................ C-2
World Wide Web Home Page ......................................................................................... C-3
Documentation and Literature... .................. ......... .. ......... ......... .. ......... ......... .. ......... ........ C-3
Literature Ordering.......................................................................................................... C-3
Index................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1. Am186CH Microcontroller Block Diagram ............................................................. 24
Figure 2. Two-Component Address Example ...................................................................... 25
Figure 3. Am186CH Microcontroller Address Bus — Default Operation .................... .. ........ 29
Figure 4. Am186CH Microcontroller—Address Bus Disable In Effect .................................. 29
Figure 5. 32-Channel Linecard Syst em Appli cation ........................ .. ......... ......... .. ......... ...... 32
Figure 6. System Clock Generation ..................................................................................... 33
Figure 7. Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies . 34
Figure 8. External Interface to Support Clocks—Fundamental Mode Crystal ...................... 34
Figure 9. External Interface to Support Clocks—External Clock Source ............................. 35
Figure 10. UART and High-Speed UART Clocks ............... .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 35
Figure 11. Typical Icc Versus Frequenc y ................................ ......... .. ......... ......... .. ......... ........ 38
Figure 12. Thermal Resistance(C/Watt) ............................................................................... 39
Figure 13. Thermal Characteristics Equations ....................................................................... 39
Figure 14. Key to Switching Waveforms ................................................................................ 40
Figure 15. Read Cycle Wavefor ms .................... ......... .. ......... .. ......... ......... .. ......... ......... .. ...... 49
Figure 16. Write Cycle Waveforms ......................................................................................... 52
Figure 17. Software Halt Cycle Waveforms ........................................................................... 53
Figure 18. Peripheral Timing Waveforms ............................................................................... 54
Figure 19. Reset Waveforms .................................................................................................. 55
Figure 20. Signals Related to Reset (System PLL in 1x or 2x Mode) ................. .. ......... ........ 56
Figure 21. Signals Related to Reset (System PLL in 4x Mode) ................. .. ......... ......... .. ...... 56
Figure 2 2 . Synch r o n ous R e ad y Wa v e fo rms ................. .. ... ............. .. .. .............. .. .. ....... .. .. ....... 57
Figure 23. Asynchronous Ready Waveforms ................ .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 58
Figure 24. Entering Bus Hold Waveforms .............................................................................. 59
Figure 25. Exiting Bus Hold Waveforms ................................................................................. 60
Figure 26. System Clocks Waveforms—Active Mode (PLL 1x Mode) ................ .. .. .. ............ . 62
Figure 27. PCM Highway Waveforms (Timing Slave) ............................................................ 63
Figure 28. PCM Highway Waveforms (Timing Master) .......................................................... 64
Figure 29. DCE Transmit Waveforms .................................................................................... 65
Figure 30. DCE Receive Waveforms ..................................................................................... 65
Figure 3 1 . SSI Wav e forms ........ .. .. ....... .. .. .............. .. .. ............. .. ... ............. .. .. ....... .. .. .............. 6 6
Figure 32. DRAM Read Cycle without Wait States Waveform ............................ .. .. .. ............ . 68
Am186™CH HDLC Microcontroller Data Sheet 5
Figure 33. DRAM Read Cycle with Wait States Waveform ...... ......... ......... .. ......... ......... .. ...... 68
Figure 34. DRAM Write Cycle without Wait States Waveform ............................................... 69
Figure 35. DRAM Write Cycle with Wait States Waveform ......... .. .. .. .. .. .............. .. .. .. ............ . 69
Figure 36. DRAM Refresh Cycle Waveform ........................................................................... 70
LIST OF TABLES
Table 1. PQFP Pin Assignments—Sorted by Pin Number .................................................. 10
Table 2. PQFP Pin Assignments—Sorted by Signal Name ........... .. .. ............ .. .. .. .. ............ . 11
Table 3. Signal Descriptions Table Definitions..................................................................... 12
Table 4. Signal Descriptions ..................... .. ......... ......... .. ......... ............................ .. ......... .... 13
Table 5. Segment Register Sele ction Rules ..... ......... .. ......... ......... .. ......... .................. ........ 26
Table 6. Cryst al Parameters ........ ....... ....... ........ ....... .. ....... ....... ........ .. ....... ....... ....... ........ .... 34
Table 7. Typica l Power Consumption Calculati on....................... .. ......... .................. ............ 38
Table 8. Thermal Characteristics (°C/Watt) ........................................................................ 39
Table 9. Alphabetical Key to Switching Parameter Symbols .............. .. .. .. .. ............ .. .. .. .. .. .. 41
Table 10. Numerical Key to Swit ching Parameter Symbols ........... .. ......... ......... .. ......... ........ 44
Table 11. Read Cycle Timing ........... ......... ............................ ......... .. ......... ......... .. ......... .. ...... 47
Table 12. Write Cycle Timing ........ ................ .. ......... ......... .. ......... ......... .. ......... ......... .. ......... . 50
Table 13. Software Halt Cycle Timing ................................................................................... 53
Table 14. Peripheral Timi ng ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 54
Table 15. Reset Timing ............... .................. ......... .. ......... ......... .. ......... ......... .. ......... ............ 55
Table 16. External Ready Cycle Timi ng ................... .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 57
Table 17. Bus Hold Timing ........ .. .. .. .............. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 59
Table 18. System Clocks Timing ............ .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 61
Table 19. PCM Highway Timing (Timing Slave) ........... ............ .. .. .. .. .. ............ .. .. .. .. ............ . 62
Table 20. PCM Highway Timing (Timing Master) .......... ......... .. ......... ......... .. ......... ......... .. .... 64
Table 21. DCE Interface Timing ........ .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 65
Table 22. SSI Timing .......... .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............. 66
Table 23. DRAM Timing ................ .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 67
Table 24. Power-On Reset (POR) Pin Defaults ...................................................................A-2
Table 25. Multiplexed Signal Trade-Of fs ......... .. ......... ......... .. ......... ......... .. ......... .. ......... .......A-5
Table 26. Reset Configuration Pins (Pinstraps) ........... ......... ......... .. ......... ......... .. ......... .......A-7
Table 27. PIOs Sorted by PIO Number ...................... ......... .. ......... ......... .. ......... ..................A-8
Table 28. PIOs Sorted by Signal Name ............... .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............A-9
Table 29. Pin List Table Definitions....................... .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ..........A-10
Table 30. Pin List Summary ................. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ..........A-11
6Am186™CH HDLC Microcontroller Data Sheet
LOGIC DIAGRAM BY INTERFACE1
CLKOUT INT8–INT0 Interrupts
Reset/ RES NMI
Clocks RESOUT
X1 LCS Chip
Selects
X2 MCS3–MCS0
PCS7–PCS0
Address and
Address/Data
Buses
A19–A0 UCS
AD15–AD0
CAS0
DRAM Control
Bus Status and
Control
ALE CAS1
ARDY RAS0
BHE RAS1
BSIZE8 Am186CH HDLC
DEN Microcontroller DCE_RXD_A, B
DCE Interface
(HDLC A–B)1
Notes:
1. Because of multiplexing, not all interfaces are available at once. Refer to Table 25, “Multiplexed Signal T rade-Offs,” on page A-5.
DS DCE_TXD_A, B
DRQ1–DRQ0 DCE_RCLK_A, B
DT/R DCE_TCLK_A, B
HLDA DCE_CTS_A, B
HOLD DCE_RTR_A, B
RD
S2–S0 PCM_RXD_A, B
PCM Interface
(HDLC A–B)1
S6 PCM_TXD_A, B
SRDY PCM_CLK_A, B
WHB PCM_FSC_A, B
WLB PCM_TSC_A, B
WR SDEN Synchronous
Serial InterfaceProgrammable
Timers
PWD SCLK
TMRIN1–TMRIN0 SDATA
TMROUT1–TMROUT0 RXD_U Asynchronous
Serial Interface
(UART)
Debug QS1–QS0 TXD_U
CTS_U
Progr amma ble I/O
(PIO) PIO47–PIO0 RTR_U
RXD_HU High-Speed
UARTConfiguration
Pinstraps
{ADEN} TXD_HU
{CLKSEL1} CTS_HU
{CLKSEL2} RTR_HU
{ONCE}
{UCSX8} UCLK UART Clock
9/
4/
8/
20
16
2/
2/
2/2/
2/
2/
2/
3/2/
2/
2/
2/
2/
2/
2/
2/
48/
Am186™CH HDLC Microcontroller Data Sheet 7
LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1
Notes:
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pins trap pins.
CLKOUT
Reset/ RES
Clocks RESOUT DCE_RXD_A [PCM_RXD_A] HDLC A
(DCE)
X1 DCE_TXD_A [PCM_TXD_A]
X2 DCE_RCLK_A [PCM_CLK_A]
DCE_TCLK_A [PCM_FSC_A]
Address and
Address/Data Buses A19–A0
AD15–AD0 PIO0 [TMRIN1] Programmab le
I/O (PIO)
PIO1 [TMROUT1]
Bus Status and
Control
ALE [PIO33] PIO2 [PCS5]
ARDY [PIO8] PIO3 [PCS4 ] {CLKSEL2}
BHE [PIO34] {ADEN}PIO4 [MCS0] {UCSX8}
BSIZE8 PIO5 [MCS3] [RAS1]
DEN [DS] [PIO3 0 ] PIO6 [INT8] [PWD]
DRQ1 PIO7 [INT7]
DT/R [PIO29 ] PIO8 [ARDY]
HLDA {CLKSEL1} PIO9 [DRQ0]
HOLD PIO10 [SDEN]
RD Am186CH HDLC PIO11 [SCLK]
S0 Microcontroller PIO12 [SDATA]
S1 PIO16 [RXD_HU]
S2 PIO17 [DCE_CTS_A] [PCM_TSC_A]
S6 PIO18 [DCE_RT R_A]
SRDY [PIO35] PIO19 [INT6]
WHB PIO20 [TXD_U]
WLB PIO21 [UCLK]
WR [PIO15] PIO22
PIO23
Debug QS1–QS0 PIO24 [CTS_U]
PIO25 [RTR_U]
High-Speed UART TXD_HU PIO26 [RXD_U]
PIO27 [TMRIN0]
Chip
Selects
LCS [RAS0]PIO28 [TMROUT0]
MCS1 [CAS1]PIO31[PCS7]
MCS2 [CAS0]PIO32[PCS6]
PCS0 [PIO13] PIO36 [DCE_RXD_B] [PCM_RXD_B]
PCS1 [PIO14] PIO37 [DCE_TXD_B] [PCM_TXD_B]
PCS2 PIO38 [DCE_CTS_B] [PCM_TSC_B]
PCS3 PIO39 [DCE_RTR_B]
UCS {ONCE}PIO40 [DCE_RCLK_B] [PCM_CLK_B]
PIO41 [DCE_TCLK_B] [PCM_FSC_B]
Interrupts INT5–INT0 PIO42
NMI PIO43
PIO44
Reserved
—RSVD_104 PIO45
—RSVD_103 PIO46 [CTS_H U]
—RSVD_102 PIO47 [RTR_HU ]
—RSVD_101
—RSVD_81
—RSVD_80
—RSVD_76
—RSVD_75
20
16
6/
8Am186™CH HDLC Microcontroller Data Sheet
PIN CONNECTION DIAGRAM—1 60-PIN PQFP PACKAGE
VCC
TXD_U
RXD_U
CTS_U
RTR_U
VSS
PIO43
PIO42
PIO44
PIO45
PIO22
PIO23
VCC
INT8/PWD
INT7
INT6
TMRIN1
TMROUT1
TMRIN0
TMROUT0
VSS
DCE_TXD_B/PCM_TXD_B
DCE_RXD_B/PCM_RXD_B
DCE_CTS_B/PCM_TSC_B
DCE_RTR_B
DCE_RCLK_B/PCM_CLK_B
DCE_TCLKB/PCM_FSC_B
VCC
UCS {ONCE}
LCS/RAS0
VSS
MCS3/RAS1
MCS2/CAS0
MCS1/CAS1
MCS0 {UCSX8}
VCC
DRQ0
DCE_CTS_A/PCM_TSC_A
DCE_RTR_A
VSS
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
1V
SS VCC 120
2 SDEN DCE_TXD_A/PCM_TXD_A 119
3 SCLK DCE_RXD_A/PCM_RXD_A 118
4 SDATA DCE_RCLK_A/PCM_CLK_A 117
5PCS0
DCE_TCLK_A/PCM_FSC_A 116
6PCS1
NMI 115
7PCS2 RES 114
8PCS3 INT5 113
9PCS4
{CLKSEL2} INT4 112
10 PCS5 INT3 111
11 PCS6 INT2 110
12 VCC INT1 109
13 PCS7 VSS 108
14 ARDY Am186CH HDLC INT0 107
15 SRDY Microcontroller VCC 106
16 WR DRQ1 105
17 DT/R RSVD_104 104
18 DEN/DS RSVD_103 103
19 ALE RSVD_102 102
20 BHE {ADEN}RSVD_101 101
21 VSS VSS 100
22 UCLK HOLD 99
23 RTR_HU HLDA {CLKSEL1} 98
24 CTS_HU RD 97
25 RXD_HU WLB 96
26 TXD_HU WHB 95
27 VCC BSIZE8 94
28 AD0 AD15 93
29 AD8 AD7 92
30 A0 VCC 91
31 A1 A19 90
32 A2 A18 89
33 VSS A17 88
34 AD1 AD14 87
35 AD9 AD6 86
36 A3 A16 85
37 A4 A15 84
38 AD2 VSS 83
39 AD10 VSS 82
40 VCC RSVD_81 81
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
A5
A6
A7
A8
AD3
AD11
VCC
A9
A10
AD4
AD12
VSS
S6
S2
S1
S0
RESOUT
VCC
CLKOUT
VSS
QS0
QS1
A11
A12
AD5
AD13
VCC
A13
A14
VSS
VSS_A
X1
X2
RSVD_75
RSVD_76
VCC_A
VCC
VCC
RSVD_80
Am186™CH HDLC Microcontroller Data Sheet 9
PIN AND SIGNAL TABLES
Table 1 on page 10 and Table 2 on page 11 show the
pins sorted by pin number and signal name,
respectively.
Table 4 on page 13 contains the signal descriptions
(grouped alphabetically within function). The table
include s columns listing the multiplexed functions and
I/O type. Table 3 on page 12 defines terms used in
Table 4.
Refer to A ppe ndi x A, “P in Tables,” on pag e A -1 for a n
additional group of tables with the following
information:
■Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 24 on
page A-2.
■Multiplexed signal trade-offs—Table 25 on
page A-5.
■Pinstraps and pinstrap options—Table 26 on
page A-7.
■Programmable I/O pins ordered by PIO pin number
and multiplexed signal name, respectively, includ-
ing pin numbers, multiplexed functions, and pin con-
figurations following system reset—Table 27 on
page A-8 and Table 28 on page A-9.
■Pin and si gnal summar y sh owing signa l name and
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage—Table 30
on page A-11.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
10 Am186™CH HDLC Microcontroller Data Sheet
Table 1. PQFP Pin Assignments—Sorted by Pin Number1
Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No. Name—Right Side Pin No. Name—Top Side
1V
SS 41 VSS 81 RSVD_81 121 VSS
2SDEN/PIO10 42A5 82V
SS 122 DCE_RTR_A/PIO18
3 SCLK/PIO11 43 A6 83 VSS 123 DCE_CTS_A/
PCM_TSC_A/PIO17
4 SDATA/PIO12 44 A7 84 A15 124 DRQ0/PIO9
5PC
S0/PIO13 45 A8 85 A16 125 VCC
6PCS1/PIO14 46 AD3 86 AD6 126 MCS0/PIO4{UCSX8}
7PCS2 47 AD11 87 AD14 127 MCS1/CAS1
8PCS3 48 VCC 88 A17 128 MCS2/CAS0
9PCS4/PIO3{CLKSEL2} 49 A9 89 A18 129 MCS3/RAS1/PIO5
10 PCS5/PIO2 50 A10 90 A19 130 VSS
11 PCS6/PIO32 51 AD4 91 VCC 131 LCS/RAS0
12 VCC 52 AD12 92 AD7 132 UCS{ONCE}
13 PCS7/PIO31 53 VSS 93 AD15 133 VCC
14 ARDY/PIO8 54 S6 94 BSIZE8 134 DCE_TCLK_B/
PCM_FSC_B/PIO41
15 SRDY/PIO35 55 S2 95 WHB 135 DCE_RCLK_B/
PCM_CLK_B/PIO40
16 WR/PIO15 56 S1 96 WLB 136 DCE_RTR_B/PIO39
17 DT/R/PIO29 57 S0 97 RD 137 DCE_CTS_B/
PCM_TSC_B/PIO38
18 DEN/DS/PIO30 58 RESOUT 98 HLDA{CLKSEL1} 138 DCE_RXD_B/
PCM_RXD_B/PIO36
19 ALE/PIO33 59 VCC 99 HOLD 139 DCE_TXD_B/
PCM_TXD_B/PIO37
20 BHE/PIO34{ADEN} 60 CLKOUT 100 VSS 140 VSS
21 VSS 61 VSS 101 RSVD_101 141 TMROUT0/PIO28
22 UCLK/PIO21 62 QS0 102 RSVD_102 142 TMRIN0/PIO27
23 RTR_HU/PIO47 63 QS1 103 RSVD_103 143 TMROUT1/PIO1
24 CTS_HU/PIO46 64 A11 104 RSVD_104 144 TMRIN1/PIO0
25 RXD_HU/PIO16 65 A12 105 DRQ1 145 INT6/PIO19
26 TXD_HU 66 AD5 106 VCC 146 INT7/PIO7
27 VCC 67 AD13 107 INT0 147 INT8/PWD/PIO6
28 AD0 68 VCC 108 VSS 148 VCC
29 AD8 69 A13 109 INT1 149 PIO23
30 A0 70 A14 110 INT2 150 PIO22
31 A1 71 VSS 111 INT3 151 PIO45
32 A2 72 VSS_A 112 INT4 152 PIO44
33 VSS 73 X1 113 INT5 153 PIO42
34 AD1 74 X2 114 RES 154 PIO43
35 AD9 75 RSVD_75 115 NMI 155 VSS
36 A3 76 RSVD_76 116 DCE_TCLK_A/
PCM_FSC_A 156 RTR_U/PIO25
37 A4 77 VCC_A 117 DCE_RCLK_A/
PCM_CLK_A 157 CTS_U/PIO24
38 AD2 78 VCC 118 DCE_RXD_A/
PCM_RXD_A 158 RXD_U/PIO26
39 AD10 79 VCC 119 DCE_TXD_A/
PCM_TXD_A 159 TXD_U/PIO20
40 VCC 80 RSVD_80 120 VCC 160 VCC
Notes:
1. SeeTable 27, “PIOs Sorted by PIO Number,” on page A-8 for PIOs sorted by PIO number.
Am186™CH HDLC Microcontroller Data Sheet 11
Table 2. PQFP Pin Assignments—Sorted by Signal Name1
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
A0 30 CLKOUT 60 PCS4/PIO3{CLKSEL2} 9 TXD_U/PIO20 159
A1 31 CTS_HU/PIO46 24 PCS5/PIO2 10 UCLK/PIO21 22
A10 50 CTS_U/PIO24 157 PCS6/PIO32 11 UCS {ONCE} 132
A11 64 DCE_CTS_A/
PCM_TSC_A/PIO17 123 PCS7/PIO31 13 VCC 12
A12 65 DCE_CTS_B/
PCM_TSC_B/PIO38 137 PIO22 150 VCC 27
A13 69 DCE_RCLK_A/
PCM_CLK_A 117 PIO23 149 VCC 40
A14 70 DCE_RCLK_B/
PCM_CLK_B/PIO40 135 PIO42 153 VCC 48
A15 84 DCE_RTR_A/PIO18 122 PIO43 154 VCC 59
A16 85 DCE_RTR_B/PIO39 136 PIO44 152 VCC 68
A17 88 DCE_RXD_A/PCM_RXD_A 118 PIO45 151 VCC 78
A18 89 DCE_RXD_B/
PCM_RXD_B/PIO36 138 QS0 62 VCC 91
A19 90 DCE_TCLK_A/
PCM_FSC_A 116 QS1 63 VCC 106
A2 32 DCE_TCLK_B/
PCM_FSC_B/PIO41 134 RD 97 VCC 120
A3 36 DCE_TXD_A/PCM_TXD_A 119 RES 114 VCC 125
A4 37 DCE_TXD_B/
PCM_TXD_B/PIO37 139 RESOUT 58 VCC 133
A5 42 DEN/DS/PIO30 18 RSVD_75 75 VCC 148
A6 43 DRQ0/PIO9 124 RSVD_76 76 VCC 160
A7 44 DRQ1 105 RSVD_80 80 VCC 79
A8 45 DT/R/PIO29 17 RSVD_81 81 VCC_A 77
A9 49 HLDA{CLKSEL1} 98 RSVD_101 101 VSS 1
AD0 28 HOLD 99 RSVD_102 102 VSS 21
AD1 34 INT0 107 RSVD_103 103 VSS 33
AD2 38 INT1 109 RSVD_104 104 VSS 41
AD3 46 INT2 110 RTR_HU/PIO47 23 VSS 53
AD4 51 INT3 111 RTR_U/PIO25 156 VSS 61
AD5 66 INT4 112 RXD_HU/PIO16 25 VSS 71
AD6 86 INT5 113 RXD_U/PIO26 158 VSS 83
AD7 92 INT6/PIO19 145 S0 57 VSS 100
AD8 29 INT7/PIO7 146 S1 56 VSS 108
AD9 35 INT8/PWD/PIO6 147 S2 55 VSS 121
AD10 39 LCS/RAS0 131 S6 54 VSS 130
AD11 47 MCS0/PIO4{UCSX8} 126 SCLK/PIO11 3 VSS 140
AD12 52 MCS1/CAS1 127 SDATA/PIO12 4 VSS 155
AD13 67 MCS2/CAS0 128 SDEN/PIO10 2 VSS 82
AD14 87 MCS3/RAS1/PIO5 129 SRDY/PIO35 15 VSS_A 72
AD15 93 NMI 115 TMRIN0/PIO27 142 WHB 95
ALE/PIO33 19 PCS0/PIO13 5 TMRIN1/PIO0 144 WLB 96
ARDY/PIO8 14 PCS1/PIO14 6 TMROUT0/PIO28 141 WR/PIO15 16
BHE/PIO34{ADEN}20PCS2 7 TMROUT1/PIO1 143 X1 73
BSIZE8 94 PCS3 8 TXD_HU 26 X2 74
Notes:
1. See Table 27, “PIOs Sorted by PIO Number,” on page A-8 for PIOs sorted by signal name.
12 Am186™CH HDLC Microcontroller Data Sheet
Signal Descriptions
Table 4 on page 13 contains a description of the
Am186CH HDLC microcontroller signals. Table 3
describes the terms used in Table 4. The signals are
organized a lp hab etic ally wi thi n t he f oll owing f unc tio nal
groups:
■Bus interface/general-purpose
DMA request (page 13)
■Clocks/reset/watchdog timer (page 17)
■Reserved (page 18)
■Power and ground (page 18)
■Debug support (page 18)
■Chip selects (page 19)
■DRAM (page 19)
■Interrupts (page 20)
■Programmable I/O (PIOs) (page 21)
■Programmable timers (page 21)
■Asynchr onous ser ial p or ts (UA RT and High-Spee d
UART) (page 21)
■Synchronous serial interface (SSI) (page 22)
■HDLC synchronous communication interfaces:
channels A and B for Data Communications
Equipment (DCE) and Pulse-Code Modulation
(PCM) interfaces (page 22)
For pinstraps refer to Table 26, “Reset Configuration
Pins (Pinstraps),” on page A-7.
Table 3. Signal Descriptions Table Definitions
Term Definition
General terms
[ ] Indicates the pin alternate function; a pin
defaults to the signal named without the
brackets.
{ } Indicates the reset configuration pin (pinstrap).
pin Refers to the physical wire.
reset An
external or power-on reset
is ca used by
asserting RES. An
internal res et
is in itiated by
the watchdog timer. A
system reset
is one that
resets the Am186CH HDLC microcontroller (the
CPU plus the internal peripherals) as well as
any external peripherals connected to
RESOUT. An external reset always causes a
system reset; an internal reset can optionally
cause a system reset.
signal Refers to the electrical signal that flows across
a pin.
SIGNAL A line over a signal name indicates that the
signal is active Low; a signal name without a
line is active High.
Signal types
B Bidirectional
HHigh
LS Programmable to hold last sta te of pin
O Totem pole output
OD Open drain output
OD-O Open drain output or totem pole output
PD Internal pulldown resistor
PU Internal pullup resistor
STI Schmitt trigger input
STI-OD Schmitt trigger input or open drain output
TS Three-state output
Am186™CH HDLC Microcontroller Data Sheet 13
Table 4. Signal Descriptions
Signal Name Multiplexed
Signal(s) Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0 — O Address B us s up pli es no nm ultiplex ed mem ory or I/ O a ddr ess es to the sy ste m
one half of a CLK O UT peri od ea rlier th an the multiplexed addre ss an d data bus
(AD15–AD0). During bus-hold or reset conditions, the address bus is three-
stated with pul ldowns.
When the lo wer or upper chip-select regions are configured for DRAM mode, the
A19–A0 bus provides the row and column addresses at the appropriate times.
The upper and lo w e r me mo ry chip-se lec t ranges can be ind ivi dually c onf igu r ed
for DRAM mode.
AD15–AD0 — B Address and Data Bus tim e-m ultipl e x ed pins suppl y mem ory or I/O add resses
and data to the system. This bus can supply an address to the system during the
first period of a bus cycle (t1). It transmits (write cycle) or receives (read cycle)
data t o or from the syst em during the r ema ining p eriods o f t hat c yc le (t2, t3, and
t4). The address phase of these pins can be disabled—see the {ADEN} pin
description in Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.
During a reset condition, the address and data bus is three-stated with
pulldowns, and during a bus hold it is three-stated.
In addition, during a re set the state of the address and data bus pins (AD15–
AD0) is latched into the Reset Configuration (RESCON) register. This feature
can be used to provide software with information about the external system at
reset time.
ALE [PIO33] O Address Latch En able indic ates to the s ystem that a n addre ss ap pears on the
address and data bus (AD15–AD0). The address is guaranteed valid on the
falling edge of ALE.
ALE is thr ee-stated and has a pulldown resistor during bus-hold or reset
conditions.
ARDY [PIO8] STI Asynchronous Ready is a true asynchronous ready that indicates to the
microcontroller that the addressed memory space or I/O device will complete a
data tr ansfer. The ARDY pin is as ynchr ono us to CLKOUT and is ac tiv e H igh. To
guarantee the number of wait states inserted, ARDY or SRDY must be
synchronized to CLKOUT. If the falling edge of ARDY is not synchronized to
CLKOUT as specified, an additional clock period can be added.
To alwa ys asse rt the ready con dition to the m icrocontroll er , tie ARDY and SRDY
High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
14 Am186™CH HDLC Microcontroller Data Sheet
BHE [PIO34]
{ADEN}OBus High Enable: During a memory access, BHE and the least-significant
address bit (AD0) indicate to the system which bytes of the data bus (upper,
lower, or both) participate in a bus cycle. The BHE and AD0 p ins are enco ded as
follows:
BHE is asserted during t1 and remains asserted through t3 and tW. BHE does not
require latchi ng. BH E is three-stated with a pullup during bus-hold and reset
conditions.
WLB and WHB implement the functionality of BHE and AD0 for high and low byte
write enables, and th ey have timing app ropriate fo r us e with th e nonm ul tipl exed
bus in terface.
BHE also signal s DRAM refresh cycle s when using the m ultiple xe d address and
data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High.
During refres h cy cles , t he AD bus is driv e n during the t 1 pha se an d three -state d
during the t2, t3, and t4 phases. The v alue driv en on the A b us is unde fined during
a refresh cycle. For this reason, th e A0 signal cannot be used in place of the AD0
signal to determine refresh cycles.
BSIZE8 —OBus Size 8 is asserted during t1–t4 to indic ate an 8- bit cycle , or is deasserted to
indicate a 16-bit cycle.
DEN [DS]
[PIO30] OData Enable supplies an output enable to an external data-bus transceiv er. DEN
is asserted during memory and I/O cycles. DEN is deasserted when DT/R
change s state. D EN is three-stated with a pullup during bus-hold or reset
conditions.
[DRQ0]
DRQ1
PIO9
—
STI
STI
DMA Requests 0 and 1 indic ate to the micro controller that an e xternal de vice is
ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are level-
triggered an d i nternally sy nc hro nized. DRQ1–[ DRQ0] are no t la tch ed and m u st
remain act ive until serviced.
[DS]DEN
[PIO30] OData Strobe provides a signal where the write cycle timing is identical to the read
cycle timing. When used with other control signals, [DS] provides an interface for
68K-type peripherals without the need for additional system interface logic.
When [DS] is asserted, addresses are valid. When [DS] is asser ted on writes,
data is v alid. W hen [D S] is asserted on rea ds, dat a can be driv en on the AD bu s.
Following a reset, this pin is configured as DEN. The pin is then configured by
software to operate as [DS].
DT/R [PIO29] O Data T ransmit or Receive indicates which direction data should flow through an
external data-bus transceiver . When DT/R is asserted High, the mic roc on trol ler
transmits data. When this pin is deasserted Low, the microcontroller receives
data. DT/R is three-stated with a pullup during a bus-hold or reset condition.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Data Byte Encoding
BHE AD0 Type of Bus Cycle
00Word transfer
0 1 High byte transfer (bits 15–8)
1 0 Low byte transfer (bits 7–0)
11Refresh
Am186™CH HDLC Microcontroller Data Sheet 15
HLDA {CLKSEL1} O Bus-Hold Acknowledge is asserted to indicate to an external bus master that
the microcontroller has relinquished control of the local bus. When an external
bus master requests control of the local bus (by asserting HOLD), the
microcon troller complet es the bus cycle in pro gress, the n relinquishes control of
the bus to the external bus mast er b y asserting HLDA and three-stat ing S 2–S0,
AD15–AD0, S6, and A19–A0. The following are also three-stated and have
pullups: UCS, LCS, MCS 3–MCS0, PCS7–PCS0, DEN, RD, WR , BHE, WHB,
WLB, and DT/R. ALE is three-stated and has a pulldown.
When the external bus master has finished using the local bus, it indicates this
to the microcontroller by deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for example, for refresh), the
microcontroller deasserts HLDA before the external bus master deasserts
HOLD. The external bus master must be able to deassert HOLD and allow the
microcontroller access to the bus. See the timing diagrams for bus hold on
page 59.
HOLD — STI Bus-Hold Requ est indicates to the microcontroller that an e xternal bus master
needs control of the local bus.
The microcontroller HOLD latency time—the time between HOLD request and
HOLD acknowledge—is a function of the activity occurring in the processor
when the HOLD request is received. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received by the processor. This
implies that if a HOLD request is received just as a DMA transfer begins, the
HOLD latency can be a s great as four bus cycles. This occurs if a DMA word
transfer operation is taking place from an odd address to an odd address. This
is a total of 16 clock cycles or more if wait states are required. In addition, if
locked transfers are performed, the HOLD latency time is increased by the
length of the locked transfer. HOLD latency is also potentially increased by
DRAM refreshes.
The board designer is responsible for properly terminating the HOLD input.
For more information, see the HLDA pin description above.
RD —ORead Strobe indicates to the system that the microcontroller is performing a
memory or I/O read cycle. RD is guaranteed not to be asserted before the
address and data bus is three-stated during the address-to-data transition. RD
is three-stated with a pullup during bus-hold or reset conditions.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
16 Am186™CH HDLC Microcontroller Data Sheet
S0
S1
S2
—
—
—
OBus Cycle Sta tus 2–0 indicate to the syst e m th e ty pe of bus cycle in prog ress.
S2 can be used as a logical memory or I/O indicator, and S1 can be used as a
data transmit or receive indicator. S2–S0 are three-stated during bus hold and
three-st ated w it h a pu llu p during rese t. Th e S2–S0 pins are en cod ed as fo llows:
S6 — O Bus Cycle Status Bit 6: This signal is asserted during t1–t4 to indicate a DMA-
initiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and
three-stated with a pulldown during reset.
SRDY [PIO35] STI Synchronous Ready indicates to the microcontroller that the addresse d
memory space or I/O de vice will complete a data transfer . The SRD Y pin accepts
an active High input synchronized to CLKOUT.
Using SRDY instead of ARDY allows a relaxed system timing because of the
elimination of the one-half clock period required to internally synchronize ARD Y.
To alwa ys assert the ready cond ition to the microc ontroller , tie SRDY High. If the
system does not use SRDY, t ie the pin Low to yield control to ARDY.
WHB
WLB
—
—
O
O
Write Hi gh Byte and Write Low Byte indicate to th e syst em which bytes of the
data bus (upper, lower, or both) participate in a writ e cycle. In 80C186
microcontroller des ig ns, this inf ormation is provided by BHE , AD0, and WR.
However, by using WHB and WLB, the standard system interface logic and
external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WLB is asserted with A D7–AD0. WLB is the logical AND of AD0 and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WR [PIO15] O Write Strobe indicates to the syst em th at the data on t he bu s is to be w ritten to
a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset
conditions.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Bus Status Pins
S2 S1 S0 Bus Cycle
0 0 0 Reserved
0 0 1 Read data from I/O
0 1 0 Write data to I/O
011Halt
1 0 0 Instruction fetch
1 0 1 Read data from memor y
1 1 0 Write data to memory
1 1 1 None (passive)
Am186™CH HDLC Microcontroller Data Sheet 17
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT —OClock O utp ut su pplies the clo c k to the sy stem . Dependi ng on the v alues of the
CPU mode select pi ns tr aps, {CLKSEL1} and {CLKSEL2}, CLKOUT oper ate s at
either the PLL frequency or the source input frequency during PLL Bypass
mode. (See Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.)
CLKOUT remains active during bus-ho ld or reset conditions.
The DISCL K bit in the SYSCON register can be set to disable the CLKOUT
signal. Refer to the
Am186™CC/CH/CU Microcontrollers Register Set Manual
,
order #21916.
All synchronous AC timing specifications not associated with SSI, HDLCs, and
UARTs are synchronous to CLKOUT.
RES —STIReset requires the microcontroller to perform a reset. When RES is asserted,
the microco ntroller imm ediately terminate s its present activ ity, clears its internal
logic , and on the dea ssertion of RES , transfer s CPU control to the re set address
FFFF0h.
RES must be asserted for at least 1 ms to allow the internal circuits to stabilize.
RES can be asserted asynchronously to CLK OUT because RES is synchronized
internally. For proper initialization, VCC must be within specifications, and
CLKOUT mus t be s tab le fo r more t han four CLKOUT periods during wh ich RES
is asserted.
If RES is asserted while the watchdog timer is pe rforming a w atchdog-timer reset,
the external reset take s preceden ce o ver the watchdog-timer reset. This means
that the RESOUT signal asserts as with any external reset and the WDTCON
register will not hav e the RSTFLA G bit set. In addition, the microcontroller will e xit
reset based on the e xternal reset timing (i.e ., 4.5 c locks after the deassertion of
RES rather than 216 clo c k s after the watchdog timer timeout occurred).
The microcontroller begins fetching instructions approximately 6.5 CLKOUT
periods after R ES is deasserted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via a resistor-capacitor (RC) network.
RESOUT — O Reset Out indicates that the microcontroller is being reset (either externally or
internally), and the signal can be used as a system reset to reset any external
peripherals connected to RESOUT.
During an external reset, RESOUT remains active (High) for two clocks after
RES is deasserted. The microcon troller e xits res et and begins the first val id bus
cycle approximately 4.5 clocks after RES is deasserted.
[UCLK] PIO21 STI UART Clock can b e used inst ead of the processor cloc k as the sour ce cloc k for
either the UART or the High-Speed UART. The source clock for the UART and
the High-Speed UART are selected independently and both can use the same
source.
X1
X2
—
—
STI
O
CPU Crystal Input (X1) and CPU Crystal Output (X2 ) prov ide conne ctions fo r
a fundamental mode, parallel-resonant crystal used by the internal oscillator
circuit. If a n external osc illator is us ed, inject the s ignal directl y into X1 and lea ve
X2 floating.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
18 Am186™CH HDLC Microcontroller Data Sheet
PINSTRAPS (See Table 26, “Reset Configuration Pins (Pinstraps),” on page A-7.)
RESERVED
RSVD_101 — The pins RSVD_104–RSVD_101, RSVD_75, RSVD_76, RSVD_80, and
RSVD_81 are reserved.
The RSVD_75 pin should be tied e xternally to VSS. All other se ven reserved pins
should not be connected.
RSVD_102 —
RSVD_103 —
RSVD_104 —
RSVD_75 —
RSVD_76 —
RSVD_80 —
RSVD_81 —
POWER AND GROUND
VCC (16) — STI Digital Power Supply pins supp ly pow er (+3.3 ± 0.3 V) to the Am186CH HDLC
microcontroller logic.
VCC _A (1) — STI Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and
PLLs.
VSS (16) — STI Digital Ground pins connect the Am186CH HDLC microcontroller logic to the
system ground.
VSS _A (1) — STI Analog Ground pin connects the oscillators and PLLs to the system ground.
DEBUG SUPPORT
QS0
QS1
—
—
O
O
Queue Status 1–0 values provide information to the system concerning the
interaction of the CPU and the instruction queue. The pins have the following
meanings:
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,
CLKOUT, {CLKSEL2–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,
RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, WHB, WLB, WR. See the
Am186CC/CH/CU Microco ntrollers User’s Manual
,
order #21914, for more information.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Queue Status Pins
QS1 QS0 Queue Operation
0 0 None
0 1 First opcode byte fetched from queue
1 0 Queue was initialized
1 1 Subsequent byte fetched from queue
Am186™CH HDLC Microcontroller Data Sheet 19
CHIP SELECTS
LCS [RAS0]OLower Memory Chip Select indicates to the syst em that a mem ory ac cess i s in
progress to the lower memory block. The base address and size of the lower
memory block are programmable up to 512 Kbyte. LCS ca n b e c on f ig ured fo r 8-
bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold
or reset conditions.
[MCS0]
MCS1
MCS2
[MCS3]
{UCSX8}
PIO4
[CAS1]
[CAS0]
[RAS1]
PIO5
OMidrange Memory Chip Selects 3–0 indicate to the system that a memory
access is in progress to the corresponding region of the midrange memory block.
The base address and size of the midrange memory block are programmable.
The midrange chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors during bus-hold or
reset conditions.
[MCS0] can be programmed as the chip select for the entire middle chip select
address range.
Unli ke the U CS and LCS chip sele cts that oper ate relativ e to the earlier tim ing of
the nonm ultipl e xed A address b us , the MC S out puts as sert with the multi plexed
AD address and data bus timing.
PCS0
PCS1
PCS2
PCS3
[PCS4]
[PCS5]
[PCS6]
[PCS7]
[PIO13]
[PIO14]
—
—
PIO3
{CLKSEL2}
PIO2
PIO32
PIO31
OPeripheral Chip Selects 7–0 indicate to the system that an access is in
progress to the corresp onding region of the peripher al addre ss b loc k (eith er I/O
or memory address space). The b ase address of th e peripheral address b lock i s
progr a mmable. PCS7–PCS0 are three-stated with pullup resistors during bus-
hold or reset conditions.
Unli ke the U CS and LCS chip sele cts that oper ate relativ e to the earlier tim ing of
the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed
AD address and data bus timing.
UCS {ONCE}OUpper Memory Chip Select indi cates to the system that a m emory access is in
progress to the upper memor y block. The base address and size of the upper
memory block are programmable up to 512 Kbytes. UCS is three-stated with a
weak pullup during bus-hold or reset conditions.
The UCS can be configured fo r an 8-bit or 16-bit bus size out of reset . For
additional information, see the {UCSX8} pin description in Table 26, “Reset
Configuration Pins (Pinstraps),” on page A-7.
After reset, UCS is active for the 6 4-Kbyte me mory rang e from F0000h to FFFFFh,
including the re set addres s of FFFF0h.
DRAM
[CAS0]
[CAS1]
MCS2
MCS1
OColumn Address Strobes 1–0: When either the upper or lower chip select
regions are configured for DRAM, these pins provide the column address strobe
signals to the DRAM. The CAS signals can be used to perform byte writes in a
manne r simi lar to W LB and WHB, respectively (i.e., [CAS0] corresponds to the
low byte (WLB) and [CAS1] corresponds to the high byte (WHB)).
[RAS0]LCS ORow Address Strobe 0: When the lower chip select region is configured to
DRAM, this pin provide s the row addres s strobe sign al to the low er DRAM ban k.
[RAS1][MCS3]
PIO5 ORow Address Strobe 1: When the upper chip select region is configured to
DRAM, this pin provides the row address strobe signal to the upper DRAM bank.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
20 Am186™CH HDLC Microcontroller Data Sheet
INTERRUPTS
NMI —STINonmaskable Interrupt indicates to the microcontroller that an interrupt request
has occurred. The N MI signal is the highest priority hardware i nterrupt and cannot
be masked. The m icroco ntrol ler alwa ys transfers pro gr am exec ution to the
location specified by the nonmask ab l e interrupt vector in the microcontroller’s
interrupt vector table when NMI is asserted.
Although NMI is the highest priority hardware interrupt source, it does not
partici pate in the priority reso lut ion proces s of the mask ab le inte rrupts. There is
no bit associated with NMI in the interrupt in-service or interrupt request
registers. This means that a new NMI request can interrupt an executing NMI
interrupt service routin e. As with al l hardw are in terrupts , the int errupt flag (IF) is
cleared when the proce ssor takes the interrupt, disab ling the mas kable interrupt
sources. However, if maskable interrupts are re-enabled by software in the NMI
interrupt service routine (for example, via the STI instruction), the fact that an
NMI is currently in service does not have any effect on the priority resolution of
ma skable in terrupt requests. For this reason, it is strongly advised that the
interrupt service routine for NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized internally, and it
initiates the interrupt at the next instruction boundary . To guarantee that the interrupt
is recognized, the NMI pin must be asserted for at least one CLKOUT period.
The board designer is responsible for properly terminating the NMI input.
INT5–INT0
[INT6]
[INT7]
[INT8]
—
PIO19
PIO7
[PWD]
PIO6
STI
STI
STI
STI
Maskable Interrupt Requests 8–0 indicate to the microcontroller that an
external interrupt request has occurred. If the individual pin is not masked, the
microcontroller transfers program execution to the location specified by the
associated interrupt vector in the microcontroller’s interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. The interrupt polarity is programmable.To guarantee interrupt
recognition for edge-triggered interrupts, the user should hold the interrupt
source for a minimum of five system clocks. A second interrupt from the same
source is not recognized until after an acknowledge of the first.
The board designer is responsible for properly terminating the INT8–INT0 inputs.
Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35.
(See the
Am186CC/CH/CU Microcontrollers User’s Manual
, order #21914 for more information.)
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CH HDLC Microcontroller Data Sheet 21
PROGRAMMABLE I/O (PIOS)
PIO47–PIO0 (For multiplexed
signals see Table
27, “PIOs Sorted
by PIO Number,”
on page A-8 and
Table 28, “PIOs
Sorted by Signal
Name,” on page
A-9.)
BShared Programmable I/O pins can be programmed with the following
attributes: PIO function (enabled/disabled), direc tion (input/outpu t), and weak
pullup or pulldown.
After a res et, th e PIO pins default to v arious c onfigu ratio ns . The colu mn e ntitled
“Pin Configuration Following System Reset” in Table 27 on page A-8 and
Table 28 on page A-9 lists the defaults for the PIOs. Most of the PIO pins are
configured as PIO in puts w ith pull up after reset. See Table 30 on page A-11 for
detailed termination information fo r all pins . Th e s ys tem in iti ali zation c ode m u st
reconfigure any PIO pins as requ ire d.
PIO5, PIO15, PIO27, PIO29, PIO30, and PIO33–PIO35 are capable of
generating an interrupt on the shared interrupt channel 14.
The multiplexed signals PIO33/ALE, PIO8/ARDY, PIO34/BHE, PIO30/DEN,
PIO29/DT/R, PIO14/PCS1–PIO13/PCS0, PIO3 5/SR DY, and PIO15/W R default
to non-P IO operation at reset.
The following PIO signals are m ultiple xed wi th alternate signals tha t can be used
by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consider any emulator
requirements for the alternate signals before using these pins as PIOs.
PROGRAMMABLE TIMERS
[PWD] [INT8]
PIO6 STI Pulse-W idth Demodulator: If pulse-wid th demodulation is enable d, [PWD]
processe s a s ignal th rough t he Schmitt trigge r inpu t. [PWD ] is used int ernally to
drive [TMRIN0] and [INT8], and [PWD] is inverted internally to drive [TMRIN1]
and an additional internal interrupt. If interrupts are enabled and Timer 0 and
Timer 1 are prop erly config ured, the pulse wid th of the al ternating [PWD] sig nal
ca n be calculated by comparing the values in Timer 0 and Timer 1.
In PWD mode , the sign als [TMRIN0]/ PIO27 and [TMRIN 1]/PIO0 can be us ed as
PIOs. If they are not used as PIOs they are ignored internally.
The addit ional internal inter rupt used in PWD mode uses the sa me inter rupt
channel as [INT7]. If [INT7] is used, it must be assigned to the shared interrupt
channel.
[TMRIN0]
[TMRIN1]
PIO27
PIO0
STI
STI
Timer Inpu ts 1–0 supply a clock or control signal to the internal microcontroller
timers. After internally synchronizing a Low-to-High transition on [TMRIN1]–
[TMRIN0], the microcontroller increments the timer. [TMRIN1]–[TMRIN0] must
be tied High if not being used. When PIO is enabled for one or both, the pin is
pulled High internally.
[TMRIN1]–[TMRIN0] are driven internally by [INT8]/[PWD] when pulse-width
demodulation functionality is enabled. The [TMRIN1]–[TMRIN0] pins can be
used as PIOs when pulse-width demodulation is enabled.
[TMROUT0]
[TMROUT1]
PIO28
PIO1
O
O
Timer Outputs 1–0 su pply the system w ith either a singl e pulse or a contin uous
waveform with a programmable duty cycle. [TMROUT1]–[TMROUT0] are three-
stated during bus-hold or reset conditions.
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U] PIO26 STI Receive Data UART is the asynchronous serial receiv e data signal that supplies
data from the asynchronous serial por t to the microcontroller.
[TXD_U] PIO20 O Transmit Data UART is the asynchronous serial transmit data signal that
su pplie s data to the asynchronous serial port fr om th e micr ocont roller.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
22 Am186™CH HDLC Microcontroller Data Sheet
[CTS_U] PIO24 STI Clear-T o-Send UART provides the Clear-to-Send signal from the asynchronous
serial port when hardware flow control is enabled for the port. The [CTS_U]
signal gates the transmission of data from the serial port transmit shift register.
When [CTS_U] is asser ted, the transmitter begins transmission of a frame of
data, if an y is available . If [CTS_U ] is deasserted, the tr ansmitte r holds the data
in the s erial port tran smit shift register. The v al ue of [CTS_U] is checked only at
the beginning of the transmission of the frame. [CTS_U] and [RTR_U] form the
hardware handshaking interface for the UART.
[RTR_U] PIO25 O Ready-To-Re ceive UART provides the Ready-to-Receive signal for the
asynchronous serial port when hardware flo w control is enabled for the port. The
[RTR_U] sig nal is asserted when th e associated se rial port receiv e data re gister
does not contain valid, unread data. [CTS_U] and [RTR_U] form the hardware
handshaking interface for the UART.
HIGH-SPEED UART
[RXD_HU] PIO16 STI Receive Data High-Speed UART is the asynchronous serial receive data signal
that supplies data from the high-speed serial port to the microcontroller.
TXD_HU —OTransmit Data High-Speed UART is the asynchronous serial transmit data
signal that supplies data to the high-speed serial port from the microcontroller.
[CTS_HU] PIO46 STI Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the
high-spee d as ynchrono us se rial port when hard ware flow co ntrol is enab led for
the port. The [CTS_HU] signal gates the transmission of data from the serial port
transmit shift register. When [CTS_HU] is asserted, the transmitter begins
transmission of a frame of data, if any is available. If [C TS_HU ] is deasserted,
the transmitter holds the data in the serial port transmit shift register. The value
of [CTS_HU] is checked only at the beginning of the transmission of the frame.
[CTS_HU] and [RTR_HU] form the hardware handshaking interface for the High-
Speed UART.
[RTR_HU]PIO47 OReady-T o-Receive High-Speed UART provides the Ready-to-Receive signal to
the high-spe ed asynch ronous serial port when hardw are flow control is en able d
for the port. The [RTR_HU] signal is asserted when the associated serial port
receive data register does not contain valid, unread data. [CTS_HU] and
[RTR_HU] form the hardware handshaking interface for the High-Speed UART.
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK] PIO11 O Serial Clock provides the clock for the synchronous serial interface to allow
synchronous transfers between the microcontroller and a slave device.
[SDATA] PIO12 B Serial Data is used to transmit and receiv e data between the microcontroller and
a slave device on the synchronous serial interface.
[SDEN] PIO10 O Serial Data Enable enab l es data tr ansfe rs on the syn chron ous serial in terface .
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATION INTERFACES
HDLC Channel A (DCE)
DCE_RXD_A [PCM_RXD_A] STI DCE Receive Data Channel A is the serial data inp ut pin for the channel A DCE
interface.
DCE_TXD_A [PCM_TXD_A] OD-O DCE Transmit Data Channel A is the serial data output pin for the channel A
DCE interface.
DCE_RCLK_A [PCM_CLK_A] STI DCE Receive Clock Channel A provides the receive clock to the channel A
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the DCE_TCLK_A pin externally.
The DCE func tion is the de fault at reset, so th e board desig ner is responsib le for
properly terminating the DCE_RCLK_A input.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CH HDLC Microcontroller Data Sheet 23
DCE_TCLK_A [PCM_FSC_A] STI DCE Transmit Clock Channel A provides the transmit clock to the channel A
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the DCE_RCLK_A pin externally.
The DCE func tion is the de fault at reset, so th e board desig ner is responsib le for
properly terminating the DCE_TCLK_A input.
[DCE_CTS_A] [PCM_TSC_A]
PIO17 STI DCE Clear-To-Send Channel A indicates to the channel A DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_A] and
[DCE_RTR_A] provide the handshaking for the channel A DCE interface.
[DCE_RTR_A]PIO18 O DCE Ready-to-Receiv e Channel A indicates to an e xternal serial i nterface that
the internal channel A DCE interf ace is rea dy to accept data. [DCE_CTS_A ] and
[DCE_RTR_A] provide the handshaking for the channel A DCE interface.
HDLC Channel B (DCE)
[DCE_RXD_B] [PCM_RXD_B]
PIO36 STI DCE Receive Data Channel B is the serial data input pin for the channel B DCE
interface.
[DCE_TXD_B] [PCM_TXD_B]
PIO37 OD-O DCE Transmit Data Channel B is the serial data output pin for the channel B
DCE interface.
[DCE_RCLK_B] [PCM_CLK_B]
PIO40 STI DCE Receive Clock Channel B provides the receive clock to the channel B
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_TCLK_B] pin externally.
[DCE_TCLK_B] [PCM_FSC_B]
PIO41 STI DCE Transmit Clock Channel B provides the transmit clock to the channel B
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_RCLK_B] pin externally.
[DCE_CTS_B] [PCM_TSC_B]
PIO38 STI DCE Clear-To-Send Channel B indicates to the channel B DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_B] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
[DCE_RTR_B] PIO39 O DCE Ready-to-Receiv e Channel B indicates to an e xternal serial i nterface that
the internal channel B DCE interf ace is rea dy to accept data. [DCE_CTS_B ] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
HDLC Channel A (PCM)
[PCM_RXD_A] DCE_RXD_A STI PCM Receive Data Channel A is the serial data input pin for the channel A PCM
Highway interface.
[PCM_TXD_A] DCE_TXD_A O-LS-
OD PCM Transmit Data Channel A is the serial data output pin for the channel A
PCM Highway interface.
[PCM_CLK_A] DCE_RCLK_A STI PCM Clock is the single transmit and receive data clock pin for the channel A
PCM Highway interface.
[PCM_FSC_A] DCE_TCLK_A STI PCM Frame Synchronization Clock provides the Frame S ynchr onization
Clock input (usually 8 kHz) for the channel A PCM Highway interface.
[PCM_TSC_A] [DCE_CTS_A]
PIO17 OD PCM T ime Slot Cont rol A enables an external buffer dev ice when channel A PCM
Highway data is present on the [PCM_TXD_A] output pin in PCM Highwa y mode.
HDLC Channel B (PCM)
[PCM_RXD_B] [DCE_RXD_B]
PIO36 STI PCM Receive Data Channel B is the serial data input pin for the channel B PCM
Highway interface.
[PCM_TXD_B] [DCE_TXD_B]
PIO37 O-LS-
OD PCM Transmit Data Channel B is the serial data output pin for the channel B
PCM Highway interface.
[PCM_CLK_B] [DCE_RCLK_B]
PIO40 STI PCM Clock is the single transmit and receive data clock pin for the channel B
PCM Highway interface.
[PCM_FSC_B] [DCE_TCLK_B]
PIO41 STI PCM Frame Synchronization Clock provides the Frame Synchronizat ion
Clock input (usually 8 kHz) for the channel B PCM Highway interface.
[PCM_TSC_B] [DCE_CTS_B]
PIO38 OD PCM T ime Slot Cont rol B enables an external buffer device when channel B PCM
Highway data is present on the [PCM_TXD_B] output pin in PCM Highway mode.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
24 Am186™CH HDLC Microcontroller Data Sheet
ARCHITECTURAL OVERVIEW
The architectural goal of the Am186CH HDLC
microcontroller is to provide comprehensive
communications features on a processor running the
widely known x86 instruction set. The Am186CH HDLC
microcontroller combines two HDLC channels and
general communications peripherals with the Am186
microcontroller. This highly integrated microcontroller
provides system cost and performance advantages for
a wide range of communications applications. Figure 1
is a block diagram of the Am186CH HDLC
microcontroller followed by sections providing an
overview of the features.
Figure 1. Am186CH Microcontroller Block Diagram
Detailed Description
■Two independent High-level Data Link Control
(HDLC) channels support a wide range of
external interfaces
– External interface connection for HDLCs can be
PCM Highway or raw DCE
– Data rate of up to 10 Mbit/s
– Receive and transmit FIFOs
– Support for HDLC, Synchronous Data Link
Control (SDLC), Line Access Procedure
Balanced (LAP-B), Line Access Procedure D
(LAP-D), Point-to-Point Protocol (PPP), and
v.120 (support of v.110 In transparent mode)
– Two dedicated buffer descriptor ring SmartDMA
channels per HDLC
– One independent time-slot assigner per HDLC
– Clear-to-Send/Re ad y- to- R ec eive (CTS/RTR)
hardware handshaking and auto-enable operation
– Collision detection for multidrop applications
– Transparency mode
– Address comparison on receive
– Flag or mark idle operation
■Two independent Time Slot Assigners (TSAs)
provide flexible time slot allocation
– Allows isolation of Ti me Division Multiplexe d (TDM)
time slot of choice from a v ariety of TDM carriers
– Up to 4096 sequential bits can be isolated
– TDM bus can have up to 512 8-bit time slots
– Start bit and stop bit times identify isolated
portion of TDM frame
– 12-bit counters define the start/stop bit times as
the number of bits after frame synchronization
– Entire frame do wn t o 1 bit per fr ame can b e isolated
■ 8 Direct Memory Access (DMA) channels
– Four buffer descriptor ring SmartDMA channels
for the two HDLC channels
– Four general-purpose DMAs support the two
integrated asynchronous serial ports; two DMA
channels have external DMA request inputs
SmartDMA
General-
Purpose
DMA (4)
Physical
Interface
Raw DCE
PCM
Serial Communications Peripherals
TSA
TSA
Muxing
Glueless
Interface
to RAM/ROM DRAM
Controller
Am186
CPU Chip
Selects (48) Watchdog
Timer
Interrupt
Controller UART High-Speed
UART with
Autobaud
Synchronous
HDLC
HDLC
(14)
Highway
(17 Ext.
Sources)
PIOs Serial
Interface (SSI)
Timers
(3)
System PeripheralsMemory Peripherals
Channels
(4)
Am186™CH HDLC Microcontroller Data Sheet 25
■High-speed asynchronous serial interface
provides enhanced UART functions
– Capable of sustained operation at 460 Kbaud
– 7-, 8-, or 9-bit data transfers
– FIFOs to support high-speed operation
– DMA support available
– A utomatic baud-rate detection that allows
emulation of a Hayes AT-compatible modem
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■Asynchronous serial interface (UART)
– 7-, 8-, or 9-bit data transfers
– DMA support available
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■Synchronous Serial Interface (SSI) provides
half-duplex, bidirectional interface to high-
speed peripherals
– Useful with many telecommunication interface
perip herals such as code cs , line interface units,
and transceivers
– Selectable device-select polarity
– Selectab le bit shift order on transmit and receive
– Glueless connection to AMD Subscriber Line
Audio Processing Cir cuit (SLAC™) devices
■Clocking options offer high flexibility
– CPU can run in 1x, 2x, or 4x mode
Am186™ Embedd ed CPU
All members of the Am186 family, including the
Am186CH HDLC microcontroller, are compatible with
the original industry-standard 186 parts, and build on
the same core set of 186 registers, address generation,
I/O space, instruction set, segments, data types, and
addressing modes.
Memory Organization
Memory is organized in sets of segments. Each
segme nt is a li near co ntiguous sequence of 64K (216)
8-bit bytes. Memory is addressed using a two-
component address consisting of a 16-bit segment
value and a 16-bit offset. The 16-bit segment values
are contained in one of four internal segment registers
(CS, DS, SS, or ES). The physical address is
calculated by shifting the segment value left by 4 bits
and adding the 16-bit offset value to yield a 20-bit
physical address (see Figure 2). This allows for a
1-Mbyte physical address size.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the
segment register used for physical address generation
is implied by the addressing mode used (see Table 5
on page 26).
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN/INS and OUT/OUTS)
address the I/O space with either an 8-bit port address
specified in the instr uction, or a 16-bit por t address in
the DX register. Eight-bit port addresses are zero-
extended such that A15–A8 are Low.
Figure 2. Two-Component Address Example
1 2 A 4 0
0 0 0 2 2
1 2 A 6 2
1 2 A 4
0 0 2 2
Shift
Left
4 Bits
To Memory
015
15
15
19
19
0
0
0
0
Logical Address
Segment Base
Offset
Physical Address
26 Am186™CH HDLC Microcontroller Data Sheet
Serial Communications Support
The Am186CH HDLC microcontroller supports five
serial interfaces. This includes two HDLC channels,
two UAR Ts, and a synchronous serial interface.
Two HDLC Channels and Two TSAs
The Am186CH HDLC microcontroller provides two
HDLC chan nels that su ppor t the HDLC, SDLC, LAP-B,
LAP-D, PPP, and v.120 protocols. The HDLC channels
can also be used in transparent mode to support v.110.
Each HDLC channel can connect to an external serial
interface directly (nonmultiplexed mode), or can pass
through a TSA (multiplex ed mode). The flexible interface
multiple xing arrangement allows each HDLC channel to
have its own external raw DCE or PCM highway
inter face, shar e a co mmon P CM hig hway or ot her time
TDM bus with one or more channels, or work in some
combination.
Each HDLC channel’s independent TSA allows it to
extract a subset of data from a TDM bus. The entire
frame, or as little as 1 bit per frame, can be extracted.
Twelve-bit counters define the star t/stop bit times as
the number of bits after frame synchronization. The
time slot can be an arbitrary number of bits up to 4096
bits. Start bit and stop bit times identify the isolated
portion of the TDM frame. Support of less than eight
bits per time slot, or
bit slotting
, allows isolation of from
one to eight bits in a single time slot. Each TDM bus
can have up to 512 8-bit time slots. Support of these
features allows interoperation with PCM highway, E1,
IOM-2, T1, and other TDM buses.
The HDLC channels have features that make the
Am186CH HDLC microcontroller an attractive device
for use where general HDLC capability is required.
These features include CTS/RTR hardware
handshaking and auto-enable operation, collision
detection for multidrop applications, transparency
mode, address comparison on receive, flag or mark
idle operation, two dedicated buffer descriptor ring
SmartDMA channels per HDLC, transmit and receive
FIFOs, and full-duplex data transfer. Each TSA
channel can support a burst data rate to/from the
HDLC of up to 10 Mbit/s in both raw DCE and PCM
Highway modes. Total system data throughput is highly
dependent on the amount of per-packet and per-byte
CPU processing, the rate at which packets are being
sent, and other CPU activity.
When combined with the TSAs, the HDLC channels
can be used in a wide variety of applications such as
PCM highway, X.25, Frame Relay, and other
proprietary Wide Area Network (WAN) connections.
Four SmartDMA™ Channels
The Am186CH HDLC microcontroller provides four
Smar tDMA channels that provide a faster method for
moving data between peripherals and memory with
lower CPU utilization. SmartDMA transmits and
receives data across multiple memory buffers and a
sophisticated buffer-chaining mechanism. These
channels are always used in pairs: transmitter and
receiver. The transmit chann els can onl y transfer dat a
from memory to a peripheral; the receive channels can
only transfer data from a peripheral to memory.
The four channels (two pairs) are dedicated for use
with the two on-board HDLC channels.
In addition to the four SmartDMA channels, the
Am186CH HDLC microcontroller provides four
general-purpose DMA channels (see page 27).
Two Asynchronous Serial Ports
The Am186CH HDLC microcontroller has two
asynch ro nou s seria l p orts (a UART and a Hi gh- S pee d
UART) that provide full-duplex, bidirectional data
transfer at speeds of up to 115.2 Kbaud or up to 460
Kbaud, respectively. The High-Speed UART has
16-byte transmit and 32-byte receive FIFOs, special-
character matching, and automatic baud-rate
detection, suitable for implementation of a Hayes-
compatible modem interface to a host PC. There is
also a low er speed U ART that typically is used for a low
baud-rate system configuration port or debug port.
Each of these U AR Ts can derive its baud rate from the
system clock or from a separate baud-rate generator
clock input. Both UARTs support 7-, 8-, or 9-bit data
transfers; address bit generation and detection in 7- or
8-bit frames; one or two stop bits; even, odd, or no
parity; break generation and detection; hardware flow
control; an d DMA to and/or from th e ser ial p or ts usin g
the general-purpose DMA channels.
Table 5. Segment Register Selection Rules
Memory Reference Needed Segment Register Used Implicit Segment Selection Rule
Instructions Code (CS) Instructions (including immediate data)
Local Data Data (DS) All data references
Stack Stac k (SS) All stack pushes and pops;
any memory references that use the BP register
External Data (Global) Extra (ES) All string inst ruction reference s that use the D I register as an inde x
Am186™CH HDLC Microcontroller Data Sheet 27
Synchronous Serial Port
The Am186CH HDLC microcontroller includes one SSI
port that provides a half-duplex, bidirectional,
communications interface between the Am186CH
HDLC microcontroller and other system components.
This interface is typically used by the microcontroller to
monitor the status of other system devices and/or to
configure these devices under software control. In a
communications application, these devices could be
system components such as audio codecs, line
interface units, and transceivers. The SSI supports
data transfer speeds of up to 25 Mbit/s with a 50-MHz
system clock.
The SSI port operates as an interface master, with the
other attached devices acting as slave devices. Using
this proto col, th e micro contr oller sen ds a co mmand byt e
to the attached device, and then follows that with either
a read or write of a byte of data.
The SSI port consists of three I/O pins: an enable
(SDEN), a clock (SCLK), and a bidirectional data pin
(SDATA ). SDEN can be us ed dire ctly as an enable for
a single attached device. Whe n more than one device
requires control via the SSI, PIOs can be used to
provide enable pins for those devices.
The Am186CH SSI is, in gene ral, soft ware compa tible
with software written for the Am186EM SSI. (Additional
features have been added to the Am186CH SSI
implementation.) The Am186CH HDLC microcontroller
features the additional capability of selecting the
polarity of the SCLK and SDEN pins, as well as the shift
order of bits on the SDATA pin (least-significant-bit first
versus most-significant-bit first). The SSI port also
offers a programmable clock divisor ( di vidi ng the clock
from 2 to 256 in power of 2 increments), a bidirectional
transmit/recei ve shift register, and direct conne ction to
AMD SLAC device s.
System Peripherals
Interrupt Controller
The Am186CH HDLC microcontroller features an
interrupt controller that arranges the 36 maskable
interrupt requests by priority and presents them one at
a time to the CPU. In addition to interrupts managed b y
the interrupt controller, the Am186CH HDLC
microcontroller supports eight nonmaskable
interrupts—an external or internal nonmaskable
interrupt (NMI), a trace interrupt, and software
interrupts and exceptions.
The interrupt controller supports the 36 maskable
interrupt sources through the use of 15 channels.
Because of this, most channels support multiple
interrupt sources. These channels are programmable to
support the external interrupt pins and/or various
peripheral devices that can be configured to generate
interrupts. The 36 maskable interrupt sources include 19
internal sources and 17 external sources.
Four General-Purpose DMA Channels
The Am186CH HDLC microcontroller provides a total
of 12 DMA channels that can be used for data transfer
between memory and I/O spaces (i.e., memor y-to-I/O
or I/O-to-memory) or within the same space (i.e.,
memory-to-memory or I/O-to-I/O). In addition, the
Am186CH HDLC microcontroller supports data
transfer between peripherals and memory or I/O.
Internal peripherals that support general-purpose DMA
are Timer 2 and the two asynchronous serial ports
(UART and High-Speed UART). External peripherals
support DMA transfers through the external DMA
request pins. Each general-purpose channel can
accept synchronized DMA requests from one of three
sources: DMA request pins (DRQ1–DRQ0), Timer 2, or
the UARTs. In addition, system software can initialize
and start unsynchronized DMA transfers.
In addition to the four general-purpose channels, the
Am186CH HDLC microcontroller provides four
SmartDMA channels (see page 26).
48 Programmable I/O Signals
The Am186CH HDLC microcontroller provides 48
user-progr ammable input/output signals (PIOs). All b ut
six of the 48 signals share a pin with at least one
alter nate function. If an ap plication does not need the
alter nate fun ction, the asso ciated PIO c an be used by
programming the PIO registers.
If a pin is enabled to function as a PIO signal, the
alternate function is disabled and does not affect the
pin. A PIO signal can be configured to operate as an
input or output, with or without internal pullup or
pulldown resisto rs (pul lup or pul ldown d epends on the
pin configuration and is not user-configurable), or as an
open-drain output. Additionally, eight PIOs can be
configured as external interrupt sources.
Three Programmable Timers
There are three 16-bit programmable timers in the
Am186CH HDLC microcontroller. Timers 0 and 1 are
highly v ersatile and are each connected to two external
pins (each one has an input and an output). These two
timers can be used to count or time e xternal ev ents that
dri ve the time r input pins. Timers 0 an d 1 can also be
used to generate nonrepetitive or variable-duty-cycle
waveforms on the timer output pins.
Timer 2 is not connected to any external pins. It can be
used by software to generate interrupts, or it can be
polled for real-time coding and time-delay applications.
Timer 2 can also be used as a prescaler to Timer 0 and
Timer 1, or as a DMA request source.
The source clock for Timer 2 is one-fourth of the
system clock frequency. The source clock for Timers 0
28 Am186™CH HDLC Microcontroller Data Sheet
and 1 can be configured to be one-fourth of the system
clock, or they can be dr i ven from the ir re sp ec tive timer
input pins. When driven from a timer input pin, the timer
is counting the “event” of an input transition.
The Am186CH HDLC microcontroller also provides a
pulse width demodulation (PWD) option so that a
toggling input signal’s Low state and High state
durations can be measured.
Hardware Watchdog Timer
The Am186CH HDLC microcontroller provides a full-
featured watchdog timer, which includes the ability to
generate Non-Maskable Interrupts (NMIs), micro controller
resets, and system resets when the timeout value is
reached. The timeout value is programmable and ranges
from 210 to 226 processor clocks.
The watchdog timer is used to regain control when a
syste m has failed due to a software error or to failure of
an external device to respond in the expected way.
Software errors can sometimes be resolved by
recapturing control of the execution sequence via a
watchdog-timer-generated NMI. When an external
de vice fails to respond, or responds incorrectly, it may be
necessary to reset the controller or the entire system,
including external de vices. The watchdog timer provides
the flexibility to support both NMI and reset ge neration.
Memory and Peripheral Interface
System Interfaces
The Am186CH HDLC microcontroller bus interface
controls all accesses to the peripheral control block
(PCB), memory-mapped and I/O-mapped external
peri pherals, and memor y devices. Inter nal per ipherals
are accessed by the bus interface through the PCB.
The bus interface features programmable bus sizing;
individually selectable chip selects for the upper (UCS)
memory space, lower (LCS) memory space, all non-UCS,
non-LCS and I/O memory spaces; separate byte-write
enab le s; an d, bo ot op tio n from a n 8- o r 16 - bit d evice.
The integrated peripherals are controlled by 16-bit
read/write registers. The peripheral registers are
contained within an internal 1-Kbyte control block. At
reset, the base of the PCB is set to FC00h in I/O space.
The registers are physically located in the peripheral
devices they control, but they are addressed as a
single 1- Kbyte block. For detail s on the PCB regist ers,
refer to the
Am186™CC/CH/CU Microcontrollers
Register Set Manual
, order #21916.
Accesses to the PCB should be performed by direct
processor actions. The use of DMA to write or read
from the PCB results in unpredictable beha vior, except
where explicit exception is made to support a
peripheral function, such as the High-Speed UART
transmit and receive data registers.
The 80C186 and 80C188 microcontrollers use a
multiplex ed address and data (AD) bus. The address is
present on the AD bus only dur ing the t1 clock phase.
The Am186CH HDLC microcontroller continues to
provide the multiplexed AD bus and, in addition,
provide a nonmultiplexed address (A) bus. The A bus
provides an address to the system for the complete bus
cycle (t1–t4). During refresh cycles, the AD bus is
driv en during the t1 phase and the values are unknown
during the t2, t3, and t4 phases. The value driven on the
A bus is undefined during a refresh cycle.
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUT cycle in advance of the address on
the AD bus. When used with the modified UCS and
LCS outputs and the byte write enable signals, the
A19–A0 bus provides a seamless interface to SRAM,
DRAM, and Flash/EPROM memory systems.
F or systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186CH HDLC microcontroller
duri ng the nor mal ad dress portion of the bus cycle for
access es to upper (UCS ) and/or lower (LCS ) address
spaces. In this mode, the affected bus is placed in a
high-impedance state during the address portion of the
bus cycle. This feature i s enabled through the DA bits
in the Upper Memor y Chip Select (UMCS) and L ower
Memory Chip Select (LMCS) registers.
When address disable is in effect, the number of
signals that assert on the bus during all normal bus
cycles to the associated address space is reduced,
thus decreasing power consumption, reducing
processor switching noise, and preventing bus
contention with memory de vices and peripherals when
operating at high clock rates.
If the A DEN p in i s ass erted du ri ng pr oc essor rese t, the
value of the D A bits in the UMCS and LMCS registers is
ignor ed and the address is dr iven on the AD bus for a ll
accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed
address bus and providing support for existing
emulation tools. For details on these registers, refer to
the
Am186™CC/CH/CU Microcontrollers Register Set
Manual
, ord er #2 19 16 .
Figure 3 on page 29 shows the affected signals during
a normal read or write operation. The address and data
are multiplexed onto the AD bus.
Figure 4 on pa ge 29 shows a bus cy cle when addre ss
bus disable is in effect, which causes the AD bus to
operate in a nonmultiplexed data-only mode. The
A bus has the address during a read or write operation.
Am186™CH HDLC Microcontroller Data Sheet 29
Figure 3. Am186CH Microcontroller Address Bus — Default Operation
Figure 4. Am186CH Microcontroller—Address Bus Disable In Effect
CLKOUT
t1t2t3t4
AD15–AD0
(Read) Data
AD15–AD0
(Write)
LCS or UCS
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
MCSx, PCSx
CLKOUT
t1t2t3t4
AD15–AD0
(Write) Data
LCS or UCS
AD15–AD8
(Read)
AD7–AD0
(Read)
Address
Phase
Data
Data
Phase
Data
A19–A0 Address
30 Am186™CH HDLC Microcontroller Data Sheet
Bus Interface
The bus interface controls all accesses to external
peripherals and memory devices. External accesses
include those to memor y devices, as well as those to
memory-map ped and I/O - map ped per i phe rals and the
peripheral control block. The Am186CH HDLC
microcontroller provides an enhanced bus interface
unit with the following features:
■Nonmultiplexed address bus
■Separate byte write enables for high and low bytes
■Output enable
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an e x-
ternal address latch. On the Am186CH HDLC micro-
controller, byte write enables and a nonmultiplexed
address bus can reduce design costs by eliminating
this external log ic .
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid
one-half CLKOUT cycle i n advance of the address on
the AD bus. When used with the modified UCS and
LCS outputs and the byte write enable signals, the
A19–A0 bus provid es a sea mless inter face to exter nal
SRAM, and Flash memory/EPROM systems.
Byte Write Enables
The Am186CH HDLC microcontroller provides the
WHB (Write High Byte) and WLB (Write Low Byte)
signals that act as byte write enables .
WHB is the logical OR of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
OR of A0 and W R. W LB is Low when A0 and WR are
both Low.
The byte write enables are driven with the
nonmultiplexed address bus as required for the write
timing requirements of common SRAMs.
Output Enable
The Am186CH HDLC microcontr oller provide s the RD
(Read) signal that acts as an output enable for memory
or peripheral devices. The RD signal is Low when a
word or byte is read by the microcontroller.
DRAM Support
To support DRAM, the Am186CH HDLC
microcon troller has a fully integrated DRAM controller
that provides a glueless interface to 25–70-ns
Extended Data Out (EDO) DRAM. (EDO DRAM is
sometimes called Hyper-P age Mode DRAM.) Up to two
banks of 4-Mbit (256 Kbit x 16 bit) DRAM can be
accessed. Page Mode DRAM, Fast Page Mode
DRAM, Asymmetrical DRAM, and 8-bit wide DRAM are
not suppor ted. The microcontroller provides zero-wait
state operation at up to 50 MHz with 40-ns DRAM. This
allows designs requir ing larger amounts of memo r y to
save system cost over SRAM designs by taking
advantage of low DRAM memory costs.
The DRAM interface uses various chip select pins to
implement the RAS/CAS interface required by DRAMs.
The DRAM controller drives the RAS/CAS interface
appropriately during both normal memory accesses
and dur ing refre sh. All signal s required are generated
by the microcontroller and no e xternal logic is required.
The DRAM mul tip lexed addres s pi ns are connecte d t o
the odd address pins of the Am186CH HDLC
microcontroller, starting with A1 on the Am186CH
HDLC microcontroller connecting to MA0 on the
DRAM. The correct row and column addresses are
generated on these odd addres s pins duri ng a DRAM
access.
The RAS pins are multiplexed with LCS and MCS3,
allowing a DRAM bank to be present in either high or
low memor y space. The MCS1 an d M CS2 fun ction as
the upper and lower CAS pins, respectively, and define
which b yte of data in a 16-bit DRAM is being accessed.
The microcontroller supports the most common DRAM
refresh option, CAS-Before-RAS. All refresh cycles
contain three wait states to support the DRAMs at
various frequencies. The DRAM controller never
performs a burst access. All accesses are single
accesses to DRAM. If the PCS chip selects are
decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
Chip Selects
The Am186CH HDLC microcontroller provides six chip
select outputs for use with memor y devices and eight
more for use with per ipherals in either me mory or I/O
space. The six memory chip selects can be used to
address three memor y ranges. Each peripheral chip
select addresses a 256-byte block offset from a
programmable base address.
The microcontroller can be programmed to sense a
ready signal for each of the peripheral or memory chip
select lines. A bit in each chip select control register
determines whether the external ready signal is
required or ignored.
The chip se lects can con trol th e number of wait states
inser ted in the bus cycle. Although most memor y and
peri pheral devices ca n be acce ssed with three or less
wait states, some slower devices cannot. This feature
allows devices to use wait states to slow down the bus.
The chip se lect li nes are acti ve for all memory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
General enhancements over the original 80C186
include bus ma ste ring (thr ee- s tate ) supp ort for all c hi p
selects and activation only when the associated
register is written, not when it is read.
Am186™CH HDLC Microcontroller Data Sheet 31
Clock Control
The processor supports clock rates from 16 to 50 MHz
using an integrated crystal oscillator and PLL.
Commercial and industrial temperature ratings are
available. The CPU can run in 1x, 2x, or 4x PLL mode.
In-Circuit Emulator Support
Beca use pi ns ar e a n expensive reso ur ce, many pl ay a
dual role, and the programmer selects PIO operation or
an alter nate functio n. However, a pin c onfigured to be
a PIO may also be required for emulation support.
Therefore, it is important that before a design is
committed to hardware, a user should contact potential
emulator suppliers for a list of their emulator’s pin
requirements. The following PIO signals are
multiplexed with a lte rnate sign al s that may be us ed by
emulators: PIO8, PIO15, PIO33–PIO35.
The Am186CH HDLC microcontroller was des ig ned to
minimize conflicts. In most cases, pin conflict is
avoi ded. For ex ample, if the ALE signal is requir ed for
multiplex bus support, then it is not programmed as
PIO33. If the multiple x ed AD bus is not used, then ALE
can be programmed as a PIO pin. And if the
multiplexed bus is not in use, then the emulator does
not require the ALE signal. However, an emulator is
likely to always use the de-multiplexed address,
regardless of how the AD bus is programmed.
APPLICATIONS
The Am186CH HDLC microcontroller with its
integrated HDLC and other communications features
provides a hig hly integrated, c ost-effective solut ion for
a wide range of telecommunications and networking
applications.
■Linecard Applications: Typically, the microcontrol-
ler linecards used in Central Offices (COs), PABX
equipment, and other telephony applications require
one or two channels of HDLC. Linecard manufactur-
ers are moving to more lines per card for analog
POTS as a means of cost reduction. This and digital
linecards often require higher performance than ex-
isting 8-bit devices can offer. The Am186CH HDLC
microc on tr o ller is an ideal sol u tio n fo r these appl i ca -
tions because it integrates much of the necessary
glue lo gi c wh ile providing high er perf o rmance .
■Industrial Control: Embedded x86 processors
have long been used in the industrial control
market. These applications often require a robust,
high-performance processor solution with the
capability to easily communicate with other parts of
a system. TheAm186CH HDLC microcontroller
provides numerous interfaces to achieve this
communication, including the SSI interface, high-
speed UAR T, and the HDLC channels that also can
be used to create a multidrop backplane.
■General Communications Applications: The
Am186CH HDLC microcontroller will also find a
home in general embedded applications, because
many devices will incorporate communications
capability in the future. Many designs are adding
HDLC capability as a robust means of inter- and
intra-system communications. The microcontroller is
especially attractive for 186 designs adding HDLC.
Figure 5 on page 32 shows a 32-channel linecard
system application.
The 32-channel linecard design demonstrates the
Am186CH HDLC microcontroller’s use in a linecard
application where 32 incoming POTS lines are
aggregated onto a single E1 connection.
32 Am186™CH HDLC Microcontroller Data Sheet
Figure 5. 32-Channel Linecard System Application
*The Am186CH HDLC microcontroller does not have a USB peripheral controller or a GCI interface.
Am186™CH HDLC Microcontroller Data Sheet 33
CLOCK GENERATION AND CONTROL
The Am186CH HDLC microcontroller clocks include
the general system clock (CLKOUT), transmitter/
receiver clocks fo r each HDLC cha nnel, and the bau d
rate generator clock for UAR T and High-Speed UART.
The SSI and the timers (Timers 0, 1, and 2) derive their
clocks from the system clock.
Features
The Am186CH HDLC microcontroller clocks include
the following features and characteristics:
■A cr ys tal-contr olled os cillator that us es an exter nal
fundamental mode crystal or oscillator to generate
the system inpu t clock.
■An internal PLL that generates a system clock
(CLKOUT) that is 1x, 2x, or 4x the system input
clock.
■Each HDLC receives its clock inputs directly from
the external communication clock pins (TCLK _X
and RCLK_X ) i n al l m odes . The sy st em c lo ck must
be at least the same frequency as any HDLC clock.
– HDLC DCE and PCM modes support clocks up to
10 MHz.
■SSI clo ck (SCLK ) i s der i ved from the sy s tem cl ock,
divided by 2, 4, 8, 16, 32, 64, 128, or 256.
■Timers 0 and 1 can be configured to be driven by
the timer input pins (TMRIN1, TMRIN0) or at one-
fourth of the system clock. Timer 2 is driven at one-
fourth of the system clock.
■U ART clock can be derived from the internal system
clock frequency or from the UART clock (UCLK)
input.
See Figure 6 for a diagram of the basic clock
generation and Figure 7 on page 34 for suggested
clock frequencies and modes.
System Clock
The system PLL generates frequencies from 16 to
50 MHz. The reference for the system PLL can vary
from 8 to 40 MH z, depend ing on t he PLL mo de select ed
and the desired system frequency (see Figure 7 on
page 34).
The syst em PLL m odes are cho sen by the st ate of the
{CLKSEL1} and {CLKSEL2} pins during reset. For these
pinstrap settings see Table 26, “Reset Configuration
Pins (P ins tr a ps) ,” on page A- 7.
The system clock can be generated in one of two wa ys:
■Using the interna l PLL running at 1x, 2x, or 4x the
reference clock. The reference clock can be
generated from an external crystal using the
integrated oscillator or an e xternal oscillator input.
■Bypassing the internal PLL. The external reference
generated from either a crystal or an external
oscillator input is used to generate the system clock
(see “PLL Bypass Mode” on page 35).
Figure 6. System Clock Genera tion
{CLKSEL2}–{CLKSEL1}
CLKOUT
PLL Bypass Mode
1x
2x
4x
X1 X2 PLL
System Clock
Am186CH HDLC Microcontrolle r
34 Am186™CH HDLC Microcontroller Data Sheet
Figure 7. Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies
Crystal-Driven Clock Source
The internal oscillator circuit is designed to function
with an external parallel-resonant fundamental mode
crystal. The crystal frequency can vary from 8 to
40 MHz, depending on the PLL mode selected and de-
sired system frequency.
When sel ecti ng a crystal, th e load capac itanc e sho uld
always be specified (CL). This value can cause
variance in the oscillation frequency from the desired
specified value (resonance). The load capacitance and
the loading of the feedback network have the following
relationship:
where CS is the stray capacitance of the circuit.
Table 6 shows crystal parameter values. Figure 8
shows the system clocks using an external crystal and
the integrated oscillator . The specific values for C1 and
C2 must be determined by the designer and are
dependent on the c hara cteristics of the chose n crystal
and board design.
Figure 8. External Interface to Support Clocks—
Fundamental Mode Crystal
8-MHz to 25-MHz Xtal or Clock
4x Mode2x Mode1x Mode
32 MHz
System Operating Frequency
1The crystal oscillator is not guaranteed above 40 MHz.
16 MHz
20 MHz 30 MHz 40 MHz 50 M Hz
0-MHz to 24-MHz Xtal or Clock
0 MHz 24 MHz
PLL B ypass Mode
8-MHz to 12.5-MHz Xtal or Clock
1x Mode
2x Mode
4x Mode
16-M H z to 40-MH z Xtal or C lo c k
1
PLL
Bypass
Mode
(C1 ⋅ C2)
CL = (C1 + C2)+ CS
Table 6. Crys tal Parameters
Parameter Mi n.
Value Max.
Value Units
Frequency 8 40 MHz
ESR
8–24 MHz 20 90 ohms
24–50 MHz 20 60 ohms
Load capacitance 10 — pF
C2
C1
Xtal X1
X2
Am186™CH HDLC Microcontroller Data Sheet 35
Exter n al Clock Source
The internal oscillator also can be driven b y an e xternal
clock source. The external clock source should be
connected to the input of the inverting amplifier (X1)
with the output (X2) left unconnected. Figure 9 shows
the system clocks using an external clock source
(oscillato r bypass).
Note: X1 and X2 are not 5-V tolerant and have a
maximum input equal to V
CC
.
Figure 9. External Interface to Support Clocks—
External Clock Sourc e
Static Operation
The Am186CH HDLC microcontroller is a fully static
design and can be placed in static mode by stopping
the inp ut clock. See the P LL Bypas s Mode disc ussio n
below.
Note: It is the re spons ibil ity of the sy stem de sign er to
ensure that no short clock phases are generated when
starting or stopping the clock.
PLL Bypass Mode
The Am186CH HDLC microcontroller provides a PLL
Bypass m ode t hat al lows the X 1 inp ut fr equ ency to b e
anywhere from 0 to 24 MHz. When the microcontroller
is in PLL Bypass mode, the CLKOUT frequency equals
the X1 inp ut frequency. This mode must be used with
an external clock source. For PLL Bypass Mode
enabling, see Table 26, “Reset Configuration Pins
(Pinstraps),” on page A-7.
When changing frequency in PLL Bypass mode, the X1
input must not have any short or “runt” pulses. At
24 MHz, the nominal High/Low time is 21 ns. The
actual High times and Low times must not fall below 16
ns. These values allow a 60%/40% duty cycle at X1.
In the Am186CH microcontroller, the system clock
must be at the same or a greater frequency than the
HDLC clock and UCLK (if using UCLK). Therefore, if
reducing the system clock frequency, disable these
interfaces or run them at a lower frequency.
UART Baud Clock
The UART and High-Speed UART have two possible
clock sources: the system clock or the UCLK input pin.
If UCLK is used f or the UART c lock, the system clock
must be at least the same frequency as UCLK. The
clock configurations are shown graphically in
Figure 10.
The baud clock is generated by dividing the clock
source by the value of the baud rate divisor register.
The serial port logic can select its baud rate clock from
either an external pin (UCLK) or from the system clock.
The system o r UCLK c lock is sele cted indep endent of
any other settings.
The formula for determining the baud rate divisor
register value is:
BAUDDIV = (clock frequency/(16 • baud rate))
Note: UCLK canno t be clocked at a fr equency hig her
than the system clock frequency.
Figure 10. UART and High-Speed UART Clocks
External
Clock
NC
X1
X2
Baud
Divisor
System Clock
UCLK
UART/High-Speed UART
Oversampling
Clock
Oversample
Baud Clock
Divide for
Autobaud Clock
Clock S ele ct (High-Speed UART Only)
36 Am186™CH HDLC Microcontroller Data Sheet
POWER SUPPLY OPERATION
CMOS dynamic power consumption is propor tional to
the square of the operating voltage multiplied by
capacitance and operating frequency. Static CPU
operation can reduce power consumption by enabling
the system designer to reduce operating frequency
when possible. However, operating voltage is always the
dominant factor in power consumption. By reducing the
operating voltage from 5 V to 3.3 V for any device, the
power consumed is reduced by 56%.
Reduct ion of CPU an d system l ogic operatin g voltage
dramatically reduces overall system power consump-
tion. Addition al power savings can be realized as low-
voltage mass st orage and peripheral devices become
available.
Two basic strategies exist in designing systems
containing the Am186CH HDLC microcontroller. The
first strategy is to design a homogenous system in
which all logic components operate at 3.3 V. This
provides the lowest overall power consumption.
However, system designers may need to include
devices for which 3.3-V versions are not available.
In the second strategy, the sy stem desig ner must then
design a mixed 5-V/3.3-V system. This compromise
enables the system designer to minimize the system
logic power consumption while still including the
functionality of the 5-V features. The choice of a mixed
voltage system design also involves balancing design
complexity with the need for the additional features.
Power Supply Connections
Connect all VCC pins together to the 3.3-V power
supply and all ground pins to a common system
ground.
Input/Output Circuitry
To accommodate current 5-V systems, the Am186CH
HDLC microcontroller has 5-V tolerant I/O drivers. The
driv ers produce TTL-compatible driv e output (minimum
2.4-V logic High) and receive TTL and CMOS levels (up
to VCC + 2.6 V). The following are some design issues
that should be considered with mixed 3.3-V/5-V
designs:
nDuring power-up, if the 3.3-V supply has a
significant delay in achieving stable operation
relative to 5-V supply, then the 5-V circuitry in the
system may start driving the processor’s inputs
above the maximum levels (VCC + 2.6 V). The
system design should ensure that the 5-V supply
does not exceed 2.6 V above the 3.3-V supply
during a power-on sequence.
nPreferably, all inputs are driven by sources that can
be three-stated during a system reset condition.
The system reset condition should persist until
stable VCC conditions are met. This should help
ensure that the maximum input levels are not
exceeded during power-up conditions.
nPreferably, all pullup resistors are tied to the 3.3-V
supply, which ensures that inputs requir ing pullups
are not over stressed during power-up.
PIO Supply Current Limit
Each programmable I/O output is able to sink or source
a sustained 16-mA drive current. However, only 40 mA
of sustained PIO current is allowed for each supply pin
(VCC), and o nly 60 mA is allowed for each ground pi n
(VSS).
To calculate the PIO current for each supply or ground
pin, sum the applicable current (source or sink) of all
PIO pins on either side of the pin (to the adjacent
corresponding pins), and divide the sum by two. The
resulting value should not exceed 40 mA for VCC or
60 mA for VSS.
Exclude the following pins from this calculation: 72
(VSS_A), 82 (VSS), 77 (VCC_A), and 79 (VCC).
For example, to calculate the PIO current for pin 83
(VSS), total the sustained sinking current for all PIO
pins between pin 71 (VSS) and pin 100 (VSS), and
divide the sum by two.
Am186™CH HDLC Microcontroller Data Sheet 37
ABSOLUTE MAXIMUM RATINGS1
Notes:
1. Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Parameter Symbol Minimum Maximum Unit
Temperature under bias: commercial TC2
2. T
C
= case temperature.
0100°C
Industrial TA3
3. T
A
= ambient temperature.
–40 +85 °C
Stora ge temperature — –65 +15 0 °C
Voltage on 5-V-tolera nt pins4 with respect to g round
4. 5-V-tolerant pins are indicated in Table 30, “Pin List Summary,” on page A-11.
—–0.5V
CC + 2.6 V
Voltage on other pins with respect to ground — –0.5 VCC + 0.5 V
Sustained current on any supply (VCC) pin5
5. See “PIO Supply Current Limit” on page 36.
—40—mA
Sustained PIO current on any ground (VSS) pin5—60—mA
OPERATING RANGES1
Notes:
1. Operating Ranges define those limits between which the functionality of the device is guaranteed.
Parameter Symbol Minimum Maximum Unit
Commercial TC2
2. T
C
= case temperature.
0100°C
Industrial TA3
3. T
A
= ambient temperature.
–40 + 85 °C
Supply voltage with respect to ground VCC 3.0 3.6 V
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATIN G RA NGES1
Notes:
1. Current out of pin is stated as a negative value.
Symbol Parameter Preliminary Unit
Minimum Maximum
VOH Output High voltage (IOH = –2.4 mA) 2.4 — V
VOH Output High voltage (IOH = –0.1 mA)2
2. Characterized but not tested.
VCC – 0.2 — V
VOL Output Low voltage (IOL = 4.0 m A) — 0.45 V
VIH5 5-V tolerant Input High voltage 2.0 VCC + 2.6 V
VIH Input High volta ge, except 5-V tolerant 2.0 VCC + 0.3 V
VIL Input Low voltage –0.3 0.8 V
ILI Input leakage current (0.1 V VOUT VCC)
(all pins exce pt those with inte rnal pullu p/pulldo wn resistors) —±10mA
ILO Output leakage current3 (0.1 V VOUT VCC)
3. This parameter is for three-state outputs wher e V
OUT
is driven on the three-state output.
—±15mA
PCC Power cons umption — 1.2 W
38 Am186™CH HDLC Microcontroller Data Sheet
MAXIMUM LOAD DERATING
All maximum delay numbers should be increased by
0.035 ns for every pF of load over the maximum load
(up to a maximum of 150 pF) specified in Table 30, “Pin
List Summary,” on page A-11.
POWER SUPPLY CURRENT
For the fol lowing typ ical sys tem spe cificat ion shown in
Figure 11, ICC has been measured at 6 mA per MHz of
system clock. The typical system is measured while the
system is executing code in a typical application with
nominal voltage and maximum case temperature.
Actual power supply current is dependent on system
design an d may be greater or less than th e typ ical ICC
fi gure presented here.
Typical current in Figure 11 is given by:
ICC = 6 mA ¼ freq(MHz)
Please note that dynamic ICC measurements are de-
pendent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the out-
puts. For these ICC measurements, the devices were
set to the following modes:
■No DC loads on the output buffers
■Output capacitive load set to 30 pF
■AD bus set to data only
■PIOs are disabled
■Timer, serial port, refresh, and DMA are enabled
Tabl e 7 shows t he values that are used to ca lcul ate t he
typical power consumption value for the Am186CH
HDLC microcontroller.
Figure 11. Typical Icc Versus Frequency
CAPACITANCE
Symbol Parameter Preliminary Unit
Minimum Maximum
CIN Input capac ita nc e —15pF
CCLK Clock capacitanc e — 15 pF
COUT Output capacitance — 20 pF
CI/O I/O pin capacitance — 20 pF
Table 7. Typical Power Consumption Calculation
MHz ¼ ICC ¼ Volts / 1000 = P Typical Power
in Watts
MHz Typical ICC Volts
25 6 3.3 0.495
40 6 3.3 0.792
50 6 3.3 0.99
Clock Frequency (MHz)
ICC (mA)
0
40
80
120
160
200
240
280
10 20 30 40 50
320
Am186™CH HDLC Microcontroller Data Sheet 39
THERMAL CHARACTERISTICS—PQFP PACKAGE
The Am186CH HDLC microcontroller is specified for
operation with case temperature ranges from 0C to
+100C for 3.3 V ± 0.3 V (commercial). Case
temperature is measured at the top center of the
package as shown in Figure 12. The various
temperatures and thermal resistances can be
determined using the equations in Figure 13 with
information given in Table 8.
The total thermal resistance is qJA; qJA is the sum of
qJC, the internal thermal resistance of the assembly,
and qCA, the case-to-ambient thermal resistance.
The variable P is power in wat ts. Power supply cu rren t
(ICC) is in mA per MHz of clock frequency.
Figure 12. Thermal Resistance( C/Watt)
Figure 13. Thermal Characteristics Equations
qJA qCA
qJC
qJA = qJC + qCA
TC
Table 8. Thermal Characteri stics ( C/Watt)
Package/Board
Airflow
(Linear Feet
per Minute) qJC qCA qJA
PQFP/2-Layer 0 fpm 7 38 45
200 fpm 7 32 39
400 fpm 7 28 35
600 fpm 7 26 33
PQFP/4-Layer
to 6-La yer 0 fpm 5 18 23
200 fpm 5 16 21
400 fpm 5 14 19
600 fpm 5 12 17
qJA = qJC + qCA
P = ICC ¼ freq (MHz) ¼
V
CC
TJ = TC+ (P ¼ qJC)
TJ = TA+ (P ¼ qJA)
TC = TJ – (P ¼ qJC)
TC = TA + (P ¼ qCA)
TA = TJ – (P ¼ qJA)
TA = TC – (P ¼ qCA)
40 Am186™CH HDLC Microcontroller Data Sheet
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to ind icate the spec ific per iods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. Whe n no bus cycle is pe nding, an idle (t i) state
occurs.
In the switching parameter descriptions, the
multiplexed
address is referred to as the AD address
bus; th e
demultiplexed
address is referr ed to as the A
address bus. Figure 14 defines symbols used in the
switching waveform diagrams.
Table 9 on page 41 contains an alphabetical listing of
the switching parameter symbols (grouped by
function), and Table 10 on page 44 contains a
numerical listing of the switching parameter symbols
(grouped by function).
Figure 14. Key to Switching Waveforms
Must be
Steady Will be
Steady
Will be changing
from H to L or
from H to three-
state
Will be changing
from L to H or
from L to three-
state
WAVEFORM INPUT OUTPUT
May change
from H to L or
from H to three-
state
May change
from L to H or
from L to three-
state
Am186™CH HDLC Microcontroller Data Sheet 41
Table 9. Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol No. Description
tARYCH 49 ARDY resolution transition setup time
tARYCHL 51 ARDY inactive holding time
tARYHDSH 951ARDY High to DS High
tARYHDV 891ARDY assert to data valid
tARYLCL 52 ARDY setup time
tARYLDSH 961ARDY Low to DS High
tAVBL 87 A address valid to WHB, WLB Low
tAVCH 14 AD address valid to clock High
tAVLL 12 AD address valid to ALE Low
tAVRL 66 A address valid to RD Low
tAVWL 65 A address valid to WR Low
tAZRL 24 AD address float to RD active
tCH1CH2 45 CLKOUT rise time
tCHAV 68 CLKOUT High to A address valid
tCHCAS 404 Change in CAS delay
tCHCK 38 X1 High time
tCHCL 44 CLKOUT High time
tCHCSV 67 CLKOUT High to LCS/UCS val id
tCHCSX 18 MCSx/PCSx inactiv e del ay
tCHCTV 22 Control active delay 2
tCHCV 64 Command lines valid delay (after float)
tCHCZ 63 Command lines float delay
tCHDX 8 Status hold time
tCHLH 9 ALE active delay
tCHLL 11 ALE inactive delay
tCHQS0V 55 Queue status 0 output delay
tCHQS1V 56 Queue status 1 output delay
tCHRAS 403 Change in RAS delay
tCHRFD 791CLKOUT High to RFSH valid
tCHSV 3 Status active delay
tCICO 69 X1 to CLKOUT skew
tCKHL 39 X1 fall time
tCKIN 36 X1 period
tCKLH 40 X1 rise time
tCL2CL1 46 CLKOUT fall time
tCLARX 50 ARDY active hold time
tCLAV 5 AD address and BHE valid delay
tCLAX 6 Address hold
tCLAZ 15 AD address float delay
tCLCH 43 CLKOUT Low time
tCLCK 37 X1 Low time
tCLCL 42 CLKOUT period
tCLCLX 801LCS inactive delay
42 Am186™CH HDLC Microcontroller Data Sheet
tCLCSL 811LCS active delay
tCLCSV 16 MCSx/PCSx active delay
tCLDOX 30 Data hold time
tCLDV 7 Data valid delay
tCLDX 2 Data in hold
tCLHAV 62 HLDA valid delay
tCLRF 821CLKOUT High to RFSH invalid
tCLRH 27 RD inactive delay
tCLRL 25 RD active delay
tCLRO 61 Reset delay
tCLSH 4 Status and BHE inactive delay
tCLSRY 48 SRDY transition hold time
tCLTMV 54 Timer output delay
tCOLV 402 Column address valid delay
tCSHARYL 881Chip select to ARDY Low
tCVCTV 20 Control active delay 1
tCVCTX 31 Control inactive delay
tCVDEX 21 DEN/DS inactive delay
tCXCSX 17 MCSx/PCSx hold from command inactive
tDSHDIR 921DS High to data invalid—read
tDSHDIW 981DS High to data invalid—write
tDSHDX 931DS High to data bus turn-off time
tDSHLH 41 DS inactive to ALE inactive
tDSLDD 901DS Low to data driven
tDSLDV 911DS Low to data valid
tDVCL 1 Data in setup
tDVDSL 971Data valid to DS Low
tDXDL 19 DEN/DS inactive to DT/R Low
tHVCL 58 HOLD setup
tINVCH 53 Peripheral setup time
tLCRF 861LCS inactive to RFSH active delay
tLHAV 23 ALE High to address valid
tLHLL 10 ALE width
tLLAX 13 AD address hold from ALE inactive
tLRLL 841LCS precharge pulse width
tRESIN 57 RES setup time
tRFCY 851RFSH cycle time
tRHAV 29 RD inactive to AD address ac tive
tRHDX 59 RD High to data hold on AD bus
tRHDZ 941RD High to data bus turn-off time
tRHLH 28 RD inactive to ALE High
tRLRH 26 RD pulse width
tSRYCL 47 SRDY transition setup time
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol No. Description
Am186™CH HDLC Microcontroller Data Sheet 43
tWHDEX 35 WR inactive to DEN inactive
tWHDX 34 Data hold after WR
tWHLH 33 WR inactive to ALE High
tWLWH 32 WR pulse width
DCE
tTCLKH 2 DCE cloc k High
tTCLKHD 6 DCE clock hold
tTCLKL 3 DCE clo ck Low
tTCLKO 4 DCE clock to output delay
tTCLKPER 1 DCE clock period
tTCLKR 7 DCE clock rise/fa ll
tTCLKSU 5 DCE clock setup
PCM (Slave)
tCLKP 1 PCM clo ck pe riod
tDCD 8 Delay time from CLK High to TXD valid
tDCLT 13 Delay fr om CLK Low of last bit to TSC invalid
tDCT 11 Delay to TSC valid from CLK
tDFT 12 Delay to TSC valid from FSC
tDTW 17 Delay from last bit CLK Low to TXD weak drive
tDZC 5 Delay time to valid TXD from CLK
tDZF 6 Delay time to valid TXD from FSC
tHCD 10 Hold time from CLK Low to RXD invalid
tHCF 4 Hold time from CLK Low to FSC va lid
tHFI 14 Hold time from CLK Low to FSC invalid
tSUDC 9 Setup time from RXD valid to CLK
tSUFC 7 Setup time for FSC High to CLK Low
tSYNSS 15 Time between successive synchronization pulses
tWH 2 PCM clock High
tWL 3 PCM clo ck Low
tWSYN 16 FSC width invalid
tDTZ 18 Delay from last bit CLK (plus one) High to TXD disable
PCM (Master)
tDCFH 1 Delay time from CLK High to FSC High
tDCFL 2 Delay time from CLK High to FSC Low
SSI
tCLEV 1 CLKO UT Low to SDEN valid
tCLSL 2 CLKOUT Low to SCLK Low
tDVSH 3 Data valid to SC LK High
tSHDX 4 SCLK High to data invalid
tSLDV 5 SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol No. Description
44 Am186™CH HDLC Microcontroller Data Sheet
Table 10. Numerical Key to Switching Parameter Symbols
No. Parameter
Symbol Description
1t
DVCL Data in setup
2t
CLDX D ata in hol d
3t
CHSV Status active dela y
4t
CLSH Statu s and BHE inactive delay
5t
CLAV AD address and BHE valid delay
6t
CLAX Address hold
7t
CLDV Data valid delay
8t
CHDX Status hold time
9t
CHLH ALE active delay
10 tLHLL ALE width
11 tCHLL ALE inactive delay
12 tAVLL AD address valid to ALE Low
13 tLLAX AD address hold from ALE inactive
14 tAVCH AD address valid to clock High
15 tCLAZ AD address float delay
16 tCLCSV MCSx/PCSx active delay
17 tCXCSX MCSx/PCSx hold from command inactive
18 tCHCSX MCSx/PCSx inactive delay
19 tDXDL DEN/DS inactive to DT/R Low
20 tCVCTV Control active delay 1
21 tCVDEX DEN/DS inactive delay
22 tCHCTV Control active delay 2
23 tLHAV ALE High to address valid
24 tAZRL AD address float to RD active
25 tCLRL RD active delay
26 tRLRH RD pulse width
27 tCLRH RD inactive delay
28 tRHLH RD inactive to ALE High
29 tRHAV RD inactive to AD address active
30 tCLDOX Data hold time
31 tCVCTX Control inactive delay
32 tWLWH WR pulse width
33 tWHLH WR inactive to ALE High
34 tWHDX Data hold after WR
35 tWHDEX WR inactive to DEN inactive
36 tCKIN X1 period
37 tCLCK X1 Low time
38 tCHCK X1 High time
39 tCKHL X1 fall time
40 tCKLH X1 rise time
41 tDSHLH DS inactive to ALE inactive
42 tCLCL CLKO UT period
43 tCLCH CLKOUT Low time
Am186™CH HDLC Microcontroller Data Sheet 45
44 tCHCL CLKOUT High time
45 tCH1CH2 CLKOUT rise time
46 tCL2CL1 CLKOUT fall time
47 tSRYCL SRDY transition setup tim e
48 tCLSRY SRDY transition hold time
49 tARYCH ARDY resolution transition setup time
50 tCLARX ARDY active hold tim e
51 tARYCHL ARDY inactive holding time
52 tARYLCL ARDY setup time
53 tINVCH Peripheral setup time
54 tCLTMV Timer ou tput delay
55 tCHQS0V Queue status 0 output delay
56 tCHQS1V Queue status 1 output delay
57 tRESIN RES setup time
58 tHVCL HOLD setup
59 tRHDX RD High to data hold on AD bus
61 tCLRO Reset delay
62 tCLHAV HLDA valid delay
63 tCHCZ Co mmand lines float delay
64 tCHCV Command lines valid delay (after float)
65 tAVWL A address valid to WR Low
66 tAVRL A address valid to RD Low
67 tCHCSV CLKOUT High to LCS/UCS valid
68 tCHAV CLKOUT High to A address valid
69 tCICO X1 to CLKOUT skew
791tCHRFD CLKOUT High to RFSH valid
801tCLCLX LCS inactive delay
811tCLCSL LCS active delay
821tCLRF CLKOUT High to RFSH invalid
841tLRLL LCS precharge pulse width
851tRFCY RFSH cycle time
861tLCRF LCS inactive to RFSH active delay
87 tAVBL A address valid to WHB, WLB Low
881tCSHARYL Chip select to ARDY Low
891tARYHDV ARDY assert to data valid
901tDSLDD DS Low to data driven
911tDSLDV DS Low to data valid
921tDSHDIR DS High to data invalid—read
931tDSHDX DS High to data bus turn-off time
941tRHDZ RD High to data bus turn-off time
951tARYHDSH ARDY High to DS High
961tARYLDSH ARDY Low to DS High
971tDVDSL Data valid to DS Low
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
No. Parameter
Symbol Description
46 Am186™CH HDLC Microcontroller Data Sheet
981tDSHDIW DS High to data invalid—write
402 tCOLV Column address valid delay
403 tCHRAS Change in RAS delay
404 tCHCAS Change in CAS delay
DCE
1t
TCLKPER DCE clock period
2t
TCLKH DCE clock High
3t
TCLKL DCE clock Low
4t
TCLKO DCE clock to output delay
5t
TCLKSU DCE clock setup
6t
TCLKHD DCE clock hold
7t
TCLKR DCE clock rise/ fall
PCM (Slave)
1t
CLKP PCM clock pe riod
2t
WH PCM clock High
3t
WL PCM clock Low
4t
HCF Hold time from CLK Low to FSC valid
5t
DZC Delay time to valid TXD from CLK
6t
DZF Delay time to valid TXD from FSC
7t
SUFC Setup time for FSC High to CLK Low
8t
DCD Delay time from CLK High to TXD valid
9t
SUDC Setup time from RXD valid to CLK
10 tHCD Hold time from CLK Low to RXD invalid
11 tDCT Delay to TSC valid from CLK
12 tDFT Delay to TSC valid from FSC
13 tDCLT Delay from CLK Low of last bit to TSC invalid
14 tHFI Hold time from CLK Low to FSC invalid
15 tSYNSS Time between successive synchronization pulses
16 tWSYN FSC width invalid
17 tDTW Delay from last bit CLK Low to TXD weak drive
18 tDTZ Delay from last bit CLK (plus one) High to TXD disable
PCM (Master)
tDCFH 1 Delay time from CLK High to FSC High
tDCFL 2 Delay time from CLK High to FSC Low
SSI
1t
CLEV CLKOUT Low to SDEN valid
2t
CLSL CLKOUT Low to SCLK Low
3t
DVSH Data valid to SCLK High
4t
SHDX SCLK High to data invalid
5t
SLDV SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
No. Parameter
Symbol Description
Am186™CH HDLC Microcontroller Data Sheet 47
Switching Characteristics over Commercial and Industrial Operating Ranges
In this section, the following timings and timing
waveforms are shown:
■Read (page 47)
■Write (page 50)
■Software halt (page 53)
■Peripheral (page 54)
■Reset (page 55)
■External ready (page 57)
■Bus hold (pag e 5 9)
■System clocks (page 61)
■PCM highway (slave) (page 62)
■DCE interface (page 65)
■SSI (page 66)
■DRAM (page 67)
Table 11. Read Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
General Timing Requirements
1t
DVCL Data in setup 10 —5—5—ns
2t
CLDX Data in hold23—2—2—ns
General Timing Responses
3t
CHSV Status active delay 0 20 0 12 0 10 ns
4t
CLSH Status and BHE
inactive delay 020012010ns
5t
CLAV AD address and
BHE valid delay 020012010ns
6t
CLAX Address hold 0 — 0 — 0 — ns
8t
CHDX Status hold time 0 — 0 — 0 — ns
9t
CHLH ALE active delay — 20 — 12 — 10 ns
10 tLHLL ALE width tCLCL–10=30 — tCLCL–5=20 — tCLCL–5=15 — ns
11 tCHLL ALE inactive delay — 20 — 12 — 10 ns
12 tAVLL AD address valid to
ALE Low30.5 • tCLCH — 0.5 • tCLCH — 0.5 • tCLCH —ns
13 tLLAX AD address hold
from ALE inactive3tCHCL —t
CHCL —t
CHCL —ns
14 tAVCH AD address valid to
clock High 0—0—0—ns
15 tCLAZ AD address float
delay tCLAX=0 20 tCLAX=0 12 tCLAX=0 10 ns
16 tCLCSV MCSx/PCSx active
delay 020012010ns
17 tCXCSX MCSx/PCSx hold
from command
inactive
tCLCH —t
CLCH —t
CLCH —ns
18 tCHCSX MCSx/PCSx
inactive delay 020012010ns
19 tDXDL DEN/DS inactiv e to
DT/R Low3, 4 –1 — –1 — –1 — ns
20 tCVCTV Control active
delay 1 020012010ns
48 Am186™CH HDLC Microcontroller Data Sheet
21 tCVDEX DEN/DS inactive
delay4020012010ns
22 tCHCTV Control active
delay 2 020012010ns
23 tLHAV ALE High to
address valid 15 —7.5— 5 —ns
Read Cycle Timing Responses
24 tAZRL AD addres s float to
RD active 0—0—0—ns
25 tCLRL RD active delay 020010010ns
26 tRLRH RD pulse width 2tCLCL–15=65 — 2tCLCL–10=40 — 2tCLCL–10=30 — ns
27 tCLRH RD inactive delay020012010ns
28 tRHLH RD inactiv e to ALE
High3tCLCH–3 — tCLCH–2 — tCLCH–2 — ns
29 tRHAV RD inactive to AD
address active 3tCLCL–10=30 — tCLCL–5=20 — tCLCL–5=15 — ns
59 tRHDX RD High to data
hold on AD Bus23—2—0—ns
66 tAVRL A address valid to
RD Low 1.5tCLCL–15=45 — 1.5tCLCL–10=
27.5 —1.5t
CLCL–10=20 — ns
67 tCHCSV CLKOUT High to
LCS/UCS valid 020010010ns
68 tCHAV CLK OUT High to A
address valid 020010010ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly.
3. Testing is performed with equal loading on referenced pins.
4. The timing of this s ignal is the same for a read cycle, whether it is configured to be DEN or DS.
Table 11. Read Cycle Timing1 (Continued)
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
Am186™CH HDLC Microcontroller Data Sheet 49
Figure 15. Read Cycle Waveforms
T4 T1 T2 T3 T4
1
2
14
12
13
24 59 29
1010 28
2626 17
19
68
38
5
15
911
25 27
67
16 18
20 21
22 22
3 4
Addr. Data
CLKOUT
A19–A0
S61
AD15–AD0
ALE
RD
BHE
LCS, UCS
MCS3–MCS0,
DEN, DS
DT/R
S2–S0
6
23
4
5
tw
66
PCS7–PCS0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t
CHSV
)) is met.
50 Am186™CH HDLC Microcontroller Data Sheet
Table 12. W rite Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
General Timing Responses
3t
CHSV Status active delay 0 20 0 12 0 10 ns
4t
CLSH Status and BHE
inactive delay 020012010ns
5t
CLAV AD address and
BHE valid delay 020012010ns
6t
CLAX Address hold 0 —0—0—ns
7t
CLDV Data v alid delay 0 20 0 12 0 10 ns
8t
CHDX Status hold time 0 — 0 — 0 ns
9t
CHLH ALE active delay — 20 — 12 — 10 n s
10 tLHLL ALE width tCLCL – 10 = 30 — tCLCL – 5 = 20 — tCLCL – 5 = 15 — ns
11 tCHLL ALE inactive delay — 20 — 12 — 10 ns
12 tAVLL AD address valid
to ALE Low20.5 • tCLCH —0.5 • t
CLCH — 0.5 • tCLCH —ns
13 tLLAX AD address hold
from ALE inactive tCHCL —t
CHCL —t
CHCL —ns
14 tAVCH AD address valid
to clock High 0—0—0—ns
16 tCLCSV MCSx/PCSx active
delay 020012010ns
17 tCXCSX MCSx/PCSx hold
from command
inactive
tCLCH —t
CLCH —t
CLCH —ns
18 tCHCSX MCSx/PCSx
inactive delay 020012010ns
19 tDXDL DEN inactive to
DT/R2, 3 –1 — –1 — –1 — ns
20 tCVCTV Control active
delay 13,4 020012010ns
21 tCVDEX DS inactive
delay3,4 020012010ns
23 tLHAV ALE High to
address valid 15 — 7.5 — 5 — ns
Am186™CH HDLC Microcontroller Data Sheet 51
Wri te Cycle Timing Respo n se s
30 tCLDOX Data hold time 0 —0—0—ns
31 tCVCTX Control inactive
delay3,4 020012010ns
32 tWLWH WR pulse width 2tCLCL – 10 = 70 — 2tCLCL – 10 = 40 — 2tCLCL – 10 = 30 — ns
33 tWHLH WR inactive to ALE
High2tCLCH – 2 — tCLCH – 2 — tCLCH – 2 — ns
34 tWHDX Data hold after WR2tCLCL – 10 = 30 — tCLCL – 10 = 15 — tCLCL – 10 = 10 — ns
35 tWHDEX WR inactive to
DEN inactive2,3 tCLCH – 3 — tCLCH —t
CLCH —ns
65 tAVWL A address valid to
WR Low tCLCL + tCHCL –3 — tCLCL + tCHCL –
1.25 —t
CLCL + tCHCL –
1.25 —ns
67 tCHCSV CLKOUT High to
LCS/UCS valid 020010010ns
68 tCHAV CLKOUT High to A
address valid 020010010ns
87 tAVBL A address valid to
WHB, WLB Low tCHCL – 3 20 tCHCL – 1.25 12 tCHCL – 1.25 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. The timing of this signal is different during a write cycle depending on whether it is configured to be DEN or DS.
4. This parameter applies to the DEN, DS, WR, WHB, and WLB signals.
Table 12. Write Cycle Timing1 (Continued)
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
52 Am186™CH HDLC Microcontroller Data Sheet
Figure 16. Write Cycle Waveforms
T4 T1 T2 T3 T4
14
87
12 13 34
10 33
32
35
17
19
68
38
5
7
30
911
20
31
20 31
67
16 18
31
34
Addr. Data
CLKOUT
A19–A0
S61
AD15–AD0
ALE
WR
WHB, WLB
BHE
LCS, UCS
MCS3–MCS0,
DEN
DT/R
S2–S0
23
6
tw
5
20
20
31
20 21
DS
65
4
PCS7–PCS0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t
CHSV
)) is met.
Am186™CH HDLC Microcontroller Data Sheet 53
Figure 17. Software Halt Cycle W aveforms
Table 13. Software Halt Cycle Timing1
Parameter Preliminary Unit
25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
3t
CHSV Status active delay 0 20 0 12 0 10 ns
4t
CLSH Status inactive
delay 020012010ns
5t
CLAV AD address invalid
delay 020012010ns
9t
CHLH ALE activ e delay —20—12—10ns
10 tLHLL ALE width tCLCL – 10 = 30 — tCLCL – 5 = 20 — tCLCL – 5 = 15 — ns
11 tCHLL ALE inactive delay — 20 — 12 — 10 ns
19 tDXDL DEN inactive to
DT/R Low2–1 — –1 — –1 ns
22 tCHCTV Control active
delay 23020012010ns
68 tCHAV CLK OUT High to A
address invalid 020012010ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. This parameter applies to the DEN/DS signal.
T4 T1 T2 TI TI
10
19
68
5
911
22
34
Invalid Addre ss
Invalid Addre ss
CLKOUT
A19–A0
S6, AD15–AD0
ALE
DEN, DS
DT/R
S2–S0
54 Am186™CH HDLC Microcontroller Data Sheet
Figure 18. Peripheral Timing Waveforms
Table 14. Peripheral Timing1, 2
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
53 tINVCH Peripheral setup time 10 —5— 5 — ns
54 tCLTMV Timer output delay — 25 — 15 — 12 ns
55 tCHQS0V Queue status 0 output delay — 25 — 15 — 12 ns
56 tCHQS1V Queue status 1 output delay — 25 — 15 — 12 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. PIO ou tputs cha nge anywhere from the be gin nin g o f T3 to the first half of T4 of the bus c yc le in w h ic h th e PIO d ata regi ster is
written.
53 54 55
CLKOUT
INT8–INT0, NMI, TMRINx
DRQ0, DRQ1
TMROUT
QS0
QS1
56
Am186™CH HDLC Microcontroller Data Sheet 55
Figure 19. Reset Waveforms
Table 15. Reset Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
57 tRESIN RES setup time 10 —5— 5 —ns
61 tCLRO Reset delay — 18 — 15 — 12 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
61
RES
CLKOUT
RESOUT
Notes:
1. RES must be held Low for 1 ms during power-up to ensure proper device initialization.
2. Diagram is shown for the system PLL in its 2x mode of operation.
3. Diagram assumes that V
CC
is stable (i.e., 3.3 V ± 0.3 V) during the 1-ms RES active time.
57
56 Am186™CH HDLC Microcontroller Data Sheet
Figure 20. Signals Related to Reset (System PLL in 1x or 2x Mode)
Figure 21. Signals Related to Reset (System PLL in 4x Mode)
RES
CLKOUT
RESOUT
AD15–AD01
All Other
Outputs
All Pinstrap
Pins1,2
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-7 for a list of all the pinstraps.
RES
CLKOUT
RESOUT
AD15–AD01
All Other
Outputs
All Pinstrap
Pins1,2
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-7 for a list of all the pinstraps.
Am186™CH HDLC Microcontroller Data Sheet 57
Figure 22. Synchronous Ready Waveforms
Table 16. External Ready Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commerc i al On ly)
No. Symbol Description Min Max Min Max Min Max
Ready Timing Requirements
47 tSRYCL SRDY transition setup tim e 210 —5— 5 — ns
48 tCLSRY SRDY transition hold time23—2— 2 — ns
49 tARYCH ARDY resolution transition setup time310 — 5 — 5 — ns
50 tCLARX ARDY active hold tim e24—3— 3 — ns
51 tARYCHL ARDY inactive holding time 10 — 5 — 5 — ns
52 tARYLCL ARDY setup time215 — 5 — 5 — ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. This timing must be met to guarantee proper operation.
3. This timing must be met to guarantee recognition at the clock edge.
T1 T2 T3 Tw T4
47
48
Tw
T3
T2
Tw
Tw
T3
Tw
Tw
Tw
T4
T4
T4
CLKOUT
SRDY
Case 11
Case 21
Case 31
Case 42
Case 51T1 T2 T3 T4
Notes:
1. Normally not ready system
2. Normally ready system
Note 2
Note 1
58 Am186™CH HDLC Microcontroller Data Sheet
Figure 23. Asynchronous Ready Waveforms
49
51
50
50
CLKOUT
ARDY1
ARDY2
49
(Normally Not-Ready System)
(Normally Ready System)
52
Notes:
1. In a normally not ready system, wait states are added after T3 until t
ARYCH
(49) and t
CLARX
(50) are met.
2. In a normally ready system, a wait state is added if t
ARYCH
(49) and t
ARYCHL
(51) during T2 or t
ARYLCL
(52)
and t
CLARX
(50) during T3 are met.
T1
Tw
T3
T2
T1
Case 11
Case 21
Case 31
Case 42
Case 51
T2 T3 Tw T4
Tw
Tw
T3
Tw
Tw
Tw
T4
T4
T4
T2 T3 T4
Am186™CH HDLC Microcontroller Data Sheet 59
Figure 24. Entering Bus Hold Waveforms
Table 17. Bus Hold Ti ming1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
5t
CLAV AD addres s valid del ay 0 20 0 12 0 10 ns
15 tCLAZ AD address float delay 0 20 0 12 0 10 ns
18 tCHCSX MCSx/PCSx inactive delay 0 20 0 12 0 10 ns
58 tHVCL HOLD setup210 —5— 5 — ns
62 tCLHAV HLDA valid delay 0 20 0 12 0 10 ns
63 tCHCZ Command lines float delay — 20 — 12 — 10 ns
64 tCHCV Command lines valid delay (after float) — 25 — 12 — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. This timing must be met to guarantee recognition at the next clock.
T4 Ti Ti
58
62
15
63
Ti Ti Ti
CLKOUT
HOLD
HLDA
AD15–AD0, DEN
Case 1
Case 2
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, WHB ,
WLB, UCS, LCS, ALE
MCS3–MCS0, PCS7–PCS0
18
60 Am186™CH HDLC Microcontroller Data Sheet
Figure 25. Exiting Bus Hold Waveforms
Ti Ti T4 T1
58
62
5
64
Ti Ti Ti T1
CLKOUT
HOLD
HLDA
AD15–AD0, DEN
MCS3–MCS0, PCS7–PCS0
Case 1
Case 2
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, W HB,
WLB, UCS, LCS, ALE
Am186™CH HDLC Microcontroller Data Sheet 61
Table 18. System Clocks Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
CLKIN Requirements for 4x PLL Mode
36 tCKIN X1 period2Not Supported 100 125 80 125 ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 45 —35—ns
38 tCHCK X1 High time (1.5 V) 45 — 35 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5ns
CLKIN Requirements for 2x PLL Mode
36 tCKIN X1 period280 125 50 125 40 125 ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 35 — 20 — 15 — ns
38 tCHCK X1 High time (1.5 V) 35 — 20 — 15 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5—5ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5—5ns
CLKIN Requirements for 1x PLL Mode
36 tCKIN X1 period240 60 25 60 Not Supported ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 15 — 7.5 — ns
38 tCHCK X1 High time (1.5 V) 15 — 7.5 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5 ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5 ns
CLKOUT Timing3
42 tCLCL CLKOUT period 40 — 25 — 20 — ns
43 tCLCH CLKOUT Low time
(CL = 50 pF) 0.5tCLCL–2 =18 — 0.5tCLCL–1 .25
=11.25 —0.5t
CLCL–1 = 9 — ns
44 tCHCL CLKOUT High time
(CL = 50 pF) 0.5tCLCL–2 =18 — 0.5 tCLCL–1.25
=11.25 —0.5t
CLCL–1 = 9 — ns
45 tCH1CH2 CLKOUT rise time
(1.0 to 3.5 V) —3—3—3ns
46 tCL2CL1 CLKOUT fall time
(3.5 to 1.0 V) —3—3—3ns
69 tCICO X1 to CLK OUT s ke w — 10 — 10 — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Testing is performed with equal loading on referenced pins.
3. The PLL req uire s a maxi mum of 1 ms to achi eve lock aft er all othe r opera tin g condi tio ns (V
CC
) are stable, which is normally
achieved by holding RES active for at least 1 ms.
62 Am186™CH HDLC Microcontroller Data Sheet
Figure 26. System Clocks Waveforms—Active Mode (PLL 1x Mode)
Table 19. PCM Highway Timing (Timing Slave)1, 2
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. TXD becomes valid after the CLK rising edge or FSC enable, whichever is later.
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
CLKP PCM clock period 200 —ns
2t
WH PCM c lock High 80 — ns
3t
WL PCM clock Low 80 — ns
4t
HCF Hold time from CLK Low to FSC valid 0 — ns
5t
DZC Delay time to valid TXD from CLK 1 25 ns
6t
DZF Delay time to valid TXD from FSC 1 25 ns
7t
SUFC Setup time for FSC High to CLK Low 35 — ns
8t
DCD Delay time from CLK High to TXD valid 1 25 ns
9t
SUDC Setup time from RXD va lid to CLK 35 — ns
10 tHCD Hold time from CLK Low to RXD invalid 5 — ns
11 tDCT Delay to TSC valid from CLK 1 25 ns
12 tDFT Delay to TSC valid from FSC 1 25 ns
13 tDCLT Delay from CLK Low of last bit to TSC invalid 1 25 ns
14 tHFI Hold time from CLK Low to FSC invalid 0 — ns
15 tSYNSS Time between successive synchronization pulses 16 — CLK
16 tWSYN FSC width invalid 8 — CLK
17 tDTW3
3. During the second half of the last bit transmittal, TXD is driven weak so that other devices can safely drive during this time.
Delay from last bit CLK Low to TXD weak drive 1 25 ns
18 tDTZ Delay from last bit CLK (plus 1) High to TXD disable 1 25 ns
36 37
40
42 44
45
69
38
43
46
X2
X1
CLKOUT
39
Am186™CH HDLC Microcontroller Data Sheet 63
Figure 27. PCM Highway Waveforms (Timing Slave)
4
PCM_CLK_x
PCM_FSC_x
PCM_TXD_x
789
PCM_RXD_x
PCM_TSC_x
23
1
10
11 12
15 16
17
12 34n
13
5 14
618
n+1
Notes:
The PCM_TXD_x outputs three-state. In the signal description and pin list summary tables, PCM_TXD_x is listed as
O-LS-OD (totem pole output/programmable to hold last state of pin/open drain output) because of the following design characteristic:
On the last bit to be transmitted in PCM Highway mode, PCM_TXD_x will be driven normally during the first 1/2 bit time. During
the last 1/2 bit time of the last bit of the transmission, PCM_TXD_x control will be in the hold-last-state condition (LS). In this
condition, the output is driven, but at a much weaker strength. This permits another device (external to the microcontroller) to
start driving during this time without bus content ion problems. After this 1/ 2 bit time of hold-last-state condition, the PCM_TXD_x
pin will be fully three-stated.
In some applications, several PCM Highway devices may have their PCM_TXD pins tied together. The time slot assigners
should be programmed so that only one device is active at any time.
The PCM_TSC_x signal permits external bus drivers, possibly to go external to the board. Each PCM_TSC_x signal is open-
drain so that mu ltiple PCM_TSC_ x pins can be conne cted together . For examp le, two Am186CH mic rocontrollers coul d be co n-
nected on the same PCM Highw ay and (wi th pro per c onfi gu r ati on of th e tim e sl ot as si gners) coul d oc cup y di fferent time slot s.
An external bus driver w ould ne ed to be activ e for both Am 186CH tim e slots . The open drain on th e PCM_TSC_x pins permi ts
them to be wired together to achieve this.
64 Am186™CH HDLC Microcontroller Data Sheet
Figure 28. PCM Highway Waveforms (Timing Master)
Table 20. PCM Highway Timing (Timing Master)1
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted . All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
DCFH Delay time from CLK High to FSC High 0 30 ns
2t
DCFL Delay time from CLK High to FSC Low 0 30 ns
PCM_CLK_x
PCM_FSC_x
12
Am186™CH HDLC Microcontroller Data Sheet 65
Figure 29. DCE Transmit Waveforms
Figure 30. DCE Receive Waveforms
Table 21 . DCE Interface Timing 1, 2
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
TCLKPER DCE clock period 95 —ns
2t
TCLKH DCE clock High 40 — ns
3t
TCLKL D CE clock Low 40 — ns
4t
TCLKO DCE clock to output delay 1 20 ns
5t
TCLKSU DCE clock set up 15 — ns
6t
TCLKHD DCE clock hold 5 — ns
7t
TCLKR DCE clock rise/fall — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
2. Timings are shown with TCLK and RCLK in the default mode without the optional clock inversion.
DCE_CTS_x
3
12
4 4
5
DCE_TCLK_x
DCE_TXD_x
7 7
6
1 2 3
5 5
4 4
DCE_RCLK_x
DCE_RXD_x
DCE_RTR_x
7 7
6
66 Am186™CH HDLC Microcontroller Data Sheet
Figure 31. SSI Wavef or ms
Table 22. SSI Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
1t
CLEV CLKOUT Low to SDEN valid 0 20 0 12 0 10 ns
2t
CLSL CLKOUT Low to SCLK Low 0 20 0 15 0 12 ns
3t
DVSH Data valid to SCLK High 10 —5— 5 — ns
4t
SHDX SCLK High to data invalid 3 — 2 — 2 — ns
5t
SLDV SCLK Low to data valid — 20 — 12 — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
1
223
4
5
CLKOUT
SDEN
SCLK
SDATA (RX)
SDATA (TX)
Notes:
1. SDEN is configured to be active High.
2. SCLK is configured to be CLKOUT/2.
3. Waveforms are shown for “normal” clock mode (i.e., transmit on negative edge of SCLK and receive on positive edge
of SCLK).
Am186™CH HDLC Microcontroller Data Sheet 67
Table 23. DRAM T i ming1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commerc i al On ly)
No. Symbol Description Min Max Min Max Min Max
1t
DVCL Data in setup 10 —5— 5 — ns
2t
CLDX Data in hold 3 — 2 — 2 — ns
5t
CLAV AD address valid delay 0 20 0 12 0 10 ns
7t
CLDV Data valid delay 0 20 0 12 0 10 ns
15 tCLAZ AD address float delay 0 20 0 12 0 10 ns
20 tCVCTV Control active delay 1 0 20 0 12 0 10 ns
25 tCLRL RD active delay 0 20 0 12 0 10 ns
27 tCLRH RD inactive d elay 0 20 0 12 0 10 ns
30 tCLDOX Data hold time 0 — 0 — 0 — ns
31 tCVCTX Control in active delay 0 20 0 12 0 10 ns
68 tCHAV CLKOUT High to A address valid 0 20 0 12 0 10 ns
402 tCOLV Column address valid delay 0 20 0 12 0 10 ns
403 tCHRAS Change in RAS delay 3 20 3 12 3 10 ns
404 tCHCAS Change in CAS delay 3 20 3 12 3 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 30, “Pin List Summary,” on page A-11.
68 Am186™CH HDLC Microcontroller Data Sheet
Figure 32. DRAM Read Cycle without Wait States Waveform
Figure 33. DRAM Read Cycle with Wait States Waveform
T4 T1 T2 T3 T4
1
2
515
68 402
403 403
404 404
25 27
Data
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
RD
Column
A9, A7, A5, A3, A1
T4 T1 T2 TW T3 T4
1
2
515
68 402
403 403
404 404
25 27
DATA
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, RAS1
RD
Column
A9, A7, A5, A3, A1
Am186™CH HDLC Microcontroller Data Sheet 69
Figure 34. DRAM Write Cycle without Wait States Waveform
Figure 35. DRAM Write Cycle with Wait States Waveform
T4 T1 T2 T3 T4
5 7 30
68 402
403 403
404 404
20 31
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
WR
Column
Data
A9, A7, A5, A3, A1
30
T4 T1 T2 TW T3 T4
5 7
68 402
403 403
404 404
20 31
Data
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
WR
Column
A9, A7, A5, A3, A1
70 Am186™CH HDLC Microcontroller Data Sheet
Figure 36. DRAM Refresh Cycle Wave form
T4 T1 T2 TW1 TW2 TW3 T3 T4
515
68 402
403403
404 404
25 27
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
RD
403403
Column (Invalid)Row (Invalid)
A9, A7, A5, A3, A1
Am186™CH HDLC Microcontroller Data Sheet A-1
APPENDIX A—PIN TABLES
This appendix contains pin tables for the Am186CH
HDLC microcontroller. Several different tables are
included with the following characteristics:
■Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 24 on
page A-2.
■Multiplexed signal trade-offs—Table 25 on
page A-5.
■Pinstraps and pinstrap options—Table 26 on
page A-7.
■Programmable I/O pins ordered by PIO pin number
and multiple xed signal name, respectively, including
pin numbers, multiplexed functions, and pin
configura tions foll owing sy stem res et—Table 27 on
page A-8 and Table 28 on page A-9.
■Pin and si gnal summar y showing signal name an d
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage column—
Table 30 on page A-11.
For pin t ables showing pins sorted by pin number an d
signal name, respectively, see Table 1, “PQFP Pin
Assignments—Sorted by Pin Number” on page 10 and
Table 2, “PQFP Pin Assignments—Sorted by Signal
Name” on page 11.
For signal descriptions, see Table 4, “Signal
Descriptions” on page 13.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
A-2 Am186™CH HDLC Microcontroller Data Sheet
Table 24. Power-On Reset (POR) Pin Defaults1
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
Bus Interface U nit
A0 30 —————
A1 31—————
A2 32—————
A3 36—————
A4 37—————
A5 42—————
A6 43—————
A7 44—————
A8 45—————
A9 49—————
A10 50—————
A11 64—————
A12 65—————
A13 69—————
A14 70—————
A15 84—————
A16 85—————
A17 88—————
A18 89—————
A19 90—————
AD0 28—————
AD1 34—————
AD2 38—————
AD3 46—————
AD4 51—————
AD5 66—————
AD6 86—————
AD7 92—————
AD8 29—————
AD9 35—————
AD1039—————
AD1147—————
AD1252—————
AD1367—————
AD1487—————
AD1593—————
ALE 19 — — — PIO33 —
ARDY 14 — — — PIO8 —
BHE 20 — — — PIO34 {ADEN}
BSIZE8 94—————
DEN 18 DS ——PIO30—
DRQ1105—————
DT/R 17 — — — PIO29 —
HLDA98—————
HOLD 99 — — — — {CLKSEL1}
RD 97—————
S0 57—————
S1 56—————
S2 55—————
Am186™CH HDLC Microcontroller Data Sheet A-3
S6 54 —————
SRDY 15 — — — PIO35 —
WHB 95—————
WLB 96—————
WR 16 — — — PIO15 —
Chip Selects —
LCS 131 RAS0 ————
MCS1 127 CAS1 ————
MCS2 128 CAS0 ————
PCS0 5— — — PIO13 —
PCS1 6— — — PIO14 —
PCS2 7—————
PCS3 8—————
UCS 132 — — — — {ONCE}
Reset/Clocks
CLKOUT60—————
RES 114—————
RESOUT58—————
X1 73—————
X2 74—————
Interrupts
INT0 107 — — — — —
INT1 109 — — — — —
INT2 110 — — — — —
INT3 111 — — — — —
INT4 112 — — — — —
INT5 113 — — — — —
NMI 115—————
Synchronous Communications Interfaces
Channel A (DCE)
DCE_RXD_A 118 PCM_RXD_A — — — —
DCE_TXD_A 119 PCM_TXD_A — — — —
DCE_RCLK_A 117 PCM_CLK_A — — — —
DCE_TCLK_A 116 PCM_FSC_A — — — —
High-Speed UART
TXD_HU26—————
Debug Support
QS0 62—————
QS1 63—————
PIOs
PIO0 144 TMRIN1 — — —
PIO1 143 TMROUT1 — — —
PIO2 10 PCS5 —— —
PIO3 9 PCS4 —— {CLKSEL2}
PIO4 126 MCS0 —— {UCSX8}
PIO5 129 MCS3 RAS1 — —
PIO6 147 INT8 PWD — —
PIO7 146 INT7 — — —
PIO9 124 DRQ0 — — —
PIO10 2 SDEN — — —
Table 24. Power-On Reset (POR) Pin Defaults1 (Continued)
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
A-4 Am186™CH HDLC Microcontroller Data Sheet
PIO11 3 SCLK —— —
PIO12 4 SDATA — — —
PIO16 25 RXD_HU — — —
PIO17 123 DCE_CTS_A PCM_TSC_A — —
PIO18 122 DCE_RTR_A —— —
PIO19 145 INT6 — — —
PIO20 159 TXD_U — — —
PIO21 22 UCLK — — —
PIO22 150 — — — —
PIO23 149 — — — —
PIO24 157 CTS_U —— —
PIO25 156 RTR_U —— —
PIO26 158 RXD_U — — —
PIO27 142 TMRIN0 — — —
PIO28 141 TMROUT0 — — —
PIO31 13 PCS7 —— —
PIO32 11 PCS6 —— —
PIO36 138 DCE_RXD_B PCM_RXD_B — —
PIO37 139 DCE_TXD_B PCM_TXD_B — —
PIO38 137 DCE_CTS_B PCM_TSC_B — —
PIO39 136 DCE_RTR_B —— —
PIO40 135 DCE_RCLK_B PCM_CLK_B — —
PIO41 134 DCE_TCLK_B PCM_FSC_B — —
PIO42 153 — — — —
PIO43 154 — — — —
PIO44 152 — — — —
PIO45 151 — — — —
PIO46 24 CTS_HU —— —
PIO47 23 RTR_HU —— —
Reserved
RSVD_104 104 — — — — —
RSVD_103 103 — — — — —
RSVD_102 102 — — — — —
RSVD_101 101 — — — — —
RSVD_81 81 — — — — —
RSVD_80 80 — — — — —
RSVD_76 76 — — — — —
RSVD_75 75 — — — — —
Notes:
1. For default reset functions and pin states refer to Table 30, “Pin List Summary,” on page A-11.
Table 24. Power-On Reset (POR) Pin Defaults1 (Continued)
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
Am186™CH HDLC Microcontroller Data Sheet A-5
Table 25. Multiplexed Signal Trade-Offs
DESIRED FUNCTION LOST FUNCTION
Interface Name Pin Interface Name Interface Name Interface Name Interface Name
Memory
SRAM LCS 131 DRAM RAS0 ————PIO—
MCS1 127 CAS1 ———— —
MCS2 128 CAS0 ———— —
MCS3 129 RAS1 ———— PIO5
DRAM
CAS0 128 SRAM MCS2 ——————
CAS1 127 MCS1 ——————
RAS0 131 LCS ——————
RAS1 129 MCS3 —————
PIO5
Synchronous Communications Interfaces
DCE
Channel
A
DCE_RXD_A 118 P CM
Channel
A
PCM_RXD_A — —
—
—PIO —
DCE_TXD_A 119 PCM_TXD_A — — — —
DCE_RCLK_A 117 PCM_CLK_A — — — —
DCE_TCLK_A 116 PCM_FSC_A — — — —
DCE_CTS_A 123 PCM_TSC_A —— — PIO17
DCE_RTR_A 122 — — — — PIO18
DCE
Channel
B
DCE_RXD_B 138 P CM
Channel
B
PCM_RXD_B — — — — PIO PIO36
DCE_TXD_B 139 PCM_TXD_B — — — — PIO37
DCE_RCLK_B 135 PCM_CLK_B — — — — PIO40
DCE_TCLK_B 134 PCM_FSC_B — — — — PIO41
DCE_CTS_B 137 PCM_TSC_B ———— PIO38
DCE_RTR_B 136 — — — — — PIO39
PCM
Channel
A
PCM_RXD_A 118 DCE
Channel
A
DCE_RXD_A — —
—
—PIO —
PCM_TXD_A 119 DCE_TXD_A — — — —
PCM_CLK_A 117 DCE_RCLK_A — — — —
PCM_FSC_A 116 DCE_TCLK_A — — — —
PCM_TSC_A 123 DCE_CTS_A —— — PIO17
PCM
Channel
B
PCM_RXD_B 138 DCE
Channel
B
DCE_RXD_B — — — — PIO PIO36
PCM_TXD_B 139 DCE_TXD_B — — — — PIO37
PCM_CLK_B 135 DCE_RCLK_B — — — — PIO40
PCM_FSC_B 134 DCE_TCLK_B — — — — PIO41
PCM_TSC_B 137 DCE_CTS_B ———— PIO38
Low-
Speed
UART
RXD_U 158 — — — — — — PIO PIO26
TXD_U 159 — — — — — — PIO20
RTR_U 156 — — — — — — PIO25
CTS_U 157 — — — — — — PIO24
High-
Speed
UART
RXD_HU 25 — — — — — — PIO PIO16
RTR_HU 23 — — — — — — PIO47
CTS_HU 24 — — ———— PIO46
Miscellaneous
Bus
Interface DEN 18 Bus
Interface DS —————
PIO30
DS 18 DEN —————
PIO30
PIOs
PIO0 144 TMRIN1 — —
PIO1 143 TMROUT1 — —
PIO2 10 PCS5 — —
PIO3 9PCS4 — —
PIO4 126 MCS0 — —
PIO5 129 MCS3 RAS1 —
A-6 Am186™CH HDLC Microcontroller Data Sheet
PIO6 147 INT8 PWD —
PIO7 146 INT7 — —
PIO8 14 ARDY — —
PIO9 124 DRQ0 — —
PIO10 2SDEN — —
PIO11 3SCLK — —
PIO12 4SDATA — —
PIO13 5PCS0 — —
PIO14 6PCS1 — —
PIO15 16 WR — —
PIO16 25 RXD_HU — —
PIO17 123 DCE_CTS_A PCM_TSC_A —
PIO18 122 DCE_RTR_A — —
PIO19 145 INT6 — —
PIO20 159 TXD_U — —
PIO21 22 UCLK — —
PIO22 150 — — —
PIO23 149 — — —
PIO24 157 CTS_U — —
PIO25 156 RTR_U — —
PIO26 158 RXD_U — —
PIO27 142 TMRIN0 — —
PIO28 141 TMROUT0 — —
PIO29 17 DT/R — —
PIO30 18 DEN DS —
PIO31 13 PCS7 — —
PIO32 11 PCS6 — —
PIO33 19 ALE — —
PIO34 20 BHE — —
PIO35 15 SRDY — —
PIO36 138 DCE_RXD_B PCM_RXD_B —
PIO37 139 DCE_TXD_B P CM_TXD_B —
PIO38 137 DCE_CTS_B PCM_TSC_B —
PIO39 136 DCE_RTR_B — —
PIO40 135 DCE_RCLK_B PCM_CLK_B —
PIO41 134 DCE_TCLK_B PCM_FSC_ B —
PIO42 153 — — —
PIO43 154 — — —
PIO44 152 — — —
PIO45 151 — — —
PIO46 24 CTS_HU — —
PIO47 23 RTR_HU — —
Table 25. Multiplexed Signal Trade-Offs (Continued)
DESIRED FUNCTION LOST FUNCTION
Interface Name Pin Interface Name Interface Name Interface Name Interface Name
Am186™CH HDLC Microcontroller Data Sheet A-7
Table 26. Reset Configuration Pins (Pinstraps)1
Signal Name Multiplex ed
Signal(s) Description
{ADEN}BHE
PIO34 Address Enable: If {ADEN} is held High or left floating during power-on reset, the
address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or
othe r mem ory bus cy cl es ba se d o n how the soft w are configures the D A b i t sett i ng . In
this case, the memory address is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on { ADEN} so no external pullup is required. This mode of
operation reduces power consumption.
If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data,
regardless of how software configures the DA bit setting.
{CLKSEL1}
{CLKSEL2}
HLDA
[PCS4]
PIO3
CPU PLL Mode Select 1 determines the PLL mode for the system clock source.
CPU PLL Mode Select 2 is sampled on the rising edge o f reset and determines the PLL
mode fo r the sy s t em cl ock source. T his pin has an i nte rnal pu ll up re si sto r tha t is ac ti ve
only during reset. There are four CPU PLL modes that are selected by the values of
{CLKSEL1} and {CLKSEL2} as shown below. (For details on clocks see “Clock
Generation and Control” on page 33.)
{ONCE} UCS ONCE Mode Request asserted Low places the Am186C H HDLC microc ontroller into
ONCE mode. Otherwise, the controller operates normally. In ONCE mode, all pins are
three-stated and remain in that state until a s ubseque nt reset occurs. To guarantee that
the controller does not inadvertently enter ONCE mode, {ON CE} has a weak internal
pullup resistor that is activ e only during a reset. A reset ending ONCE mode should be as
long as a po w er-on reset so that the PLL will s tabilize.
{UCSX8}[MCS0]
PIO4 Upper Memory Chip Select, 8 -Bit Bus asserted Lo w con fig ures the up per c hip s elect
regi on for an 8-bit b us siz e. This pi n has a pullup re sistor that is active only during reset,
so no external pullup is required to set the bus to 16-bit mode.
Notes:
1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be
held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external
reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
CPU PLL Modes
{CLKSEL1} {CLKSEL2} CPU PLL Mode
1 1 2X, CPU PLL enabled (default)
1 0 4X, CPU PLL enabled
0 1 1X, CPU PLL enabled
0 0 PLL Bypass
A-8 Am186™CH HDLC Microcontroller Data Sheet
Table 27. PIOs Sorted by PIO Number
PIO No. Pin No. Multiplexed Signal Multiplexed Signal Multiplexed Signal Pin Configuration Following
System Reset1
PIO0 144 TMRIN1 ——
Input with pullup
PIO1 143 TMROUT1 ——
Input with pulldown
PIO2 10 PCS5 ——
Input with pullup
PIO3 9PCS4 ——
Input with pullup
PIO4 126 MCS0 ——
Input with pullup
PIO5 129 MCS3 RAS1 —Input with pullup
PIO6 147 INT8 PWD —Input with pullup
PIO7 146 INT7 ——
Input with pullup
PIO8 14 ARDY ——
Alternate operation2
PIO9 124 DRQ0 ——
Input with pulldown
PIO10 2SDEN ——
Input with pulldown
PIO11 3SCLK ——
Input with pullup
PIO12 4SDATA ——
Input with pullup
PIO13 5PCS0 ——
Alternate operation2
PIO14 6PCS1 ——
Alternate operation2
PIO15 16 WR ——
Alternate operation2
PIO16 25 RXD_HU ——
Input with pullup
PIO17 123 DCE_CTS_A PCM_TSC_A —Input with pullup
PIO18 122 DCE_RTR_A ——
Input with pullup
PIO19 145 INT6 ——
Input with pullup
PIO20 159 TXD_U ——
Input with pullup
PIO21 22 UCLK ——
Input with pullup
PIO22 150 — — — Input with pulldown
PIO23 149 — — — Input with pulldown
PIO24 157 CTS_U ——
Input with pullup
PIO25 156 RTR_U ——
Input with pullup
PIO26 158 RXD_U ——
Input with pullup
PIO27 142 TMRIN0 ——
Input with pullup
PIO28 141 TMROUT0 ——
Input with pulldown
PIO29 17 DT/R ——
Alternate operation2
PIO30 18 DEN DS —Alternate operation2
PIO31 13 PCS7 ——
Input with pullup
PIO32 11 PCS6 ——
Input with pullup
PIO33 19 ALE ——
Alternate operation3
PIO34 20 BHE ——
Alternate operation2
PIO35 15 SRDY ——
Alternate operation2
PIO36 138 DCE_RXD_B PCM_RXD_B —Input with pullup
PIO37 139 DCE_TXD_B PCM _ TXD_B —Input with pullup
PIO38 137 DCE_CTS_B PCM_TSC_B —Input with pullup
PIO39 136 DCE_RTR_B ——
Input with pullup
PIO40 135 DCE_RCLK_B PCM_CLK_B —Input with pullup
PIO41 134 DCE_TCLK_B PCM_FSC_B —Input with pullup
PIO42 153 — — — Input with pulldown
PIO43 154 — — — Input with pulldown
PIO44 152 — — — Input with pullup
PIO45 151 — — — Input with pullup
PIO46 24 CTS_HU ——
Input with pullup
PIO47 23 RTR_HU ——
Input with pullup
Notes:
1. System reset is defined as a power-on reset (i.e., the
RES
input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with pullup option available.
3. When us ed as a PIO, input with a pu lldown option av ailab le.
Am186™CH HDLC Microcontroller Data Sheet A-9
Table 28. PIOs Sorted by Signal Name
Signal PIO No. Pin No. Multiplexed Signal Multiplexed Signal Pin Configuration Following
System Reset1
ALE PIO33 19 ——
Alternate operation2
ARDY PIO8 14 — — Alternate operation3
BHE PIO34 20 — — Alternate operation3
CTS_HU PIO46 24 — — Input with pullup
CTS_U PIO24 157 — — In put with pullup
DCE_CTS_A PIO17 123 PCM_TSC_A —Input with pullup
DCE_CTS_B PIO38 137 PCM_TSC_B —Input with pullup
DCE_RCLK_B PIO40 135 PCM_CLK_B —Input with pullup
DCE_RTR_A PIO18 122 — — Input with pullup
DCE_RTR_B PIO39 136 — — Input with pullup
DCE_RXD_B PIO36 138 PCM_RXD_B —Input with pullup
DCE_TCLK_B PIO41 134 PCM_FSC_B —Input with pullup
DCE_TXD_B PIO37 139 PCM_TXD_B —Input with pullup
DEN PIO30 18 DS —Alternate operation3
DRQ0 PIO9 124 — — Input with pulldown
DT/R PIO29 17 — — Alternate operation3
INT6 PIO19 145 — — In put with pullup
INT7 PIO7 146 — — Input with pullup
INT8 PIO6 147 PWD —Input with pullup
MCS0 PIO4 126 — — Input with pullup
MCS3 PIO5 129 RAS1 —Input with pullup
PCS0 PIO13 5 — — Alter nate operation3
PCS1 PIO14 6 — — Alter nate operation3
PCS4 PIO3 9 — — Input with pullup
PCS5 PIO2 10 — — Input with pullup
PCS6 PIO32 11 — — Input with pullup
PCS7 PIO31 13 — — Input with pullup
PIO22 — 150 — — In put with pulldown
PIO23 — 149 — — In put with pulldown
PIO42 — 153 — — In put with pulldown
PIO43 — 154 — — In put with pulldown
PIO44 — 152 — — In put with pullup
PIO45 — 151 — — In put with pullup
RTR_HU PIO47 23 — — Input with pullup
RTR_U PIO25 156 — — Input with pullup
RXD_HU PIO16 25 — — Input with pullup
RXD_U PIO26 158 — — Input with pullup
SCLK PIO11 3 — — Input with pullup
SDATA PIO12 4 — — In put with pullup
SDEN PIO10 2 — — Input with pulldown
SRDY PIO35 15 — — Alternate operation3
TMRIN0 PIO27 142 — — Input with pullup
TMRIN1 PIO0 144 Input with pullup
TMROUT0 PIO28 141 — — Input with pulldown
TMROUT1 PIO1 143 — — Input with pulldown
TXD_U PIO20 159 — — Input with pullup
UCLK PIO21 22 — — In put with pullup
UCLK PIO21 22 — — In put with pullup
WR PIO15 16 — — Alternate operation3
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When us ed as a PIO, input with a pu lldown option av ailab le.
3. When us ed as a PIO, input with a pu llup o ption available.
A-10 Am186™CH HDLC Microcontroller Data Sheet
Pin List Table Column Definitions
The following paragraphs describe the individual
columns of information in Table 30, “Pin List Summary,”
on page A- 11. The pin s are grouped alphabeti cally by
function.
Note: All maximum delay numbers should be in-
creased by 0.035 ns for every pF of load (up to a max-
imum of 150 pF) over the maximum load specified in
Table 30.
Column #1—Signal Name, [Alternate Function],
{Pinstrap}
This column denotes the primary and alternate
functions of the pins. Most of the pins that have
alternate functions are configured for these functions
via firmware modifying values in the Peripheral Control
Block. Refer to the
Am186™CC/CH/CU
Microcontrollers Register Set Manual
, order #21916,
for full documentation of this process.
Brackets, [ ], are used to indicate the alternate,
multiplexed function of a pin (i.e., not power-on reset
default).
Braces, { }, are used to indicate the functionality of a pin
only during a processor reset. These signals are called
pinstraps. To select the desired configuration, the
pinstraps are terminated internally with pullup resistors
or externally with pulldown resistors. Their state is
sampled during a processor reset and latched on the
rising edge of reset. The signals must be held in the
desired state for 4.5 system clock cycles after the
deassertion of reset. Based on the pinstrap’s state at
the time they are latched, certain features of the
Am186CH HDLC microcontroller are enabled or
disabled. All external termination should be
implemented with 10-Kohm resistors on these signals.
The pinstraps are listed in Table 26, “Reset
Configuration Pins (Pinstraps),” on page A-7.
Column #2—Pin No.
The pin number column identifies the pin number of the
individual I/O signal on the pac kage.
Column #3—T ype
Definitio ns of the abbreviations in the Type co lum n are
shown in Table 29.
Column #4—Max Load (pF)
The Max Load column designates the capacitive load
at which the I/O timing for that pin is guaranteed.
Column #5—POR Default Function
The POR Default Function column shows the status of
these pins after a power-on reset. In some cases the
pin is the function outlined in the “Signal Name” column
of the table. The signal name is listed in the POR
Default Function column if the signal is the default
function and not a PIO after a processor reset. In other
cas es the pin is a PIO configured as an input.
Column #6—Reset State
The Reset State column indicates the termination
present on the signal at reset (pul lup or pull down) and
indicates whether the signal is a three-stated output or
a Schmitt trigger input. Refer to Table 29 for
abbreviations used in this column.
Column #7—POR Default Operation
The POR Default Operation column describes the type
of input and/or output that is default pin operation.
Refer to Table 29 for abbreviations used in this column.
Column #8—Hold State
The Hold State column shows the state of the pin in
hold sta te. Refer to Table 29 for abbreviations u sed in
this column.
Column #9—5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs.
These inputs are not damaged and do not dra w excess
power when driven with levels up to VCC + 2.6 volts.
These pins only drive t o VCC.
Table 29. Pin List Table Definitions
Type Definition
[ ] Pin alternate function
{ } Pinstrap pin
B Bidirectional
HHigh
LS Programmable to hold last state of pin
O Totem pole output
OD Open drain output
OD-O Open drain output or totem pole output
PD Intern al pul ldown resistor
PU Intern al pul lup resistor
STI Schmitt trigger Input
STI-OD Schmitt trigger input or open drain output
TS Three-state output
Am186™CH HDLC Microcontroller Data Sheet A-11
Table 30. Pin List Summary
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A0 30 O 70 A0 TS-PD O TS-PD 5 V
A1 31 O 70 A1 TS-PD O TS-PD 5 V
A2 32 O 70 A2 TS-PD O TS-PD 5 V
A3 36 O 70 A3 TS-PD O TS-PD 5 V
A4 37 O 70 A4 TS-PD O TS-PD 5 V
A5 42 O 70 A5 TS-PD O TS-PD 5 V
A6 43 O 70 A6 TS-PD O TS-PD 5 V
A7 44 O 70 A7 TS-PD O TS-PD 5 V
A8 45 O 70 A8 TS-PD O TS-PD 5 V
A9 49 O 70 A9 TS-PD O TS-PD 5 V
A10 50 O 70 A10 TS-PD O TS-PD 5 V
A11 64 O 70 A11 TS-PD O TS-PD 5 V
A12 65 O 70 A12 TS-PD O TS-PD 5 V
A13 69 O 70 A13 TS-PD O TS-PD 5 V
A14 70 O 70 A14 TS-PD O TS-PD 5 V
A15 84 O 70 A15 TS-PD O TS-PD 5 V
A16 85 O 70 A16 TS-PD O TS-PD 5 V
A17 88 O 70 A17 TS-PD O TS-PD 5 V
A18 89 O 70 A18 TS-PD O TS-PD 5 V
A19 90 O 70 A19 TS-PD O TS-PD 5 V
AD0 2 8 B 70 AD0 TS-PD B TS 5 V
AD1 3 4 B 70 AD1 TS-PD B TS 5 V
AD2 3 8 B 70 AD2 TS-PD B TS 5 V
AD3 4 6 B 70 AD3 TS-PD B TS 5 V
AD4 5 1 B 70 AD4 TS-PD B TS 5 V
AD5 6 6 B 70 AD5 TS-PD B TS 5 V
AD6 8 6 B 70 AD6 TS-PD B TS 5 V
AD7 9 2 B 70 AD7 TS-PD B TS 5 V
AD8 2 9 B 70 AD8 TS-PD B TS 5 V
AD9 3 5 B 70 AD9 TS-PD B TS 5 V
AD10 39 B 70 AD10 TS-PD B T S 5 V
AD11 47 B 70 AD11 TS-PD B T S 5 V
AD12 52 B 70 AD12 TS-PD B T S 5 V
AD13 67 B 70 AD13 TS-PD B T S 5 V
AD14 87 B 70 AD14 TS-PD B T S 5 V
AD15 93 B 70 AD15 TS-PD B T S 5 V
ALE
[PIO33] 19 O
STI-PD [STI] [O] 50 ALE TS-PD O TS-PD 5 V
ARDY
[PIO8] 14 STI-PU
STI-PU [STI] [O] 50 ARDY STI-PU STI-PU STI 5 V
A-12 Am186™CH HDLC Microcontroller Data Sheet
BHE
[PIO34]
{ADEN}20 O
STI-PU [STI] [O]
STI 50 BHE STI-PU O TS-PU 5 V
BSIZE8 94 O 50 BSIZE8 TS-PU O ——
DEN
[DS]
[PIO30] 18 O
O
STI-PU [STI] [O] 50 DEN TS-PU O TS-PU 5 V
[DRQ0]
PIO9 124 STI-PD
STI-PD [STI] [O] 50 PIO9 STI-PD STI-PD [STI] [O] — 5 V
DRQ1 105 STI-PD — DRQ1 STI-PD STI-PD — 5 V
DT/R
[PIO29] 17 O
STI-PU [STI] [O] 50 DT/R TS-PU O TS-PU 5 V
HLDA
{CLKSEL1} 98 O
STI 50 HLDA STI-PU O H 5 V
HOLD 99 STI — HOLD STI-PD STI H 5 V
RD 97 O 70 RD TS-PU O TS-PU 5 V
S0 57 O 50 S0 STI-PU O TS 5 V
S1 56 O 50 S1 TS-PU O TS 5 V
S2 55 O 50 S2 TS-PU O TS 5 V
S6 54 O 50 S6 TS-PD O TS 5 V
SRDY
[PIO35] 15 STI-PU
STI-PU [STI] [O] 50 SRDY STI-PU STI-PU — 5 V
WHB 95 O 70 WHB TS-PU O TS-PU 5 V
WLB 96 O 70 WLB TS-PU O TS-PU 5 V
WR
[PIO15] 16 O
STI-PU [STI] [O] 50 WR STI-PU O TS-PU 5 V
CHIP SELECTS
LCS
[RAS0]131 O
O50 LCS TS-PU O TS-PU 5 V
[MCS0]
PIO4
{UCSX8}126 O
STI-PU [STI] [O]
STI 50 PIO4 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
MCS1
[CAS1]127 O
O50 MCS1 TS-PU O TS-PU 5 V
MCS2
[CAS0]128 O
O50 MCS2 TS-PU O TS-PU 5 V
[MCS3]
[RAS1]
PIO5 129 O
O
STI-PU [STI] [O] 50 PIO5 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
PCS0
[PIO13] 5O
STI-PU [STI] [O] 50 PCS0 STI-PU O TS-PU 5 V
PCS1
[PIO14] 6O
STI-PU [STI] [O] 50 PCS1 STI-PU O TS-PU 5 V
PCS2 7 O 50 PCS2 TS-PU O TS-PU 5 V
PCS3 8 O 50 PCS3 TS-PU O TS-PU 5 V
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CH HDLC Microcontroller Data Sheet A-13
[PCS4]
PIO3
{CLKSEL2} 9O
STI-PU [STI] [O]
STI 50 PIO3 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
[PCS5]
PIO2 10 O
STI-PU [STI] [O] 50 PIO2 STI-PU O TS-PU 5 V
[PCS6]
PIO32 11 O
STI-PU [STI] [O] 50 PIO32 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
[PCS7]
PIO31 13 O
STI-PU [STI] [O] 50 PIO31 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
UCS
{ONCE}132 O
STI 50 UCS STI-PU O TS-PU 5 V
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT 60 O 70 CLKOUT —O ——
RES 114 ST — RES STI STI — 5 V
RESOUT 58 O 50 RESOUT H O — 5 V
[UCLK]
PIO21 22 STI
STI-PU [STI] [O] 50 PIO21 STI-PU STI-PU [STI] [O] — 5 V
X1 73 STI — X1 — STI — —
X2 74 O — X2 — O — —
PROGRAMMABLE TIMERS
[PWD]
[INT8]
PIO6 147 STI
STI
STI-PU [STI] [O] 50 PIO6 STI-PU STI-PU [STI] [O] — 5 V
[TMRIN0]
PIO27 142 STI-PU
STI-PU [STI] [O] 50 PIO27 STI-PU STI-PU [STI] [O] — 5 V
[TMRIN1]
PIO0 144 STI-PU
STI-PU [STI] [O] 50 PIO0 STI-PU STI-PU [STI] [O] — 5 V
[TMROUT0]
PIO28 141 O
STI-PD [STI] [O] 50 PIO28 STI-PD STI-PD [STI] [O] TS 5 V
[TMROUT1]
PIO1 143 O
STI-PD [STI] [O] 50 PIO1 STI-PD STI-PD [STI] [O] TS 5 V
INTERRUPTS
INT0 107 STI — INT0 STI -PU STI — 5 V
INT1 109 STI — INT1 STI -PU STI — 5 V
INT2 110 STI — INT2 STI -PU STI — 5 V
INT3 111 STI — INT3 STI -PU STI — 5 V
INT4 112 STI — INT4 STI -PU STI — 5 V
INT5 113 STI — INT5 STI -PU STI — 5 V
[INT6]
PIO19 145 STI
STI-PU [STI] [O] 50 PIO19 STI-PU STI-PU [STI] [O] — 5 V
[INT7]
PIO7 146 STI
STI-PU [STI] [O] 50 PIO7 STI-PU STI-PU [STI] [O] — 5 V
[INT8]
[PWD]
PIO6 147 STI
STI
STI-PU [STI] [O] 50 PIO6 STI-PU STI-PU [STI] [O] — 5 V
NMI 115 STI — NMI STI-PU STI — 5 V
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
A-14 Am186™CH HDLC Microcontroller Data Sheet
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATIONS INTERFACES
HDLC Channel A
DCE_RXD_A
[PCM_RXD_A] 118 STI
STI 50 DCE_RXD_A STI-PU STI —5 V
DCE_TXD_A
[PCM_TXD_A] 119 O-OD
O-LS-OD 50 DCE_TXD_A TS-PU OD-O — 5 V
DCE_RCLK_A
[PCM_CLK_A] 117 STI
STI — DCE_RCLK_A STI -PU STI — 5 V
DCE_TCLK_A
[PCM_FSC_A] 116 STI
STI — DCE_TCLK_A STI-PU STI — 5 V
[DCE_CTS_A]
[PCM_TSC_A]
PIO17 123 STI
OD
STI-PU [STI] [O] 50 PIO17 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RTR_A]
PIO18 122 O
STI-PU [STI] [O] 30 PIO18 STI-PU STI-PU [ S T I ] [ O ] — 5 V
HDLC Channel B
[DCE_RXD_B]
[PCM_RXD_B]
PIO36 138 STI
STI
STI-PU [STI] [O] 50 PIO36 STI-PU STI-PU [STI] [O] — 5 V
[DCE_TXD_B]
[PCM_TXD_B]
PIO37 139 OD-O
O-LS-OD
STI-PU [STI] [O] 50 PIO37 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RCLK_B]
[PCM_CLK_B]
PIO40 135 STI
STI
STI-PU [STI] [O] 50 PIO40 STI-PU STI-PU [STI] [O] — 5 V
[DCE_TCLK_B]
[PCM_FSC_B]
PIO41 134 STI
STI
STI-PU [STI] [O] 50 PIO41 STI-PU STI-PU [STI] [O] — 5 V
[DCE_CTS_B]
[PCM_TSC_B]
PIO38 137 STI
OD
STI-PU [STI] [O] 50 PIO38 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RTR_B]
PIO39 136 O
STI-PU [STI] [O] 30 PIO39 STI-PU STI-PU [STI] [O] — 5 V
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U]
PIO26 158 STI
STI-PU [STI] [O] 50 PIO26 STI-PU STI-PU [STI] [O] — 5 V
[TXD_U]
PIO20 159 O
STI-PU [STI] [O] 50 PIO20 STI-PU STI-PU [STI] [O] — 5 V
[CTS_U]
PIO24 157 STI
STI-PU [STI] [O] 50 PIO24 STI-PU STI-PU [STI] [O] — 5 V
[RTR_U]
PIO25 156 O
STI-PU [STI] [O] 30 PIO25 STI-PU STI-PU [STI] [O] — 5 V
HIGH-SPEED UART
[RXD_HU]
PIO16 25 STI
STI-PU [STI] [O] 50 PIO16 STI-PU STI-PU [STI] [O] — 5 V
TXD_HU 26 O 30 TXD_HU TS-PU O — 5 V
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CH HDLC Microcontroller Data Sheet A-15
[CTS_HU]
PIO46 24 STI
STI-PU [STI] [O] 50 PIO46 STI-PU STI-PU [STI] [O] —5 V
[RTR_HU]
PIO47 23 O
STI-PU [STI] [O] 30 PIO47 STI-PU STI-PU [STI] [O] — 5 V
DEBUG SUPPORT
QS0 6 2 O 30 QS0 TS-PD O — 5 V
QS1 6 3 O 30 QS1 TS-PD O — 5 V
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK]
PIO11 3O
STI-PU [STI] [O] 50 PIO11 STI-PU STI-PU [STI] [O] — 5 V
[SDATA]
PIO12 4O
STI-PU [STI] [O] 50 PIO12 STI-PU STI-PU [STI] [O] — 5 V
[SDEN]
PIO10 2O
STI-PD [STI] [O] 50 PIO10 STI-PD STI-PD [STI] [O] — 5 V
RESERVED PINS
RSVD_104 104 — — — — — — —
RSVD_103 103 — — — — — — —
RSVD_102 102 — — — — — — —
RSVD_101 101 — — — — — — —
RSVD_81 81 — — — — — — —
RSVD_80 80 — — — — — — —
RSVD_76 76 — — — — — — —
RSVD_75 75 — — — — — — —
POWER AND GROUND
VCC 12 — — — — — — —
VCC 27 — — — — — — —
VCC 40 — — — — — — —
VCC 48 — — — — — — —
VCC 59 — — — — — — —
VCC 68 — — — — — — —
VCC 78 — — — — — — —
VCC 82 — — — — — — —
VCC 91 — — — — — — —
VCC 106 — — — — — — —
VCC 120 — — — — — — —
VCC 125 — — — — — — —
VCC 133 — — — — — — —
VCC 148 — — — — — — —
VCC 160 — — — — — — —
VCC 79 — — — — — — —
VCC_A77———————
VSS 1————— ——
VSS 21 — — — — — — —
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
A-16 Am186™CH HDLC Microcontroller Data Sheet
VSS 33 ——— — — ——
VSS 41 — — — — — — —
VSS 53 — — — — — — —
VSS 61 — — — — — — —
VSS 71 — — — — — — —
VSS 83 — — — — — — —
VSS 100 — — — — — — —
VSS 108 — — — — — — —
VSS 121 — — — — — — —
VSS 130 — — — — — — —
VSS 140 — — — — — — —
VSS 155 — — — — — — —
VSS_A72———————
Table 30. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CH HDLC Microcontroller Data Sheet B-1
APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP)
25.35
REF
27.90
28.1031.00
31.40
Pin 120
Pin 80
0.65 BASIC
3.20
3.60
0.25
Min
Pin 40
Pin 1 I.D.
25.35
REF
Pin 160
27.90
28.10
31.00
31.40
3.95
MAX
SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
B-2 Am186™CH HDLC Microcontroller Data Sheet
Am186™CH HDLC Microcontroller Data Sheet C-1
APPENDIX C—CUSTOMER SUPPORT
Related AMD Products—E86™ Family Devices
Device Description
80C186/80C188 16-bit microcontroller
80L186/80L188 Low-voltage, 16-bit microcontroller
Am186™EM/Am188™EM High-performance, 16-bit embedded microcontroller
Am186EMLV/Am188EMLV High-performance, 16-bit embedded microcontroller
Am186ES/Am188ES High-performance, 16-bit embedded microcontroller
Am186ESLV/Am188ESLV High-performance, 16-bit embedded microcontroller
Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
Am186EDLV High-performance, 80C186- and 80C188-compatible, low-v oltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
Am186ER/Am188ER High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of
internal RAM
Am186CC High-performance, 16-bit embedded communications controller
Am186CH High-performance, 16-bit embedded HDLC microcontroller
Am186CU High-performance, 16-bit embedded USB microcontroller
Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller
ÉlanSC400 Single-chip, low-power, PC/AT-compatible microcontroller
ÉlanSC410 Single-chip, PC/AT-compatible microcontroller
ÉlanSC520 High-performance, 32-bit embedded microcontroller
Am386®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am386®SX High-performance, 32-bit embedded microprocessor with 16-bit external data bus
Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am5x86® High-performance, 32-bit embedded microprocessor with 32-bit external data bus
AMD-K6™E High-performance, 32-bit embedded microprocessor with 64-bit external data bus
AMD-K6™-2E High-performance, 32-bit embedded microprocessor with 64-bit external data bus and
3DNow!™ technology
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
Am386
®
SX/DX
Microprocessors
Am486
®
DX
Microprocessor
E86™ Family of Embedded Microprocessors and Microcontrollers
Am186 E S and
Am188™EM
Am188EMLV Microcontrollers
Am188ER
— Microprocessors
— 16- and 32-bit microcontrollers
— 16-bit microcontrollers
AMD-K6™E
Microprocessor
AMD-K6™-2E
Microprocessor
Am5x86®
Microprocessor
Am186CC
Communications
Controller
Am186™CU USB
Microcontroller
Am186CH HDLC
Microcontroller
80C186 and 80C188
Microcontrollers
Am188ES
Microcontrollers
Am186EM and
Microcontrollers
80L186 and 80L188
Microcontrollers
Am186EMLV &
Microcontrollers
Am186ESLV &
Am188ESLV
Am186ER and
Microcontrollers
Am186ED
Am186EDLV
Microcontroller
Microcontroller
Élan ™SC310
Microcontroller
ÉlanSC300
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC400
Microcontroller
ÉlanSC520
Microcontroller
C-2 Am186™CH HDLC Microcontroller Data Sheet
Related Documents
The following documents provide additional
information regarding the Am186CH HDLC
microcontroller.
■
Am186™CC/CH/CU Microcontrollers User’s Manual
,
order #21 914
■
Am186™CC/CH/CU Microcontrollers Register Set
Manual
, order #21916
■
Am186™ and Am188™ Family Instruction Set
Manual
, order #21267
■
Interfacing an Am186™CC Communications
Controller to an AMD SLAC™ Device Using the
Enhanced SSI
, order #21921
Other information of interest includes:
■
E86™ Family Products and Development Tools CD,
order #21058
Am186CC/CH/CU Microcontroller
Customer De velopment Platform
The Am186CC/CH/CU customer development
platfor m (CDP) is provided as a test and developmen t
platform for the Am186CC/CH/CU microcontrollers.
The Am186CC/CH/ CU CDP ships with the Am186CC
microcontroller. Because this device supports a
superset of the features of the Am186CH HDLC
microcontroller, the development platform can be used
to evaluate the Am186CH device.
The CDP is divided into two major sections: a main
board and a development module. The main board
serves as the primary platform for silicon evaluation
and software development. The board provides
connectors for accessing the major communications
peripherals, switches to easily configure the
microcontroller, logic analyzer, and debug headers.
The develo pme nt mo dul e, which att ac hes to the top of
the main board, provides ready-to-run hardware for
three of the most common communications
requirements:
■A 10 Mbit/s Ethernet connection
■An ISDN connection (with both an S/T and a
U interface)
■Two POTS interfaces
The CDP provides a good star ting point for hardware
designers, and software development can begin
immediately without the normal delay that occurs while
waiting for prototypes.
The CDP also comes with AMD’s CodeKit software
that provides customers with pre-written driver
software for the major communications peripherals
associated with a typical Am186Cx design. Included
are drivers for the HDLC channels, USB peripheral
controller (for the Am186CU USB microcontroller),
UARTs, PCnet-ISA II (AMD’s single-chip Ethernet
solution), and several other common peripherals. The
CodeKit software comes complete with instructions,
royalty-free distribution rights, and software in both
binary and source code formats.
Third-Party Development Support Products
The FusionE86 Program of Partnerships for
Application Solutions provides the customer with an
array of products designed to meet critical time-to-
market needs. Products and solutions available from
the AMD FusionE86 partners include protocol stacks,
emulators, hardware and software debuggers, board-
lev el products, and software dev elopment tools, among
others.
In addition, mature de v elopment tools and applications
for the x8 6 pl atfo rm are wi del y available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S.
offices, international offices, and a customer training
center. Expert technical assistance is available from
the AMD wo rldwide staff of fi eld appli cation e ngineers
and factory support sta ff to answer E86 an d Comm86
family hardware and software development questions.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to www.amd.com/support/literature.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail suppor t as well as a toll-free number for direct
access to our corporate applications hotline.
The AMD World Wide Web home page provides the
latest product information, including technical
information and data on upcoming product releases. In
addition, EPD CodeKit software on the Web site
provides tested source code example applications.
Additional contact information is listed on the back of
this datasheet. For technical suppor t questions on all
E86 and Comm86 products, send e-mail to
epd.support@amd.com.
Corporate Applications Hotline
(800) 222-9323 Toll-free for U.S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
Am186™CH HDLC Microcontroller Data Sheet C-3
World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processors link for
information about E86 and Comm86 products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to
webmaster@amd.com.
Documentation and Literature
Fr ee inform ation such as data books, user’s manuals,
data sheets, application notes, the
E86™ Family
Products and Development Tools CD
, order #21058,
and other literature is available with a simple phone
call. Internationally, contact your local AMD sales office
for product literature. Additional contact information is
listed on the back of this data sheet.
Literature Ordering
(800) 222-9323 Toll-free for U.S. and Canada
C-4 Am186™CH HDLC Microcontroller Data Sheet
Am186™CH HDLC Microcontroller Data Sheet Index-1
INDEX
A
A19–A0 signals, 13
AD15–AD0 signals, 13
address and data bus (AD15–AD0)
description, 13
address bus (A19–A0)
address bus disable in effect, 29
default operation, 29
ADEN signal, A-7
ALE signal, 13
Am186CH HDLC microcontroller
applications, 31
block diagram (microcontroller), 24
DC characteristics, 37
distinctive characteristics, 1
document atio n, C-2
general description, 1
I/O circuitry, 36
logic diagram by default pin function, 7
logic diagram by interface, 6
logic diagrams, 6–7
ordering information, 2
overview (architectural), 24
physical dimensions, B-1
pin assignment tables, 10
pin connection diagram, 8
pin tables (Appendix A), A-1
PQFP package, B-1
related AMD E86 family devices, C-1
signal description table, 13
static operation, 35
applications, 31
32-channel linecard system, 32
archit ectural overview, 24
ARDY signal, 13
asynchronous communications
asynchronous ready waveforms, 58
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
UART signal descriptions, 21
B
BHE signal, 14
block diagram (microcontroller), 24
BSIZE8 signal, 14
busaddress bus description, 13
bus hold timing, 59
bus status pins, 16
entering bus hold waveforms, 59
ex iting bus hold waveforms, 60
bus i n terfa ce
description, 30
signal li st, 13
byte write enables, 30
C
capacit ance, 38
CAS1–CAS0 signals, 19
characteristics
See
DC character i sti cs.
switching characteristics, 40
chip selects
description, 30
ranges and DRAM configuration, 13, 19
signal des cription s, 19
CLKOUT signal, 17
CLKSEL1 signal, A-7
CLKSEL2 signal, A-7
clock
See also
CPU.
CLKOUT signal description, 17
clock generation and control, 33
control, 31
crystal parameters, 34
crystal-driven clock source, 34
external clock source, 35
external interface to support clocks, 34–35
features, 33
High-Speed UART clocks, 35
PLL bypass mode, 35
suggested system clock frequencies, clock modes
and crystal frequencies, 34
system clock, 33
system interfaces and clock control, 28
UART baud clock, 35
Index-2 Am186™CH HDLC Microcontroller Data Sheet
CPU
Am186 embedded CPU, 25
CPU PLL modes, A-7
system clock, 33
system clock timing waveforms, 62
system clocks timing, 61
crystal
crystal-driven clock source, 34
parameters, 3 4
suggested crystal frequencies, 34
CTS_HU signal, 22
CTS_U signal, 22
customer support
documentation and literature, C-3
hotline and web, C-2
literature ordering, C-3
ordering the microcontroller, 2
third-party development support products, C-2
web home page, C-3
D
DC characteristics over commercial and industrial
operating ranges, 37
DCE (data communications equipment)
DCE interface timing, 65
DCE receive waveforms, 65
DCE transmit waveforms, 65
signal descriptions, 22
DCE_CTS_A signal, 23
DCE_CTS_B signal, 23
DCE_RCLK_A signal, 22
DCE_RCLK_B signal, 23
DCE_RTR_A signa l, 23
DCE_RTR_B signa l, 23
DCE_RXD_A signal, 22
DCE_RXD_B signal, 23
DCE_TCLK_A signal, 23
DCE_TCLK_B signal, 23
DCE_TXD_A si gna l, 2 2
DCE_TXD_B si gna l, 2 3
debug
debug support signals, 18
DEN signal, 14
derating, 38
DMA (direct memory access)
DMA request signals, 14
general-purpose DMA channels, 27
SmartDMA channels, 26
timing waveforms, 54
documenta tio n, C-3
DRAM
chip selects and DRAM configuration, 13
description, 30
read cycle with wait states waveform, 68
read cycle without wait states waveform, 68
refresh cycle waveform, 70
signal des cription s, 19
timing, 67
write cycle with wait states waveform, 69
write cycle without wait states waveform, 69
DRQ1–DRQ0 signal s, 14
DS signal, 14
DT/R signal, 14
E
emulation
in-circuit emulator (ICE) support, 31
signals used by emulators, 18
evaluation platform, C-2
H
halt
See
software halt.
HDLC (high-level data link control)
channels and TSAs description, 26
signal des cr i pti on s, 2 2
High-Speed UAR T
signal des cription s, 22
HLDA signal, 15
HOLD signal, 15
hotline and world wide web support, C-2
I
I/O
See also
memory.
I/O circuitry, 36
I/O space, 25
programmable I/O (PIO), 27
ICE (in-circuit emulator) support, 31
INT8–INT0 signals, 20
interrupts
interrupt controller, 27
signal des cription s, 20
L
LCS signal, 19
logic diagram
by default pin function, 7
by interface, 6
Am186™CH HDLC Microcontroller Data Sheet Index-3
M
MCS3–MCS0 signals, 19
memory
See also
I/O.
memory organization, 25
segment register selection rules, 26
memory and peripheral interface, 28
multiplexed functions
signal trade-offs, A-5
N
NMI signal, 2 0
O
ONCE signa l, A- 7
operating ranges, 37
ordering information, 2
output enable, 30
P
package
PQFP physical dimensions, B-1
PCM (pulse - code modulation ) highway
signal descriptions, 23
timing (timing slave), 62
waveforms (timing slave), 63
PCM_CLK_A signal, 23
PCM_CLK_B signal, 23
PCM_FSC_A signal, 23
PCM_FSC_B signal, 23
PCM_RXD_A signal, 23
PCM_RXD_B signal, 23
PCM_TSC_A signal, 23
PCM_TSC_B signal, 23
PCM_TXD_A signal, 23
PCM_TXD_B signal, 23
PCS7–PCS0 signals, 19
peripherals
memory and peripheral interface, 28
peripheral timing, 54
peripheral timing waveforms, 54
system interfaces, 27
pins
See also
signals.
pin and signal tables, 9
pin assignments sorted by pin number, 10
pin assignments sorted by signal name, 11
pin connection diagram, 8
pin defaults, A-2
pin list summary, A-11
pin tables (Appendix A), A-1
Multiplexed Signal Trade-Offs table, A-5
Pin List Summary table, A-11
PIOs Sorted by PIO Number table, A-8
PIOs Sorted by Signal Name table, A-9
Power-On Reset (POR) Pin Defaults table, A-2
reserved, 18
pinstraps
pinstraps table, A-7
PIO47–PIO0 signals, 21
PIOs (programmable I/Os)
description, 27
signal des cr i pti on s, 2 1
sorted by pin number, A-8
sorted by signal name, A-9
PLL (phase-locked loop)
bypass mode, 35
modes, A-7
PLL bypass (CPU), A-7
system PLL, 33
POR (power-on reset)
pin defaults, A-2
power
power and ground pins, 18
power consumption calculation, 38
power supply operation, 36
supply connections, 36
supply current, 38
typical ICC versus frequency, 38
PQFP package
physical dimensions, B-1
pulldowns, in Pin List Summary table, Type column, A-
11
pullups, in Pin List Summary table, Type column, A-11
PWD signal, 21
Q
QS1–QS0 signals, 18
Index-4 Am186™CH HDLC Microcontroller Data Sheet
R
RAS1–RAS0 signals, 19
RD signal, 15
read cycle timing, 47
read cycle wavefor m s, 49
ready
external ready timing, 57
external ready wa veforms, 57
RES signal, 17
reserved pins, 18
reset
definition of types, 12
power-on reset pin defaults table, A-2
signals related to reset, 56
ti ming, 55
waveforms, 55
reset configuration pins
See
pinstraps.
RESOUT signal, 17
RSVD_x–RSVD_x pins, 18
RTR_HU signal, 22
RTR_U signal, 22
RXD_HU signal, 22
RXD_U signal, 21
S
S2–S0 signals, 16
S6 signal, 16
SCLK signal, 22
SDATA signal, 22
SDEN signal, 22
serial communications
See also
HDLC, UART.
asynchronous serial ports, 26
description, 26
SmartDM A, 26
synchronous serial port, 27
signals
See also
pins.
multiplexed signal trade-offs table, A-5
pin and signal tables, 9
pin assignments sorted by signal name, 11
signal descriptions, 13
signals related to reset, 56
SmartDMA
See
DMA.
softw are halt cycle t iming, 53
software halt cycle waveforms, 53
SRDY signal, 16
SSI (synchronous serial interface)
signal des cr i pti on s, 2 2
synchronous ready waveforms, 57
synchron ous ser i al port, 27
timing, 66
waveforms, 66
static operation, 35
switching characteristics and waveforms
alphabetical key, 41
key to switching waveforms, 40
numerical key to switching parameter symbols, 44
over commercial/industrial operating ranges, 47
parameter symbols, 41
system clock, 33
See
CPU.
system interface, 28
T
thermal characteristics, 39
equations, 39
thermal resistance, 39
timers
See also
watchdog timer.
programmable timers, 27
signal des cription s, 21
timing
asynchronous ready waveforms, 58
bus hold, 59
DCE interface, 65
DMA, 54
DRAM, 67
external ready cycle, 57
PCM highway, 62–63
perip heral timing, 54
read cycle timing, 47
reset, 55
software halt cycle, 53
SSI, 66
synchronous ready waveforms, 57
system clocks timing, 61
write cycle timing, 50
TMRIN1–TMRIN0 signals, 21
TMROUT1–TMROUT0 signals, 21
TSAs (time slot assigners)
description, 26
TXD_HU signal, 22
TXD_U signal, 21
Am186™CH HDLC Microcontroller Data Sheet Index-5
U
UART
asynchronous ready waveforms, 58
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
signal descriptions, 21
UART and High-Speed UART clocks, 35
UART baud clock, 35
UCLK signal, 17
UCS signal, 19
UCSX8 si gna l, A -7
V
VCC description, 18
VCC_A description, 18
VSS description, 18
VSS_A description, 18
W
watchdog timer
description, 28
RES and watchdog timer reset, 17
WHB signal, 16
WLB signal, 16
WR signal, 16
write cycle timing, 50
write cycle waveforms, 52
www
home page, C-3
support, C-2
X
X1 signal, 17
X2 signal, 17
Am186™CH HDLC Microcontroller Data Sheet
Trademarks
È
2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am5x86 and Am386 are registered trademarks, and AMD-K6, 3DNow!, Am186, Am188, Comm86, E86, Élan, PCnet, SLAC, and SmartDMA
are trademarks of Advanced Micro Devi ces , Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, I nc. ("AMD") products. AMD makes no representations
or warranties with respect to the accur acy or completeness of the contents of this publication and reserves the right to make changes to speci-
fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in-
tellectual property rights is granted by this pub lication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, b ut not limited to, the implied warrant y of
merchantability, fitness for a particular purpos e, or infringement of any intellectual property r ight.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontin ue o r make
changes to its products at any time without notice.
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
