MAX31865 RTD-to-Digital Converter General Description Benefits and Features Applications High Accuracy Facilitates Meeting Error Budgets * 15-Bit ADC Resolution; Nominal Temperature Resolution 0.03125NC (Varies Due to RTD Nonlinearity) * Total Accuracy Over All Operating Conditions: 0.5NC (0.05% of Full Scale) max * Fully Differential VREF Inputs * 21ms (max) Conversion Time The MAX31865 is an easy-to-use resistance-to-digital converter optimized for platinum resistance temperature detectors (RTDs). An external resistor sets the sensitivity for the RTD being used and a precision delta-sigma ADC converts the ratio of the RTD resistance to the reference resistance into digital form. The MAX31865's inputs are protected against overvoltage faults as large as Q45V. Programmable detection of RTD and cable open and short conditions is included. Industrial Equipment Medical Equipment Instrumentation Integration Lowers System Cost, Simplifies Design Efforts, and Reduces Design Cycle Time * Simple Conversion of Platinum RTD Resistance to Digital Value * Handles 100 to 1k (at 0C) Platinum RTDs (PT100 to PT1000) * Compatible with 2-, 3-, and 4-Wire Sensor Connections * SPI-Compatible Interface * 20-Pin TQFN and SSOP Packages Integrated Fault Detection Increases System Reliability * 45V Input Protection * Fault Detection (Open RTD Element, RTD Shorted to Out-of-Range Voltage, or Short Across RTD Element) Ordering Information appears at end of data sheet. Typical Application Circuits VDD VDD 4-WIRE SENSOR CONNECTION 0.1F DVDD VDD 0.1F BIAS REFIN+ DRDY REFIN- SDI HOST INTERFACE SCLK RREF ISENSOR MAX31865 RCABLE FORCE+ CS FORCE2 SDO RTDIN+ RCABLE N.C. CI* RTD RCABLE DGND GND2 GND1 RTDINFORCERCABLE *CI = 10nF FOR 1k RTD 100nF FOR 100 RTD Typical Application Circuits continued at end of data sheet. 19-6478; Rev 3; 7/15 MAX31865 RTD-to-Digital Converter Absolute Maximum Ratings Voltage Range on VDD Relative to GND1.............-0.3V to +4.0V Voltage Range on BIAS, REFIN+, REFIN-, ISENSOR.................................. -0.3V to (VDD + 0.3V) Voltage Range on FORCE+, FORCE2, FORCE-, RTDIN+, RTDIN- Relative to GND1.....-50V to +50V Voltage Range on DVDD Relative to DGND.........-0.3V to +4.0V Voltage Range on All Digital Pins Relative to DGND.............................. -0.3V to (VDVDD + 0.3V) Continuous Power Dissipation (TA = +70NC) TQFN (derate 34.5mW/NC above +70NC)...............2758.6mW SSOP (derate 11.9mW/C above +70 C)...............952.4mW ESD Protection (all pins, Human Body Model)....................2kV Operating Temperature Range......................... -40NC to +125NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+260NC Lead Temperature (soldering,10s)..................................+300NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA)...........29C/W Junction-to-Case Thermal Resistance (qJC)..................2C/W SSOP Junction-to-Ambient Thermal Resistance (qJA)...........84C/W Junction-to-Case Thermal Resistance (qJC)................32C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Recommended DC Operating Conditions (TA = -40NC to +125NC, unless otherwise noted.) (Notes 2 and 3) PARAMETER SYMBOL MIN TYP MAX UNITS VDD 3.0 3.3 3.6 V VDVDD 3.0 3.3 VDD DVDD CONDITIONS 3.6 V V Input Logic 0 VIL CS, SDI, SCLK -0.3 0.3 x VDVDD Input Logic 1 VIH CS, SDI, SCLK 0.7 x VDVDD VDVDD + 0.3 V 0 VBIAS V 350 10k I 0 50 I Analog Voltages (FORCE+,FORCE2, FORCE-, RTDIN+, RTDIN-) Normal conversion results Reference Resistor Cable Resistance RREF RCABLE Per lead Electrical Characteristics (3.0V P VDD P 3.6V, TA = -40NC to +125NC, unless otherwise noted. Typical values are TA= +25NC, VDD = VDVDD = 3.3V.) (Notes 2 and 3) PARAMETER ADC Resolution ADC Full-Scale Input Voltage (RTDIN+ - RTDIN-) www.maximintegrated.com SYMBOL CONDITIONS No missing codes MIN TYP MAX UNITS 15 Bits REFIN+ REFIN- V Maxim Integrated 2 MAX31865 RTD-to-Digital Converter Electrical Characteristics (continued) (3.0V P VDD P 3.6V, TA = -40NC to +125NC, unless otherwise noted. Typical values are TA= +25NC, VDD = VDVDD = 3.3V.) (Notes 2 and 3) PARAMETER SYMBOL CONDITIONS ADC Common-Mode Input Range MIN 0 Input Leakage Current RTDIN+, RTDIN-, 0NC to +70NC, on-state 2 RTDIN+, RTDIN-, -40NC to +85NC, on-state 5 RTDIN+, RTDIN-, -40NC to 100NC, on-state 14 Bias Voltage VBIAS 1.95 Bias Voltage Output Current IOUT 0.2 Bias Voltage Load Regulation IOUT P 5.75mA Bias Voltage Startup Time (Note 4) ADC Offset Error Input referred Common-Mode Rejection 50/60Hz Noise Rejection Fundamental and harmonics Continuous conversion (60Hz notch) tCONV Automatic Fault Detection Cycle Time V mA mV/mA 1 LSB +3 FV RMS 90 dB 82 dB 55 Single conversion (50Hz notch) 62.5 66 Continuous conversion (50Hz notch) 20 21 From CS high to cycle complete 550 600 Bias on, active conversion 2 CIN Logic inputs IL Logic inputs Output High Voltage VOH IOUT = -1.6mA Output Low Voltage VOL IOUT = 1.6mA -1 LSB 150 17.6 Bias off, ADC off ms LSB 52 Power-On Reset Voltage Hysteresis www.maximintegrated.com 2.06 5.75 1 IDD Shutdown IDD Input Leakage Current nA 16.7 Power-On Reset Voltage Threshold Input Capacitance V Single conversion (60Hz notch) Power-Supply Rejection Power-Supply Current (Note 6) VBIAS 1 -3 Noise (over Nyquist Bandwidth) UNITS 10 Differential Input, endpoint fit, 0.3 x VBIAS P VREF P VBIAS ADC Integral Nonlinearity 2.00 MAX 30 ADC Full-Scale Error Temperature Conversion Time (Note 5) TYP ms Fs LSB/V 1.5 3 mA 2 3.5 mA 2.27 V 120 mV 6 pF +1 VDVDD - 0.4 FA V 0.4 V Maxim Integrated 3 MAX31865 RTD-to-Digital Converter AC Electrical Characteristics: SPI Interface (3.0V P VDD P 3.6V, TA = -40NC to +125NC, unless otherwise noted. Typical values are TA= +25NC, VDD = VDVDD = 3.3V.) (Notes 3 and 7) (Figure 1 and Figure 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data to SCLK Setup tDC (Notes 8, 9) 35 ns SCLK to Data Hold tCDH (Notes 8, 9) 35 ns SCLK to Data Valid tCDD (Notes 8, 9, 10) 80 ns SCLK Low Time tCL (Note 9) 100 ns SCLK High Time tCH (Note 9) 100 ns SCLK Frequency tCLK (Note 9) DC SCLK Rise and Fall tR, tF (Note 9) CS to SCLK Setup tCC (Note 9) 400 ns SCLK to CS Hold tCCH (Note 9) 100 ns CS Inactive Time tCWH (Note 9) 400 ns CS to Output High-Z tCDZ (Notes 8, 9) Address 01h or 02h Decoded to DRDY High tDRDYH After RTD register read access (Note 9) 5.0 MHz 200 ns 40 50 ns ns Note 2: All voltages are referenced to ground when common. Currents entering the IC are specified positive. Note 3: Limits are 100% production tested at TA= +25C and/or TA= +85C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 4: For 15-bit settling, a wait of at least 10.5 time constants of the input RC network is required. Max startup time is calculated with a 10k reference resistor and a 0.1F capacitor across the RTD inputs. Note 5: The first conversion after enabling continuous conversion mode takes a time equal to the single conversion time for the respective notch frequency. Note 6: Specified with no load on the bias pin as the sum of analog and digital currents. No active communication. If the RTD input voltage is greater than the input reference voltage, then an additional 400A IDD can be expected. Note 7: All timing specifications are guaranteed by design. Note 8: Measured at VIH = 0.7V x VDVDD or VIL = 0.3 x VDVDD and 10ms maximum rise and fall times. Note 9: Measured with 50pF load. Note 10: Measured at VOH = 0.7 x VDVDD or VOL = 0.3 x VDVDD. Measured from the 50% point of SCLK to the VOH minimum of SDO. www.maximintegrated.com Maxim Integrated 4 MAX31865 RTD-to-Digital Converter CS tCC SCLK tCDD tCDD tCDH tDC SDI A7 A6 A0 tCDZ SDO D7 D6 WRITE ADDRESS BYTE D1 D0 READ DATA BYTE NOTE: SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1. Figure 1. Timing Diagram: SPI Read Data Transfer CS tCWH tCC tR tCL tCCH tF SCLK tCDH tCH tCDH tDC SDI A7 A6 WRITE ADDRESS BYTE A0 D7 D0 WRITE DATA BYTE NOTE: SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1. Figure 2. Timing Diagram: SPI Write Data Transfer www.maximintegrated.com Maxim Integrated 5 MAX31865 RTD-to-Digital Converter Typical Operating Characteristics (VDD = VDVDD = 3.3V, TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE (ADC AUTO CONVERSION MODE) 3 IDD (mA) ANALOG IDD (BIAS PIN UNLOADED) 2 1 MAX31865 toc02 3 IDD (mA) 4 MAX31865 toc01 4 SUPPLY CURRENT vs. TEMPERATURE (ADC NORMALLY OFF MODE) ANALOG IDD (BIAS PIN UNLOADED) 2 1 DIGITAL IDD 0 DIGITAL IDD 0 0 -50 50 100 150 0 -50 50 100 150 TEMPERATURE (C) TEMPERATURE (C) LEAKAGE CURRENT PER PIN vs. TEMPERATURE (1 VOLT APPLIED TO FORCE+, FORCE2, RTDIN+, RTDIN- PINS) SINC FILTER OPERATION INPUT FREQUENCY vs. NOISE RESPONSE 0 NOISE RESPONSE (dB) 120 CURRENT (nA) 100 80 60 40 -20 50Hz 60Hz -40 -60 -80 20 0 -100 75 50 100 125 150 50 10 90 130 170 TEMPERATURE (C) INPUT NOISE FREQUENCY (Hz) ADC CONVERSION ERROR vs. RTD RESISTANCE (4k RREF, 4-WIRE CONNECTION) ADC CONVERSION ERROR vs. RTD RESISTANCE (400 RREF, 4-WIRE CONNECTION) MAX31865 toc05 -40C 0.244 0.244 +25C 0.1C ERROR 0 +100C -0.244 MAX31865 toc06 0.488 ERROR () 0.488 ERROR () MAX31865 toc04 20 MAX31865 toc03 140 +25C 0.1C ERROR +100C -0.244 -0.488 -40C 0 -0.488 0 500 1000 1500 2000 2500 3000 3500 RRTD () www.maximintegrated.com 0 50 100 150 200 250 300 350 RRTD () Maxim Integrated 6 MAX31865 RTD-to-Digital Converter SDO CS SCLK SDI TOP VIEW DGND Pin Configurations 15 14 13 12 11 GND1 16 N.C. 17 MAX31865 DRDY 18 DVDD 19 EP 3 4 5 ISENSOR FORCE+ 1 BIAS 2 REFIN- + REFIN+ VDD 20 10 GND2 9 FORCE- 8 RTDIN- 7 RTDIN+ 6 FORCE2 TQFN (5mm x 5mm) TOP VIEW + 20 N.C. DRDY 1 DVDD 2 19 GND VDD 3 18 DGND BIAS 4 REFIN+ 5 16 CS REFIN- 6 15 SCLK ISENSOR 7 14 SDI FORCE+ 8 13 GND2 FORCE2 9 12 FORCE- RTDIN+ 10 11 RTDIN- MAX31865 17 SDO SSOP www.maximintegrated.com Maxim Integrated 7 MAX31865 RTD-to-Digital Converter Pin Description PIN NAME FUNCTION TQFN SSOP 1 4 BIAS 2 5 REFIN+ Positive Reference Voltage Input. Connect to BIAS. Connect the reference resistor between REFIN+ and REFIN-. 3 6 REFIN- Negative Reference Voltage Input. Connect the reference resistor between REFIN+ and REFIN-. 4 7 ISENSOR Low Side of RREF. Connect to REFIN-. 5 8 FORCE+ High-Side RTD Drive. Connect to FORCE2 when using the 3-wire connection configuration. Protected to 45V. 6 9 FORCE2 Positive Input Used in 3-Wire Only. When in the 3-wire connection configuration, connect to FORCE+. When in the 2-wire or 4-wire connection configuration, connect to ground. Protected to 45V. 7 10 RTDIN+ Positive RTD Input. Protected to 45V. Bias Voltage Output (VBIAS) 8 11 RTDIN- Negative RTD Input. Protected to 45V. 9 12 FORCE- Low-Side RTD Return. Protected to 45V. 10 13 GND2 11 14 SDI 12 15 SCLK 13 16 CS 14 17 SDO 15 18 DGND Digital Ground 16 19 GND1 Analog Ground. Connect to GND2. 17 20 N.C. 18 1 DRDY Active-Low, Push-Pull, Data-Ready Output. DRDY goes low when a new conversion result is available in the data register. When a read operation of an RTD resistance data register occurs, DRDY returns high. 19 2 DVDD Digital Supply Voltage Input. Connect to a 3.3V power supply. Bypass to DGND with a 0.1F bypass capacitor. 20 3 VDD Analog Supply Voltage Input. Connect to a 3.3V power supply. Bypass to GND1 with a 0.1F bypass capacitor. -- -- EP www.maximintegrated.com Analog Ground. Connect to GND1. Serial-Data Input Serial-Data Clock Input Active-Low Chip Select. Set CS low to enable the serial interface. Serial-Data Output Do Not Connect Exposed Pad (Bottom Side of Package). Connect to GND1. Applies to TQFN package only. Maxim Integrated 8 MAX31865 RTD-to-Digital Converter Block Diagram VDD BIAS DVDD VDD VBIAS GENERATOR VDVDD REFIN+ SCLK SDO REFINSERIAL LOGIC DATA REGISTERS ISENSOR SDI CS FORCE+ DIGITAL LOGIC FORCE2 3-WIRE ONLY RTDIN+ 15-BIT ADC 45V PROTECTION RTDIN- 50/60Hz DIGITAL SINC FILTER DIGITAL COMPARATOR FOR FAULT DETECTION MASTER-INITIATED FAULT-DETECTION CYCLE ADC STATE MACHINE DRDY FORCE- MAX31865 GND2 www.maximintegrated.com GND1 DGND Maxim Integrated 9 MAX31865 RTD-to-Digital Converter Detailed Description Temperature Conversion Resistance temperature detectors (RTDs) are sensors whose resistance varies with temperature. Platinum is the most common, most accurate wire material; platinum RTDs are referred to as PT-RTDs. Nickel, copper, and other metals may also be used to make RTDs. Characteristics of platinum RTDs include a wide temperature range (to over +800NC), excellent accuracy and repeatability, and reasonable linearity. For PT-RTDs, the most common values for nominal resistance at 0NC are 100I and 1kI, though other values are available. The average slope between 0NC and +100NC is called alpha (). This value depends on the impurities and their concentrations in the platinum. The two most widely used values for alpha are 0.00385 and 0.00392, corresponding to the IEC 751 (PT100) and SAMA standards. The resistance vs. temperature curve is reasonably linear, but has some curvature, as described by the CallendarVan Dusen equation: R(T) = R0(1 + aT + bT2 + c(T - 100)T3) where: T = temperature (NC) R(T) = resistance at T R0 = resistance at T = 0NC IEC 751 specifies = 0.00385055 and the following Callendar-Van Dusen coefficient values: a = 3.90830 x 10-3 b = -5.77500 x 10-7 c = -4.18301 x 10-12 for -200NC P T P 0NC, 0 for 0NC P T P +850NC Figure 3 shows the curve of resistance vs. temperature for a PT100 RTD along with a straight-line approximation based on the slope between 0NC and +100NC. To measure the RTD's resistance, connect a reference resistor (RREF) and RTD in series and apply the bias voltage to the top of RREF as shown in the Typical www.maximintegrated.com PT100 RTD RESISTANCE vs. TEMPERATURE 450 400 350 RESISTANCE () The MAX31865 is a sophisticated RTD-to-digital converter with a built-in 15-bit analog-to-digital converter (ADC), input protection, a digital controller, an SPI-compatible interface, and associated control logic. The signal conditioning circuitry is optimized to work with PT100 through PT1000 RTDs. Thermistors are also supported. STRAIGHT-LINE APPROXIMATION 300 250 200 RTD RESISTANCE 150 100 50 0 -200 -100 0 100 200 300 400 500 600 700 TEMPERATURE (C) Figure 3. PT100 RTD resistance vs. temperature. Application Circuits. The reference resistor current also flows through the RTD. The voltage across the reference resistor is the reference voltage for the ADC. The voltage across the RTD is applied to the ADC's differential inputs (RTDIN+ and RTDIN-). The ADC therefore produces a digital output that is equal to the ratio of the RTD resistance to the reference resistance. A reference resistor equal to four times the RTD's 0NC resistance is optimum for a platinum RTD. Therefore, a PT100 uses a 400I reference resistor, and a PT1000 uses a 4kI reference resistor. A 2-wire connection (see the Typical Application Circuits) can give acceptable results when the RTD is located close to the MAX31865. Note that, for a PT100, series resistance of 0.4I causes an error of approximately 1NC. Therefore, as the cable length increases, the error due to cable resistance can become excessive. The 4-wire connection eliminates errors due to cable resistance by using separate force and sense leads. A 3-wire connection is a compromise approach that uses one less conductor than the 4-wire approach. To compensate for the voltage drop across the return wire, the voltage between FORCE+ and RTDIN+ is subtracted from (RTDIN+ - RTDIN-). This is accomplished using the FORCE2 sampling input. If the cable resistances are wellmatched, the error due to cable resistance is cancelled. Select 3-wire operation by setting the 3-wire bit in the Configuration register to 1. Maxim Integrated 10 MAX31865 Linearizing Temperature Data For a temperature range of -100NC to +100NC, a good approximation of temperature can be made by simply using the RTD data as shown below: Temperature (NC) (ADC code/32) - 256 This equation gives 0NC error at 0NC, -1.75NC error at -100NC, and -1.4NC error at +100NC (assuming an IEC751 RTD and RREF equal to four times the 0 NC RTD resistance). For high precision, use the CallendarVan Dusen equation (in the Temperature Conversion section) or a lookup table to correct the RTD's predictable nonlinearity. RTD-to-Digital Converter detected only when a fault detection cycle is requested by the master. During a fault detection cycle the MAX31865 has the ability to disconnect the FORCE- input from its GND2 return path by means of and internal analog switch. The conditions that generate a fault are listed below, see Figure 4 for a fault detection flowchart. * Overvoltage (> VDD) or undervoltage (< GND1) condition on FORCE+, FORCE2, RTDIN+, RTDIN-, or FORCE- pins * Analog-to-Digital Converter (ADC) The ADC has fully differential analog inputs, RTDIN+ and RTDIN-, and fully differential reference inputs, REFIN+ and REFIN-. The output code represents the ratio between the analog input voltage and the reference voltage. A negative input voltage produces an output code of 0. An input voltage greater than the reference voltage produces a full-scale output. Input noise is attenuated by a third-order digital "sinc" filter. Noise from 50Hz or 60Hz power sources (including harmonics of the ac power's fundamental frequency) is attenuated by 82dB. Fault Detection and Input Protection The MAX31865 detects a variety of faults that can occur with the external RTD and 2-, 3-, or 4-wire cables. Some faults are detected on every conversion, while others are www.maximintegrated.com Detected every ADC conversion Greater than or equal to threshold high conversion result Using Thermistors Other resistive sensors, such as thermistors (NTCs or PTCs) may be used. Select an RREF that is greater than or equal to the sensor's maximum resistance over the temperature range of interest. The output data is the ratio of the sensor resistance to the reference resistance. Detected at any point in time Less than or equal to threshold low conversion result * Detected on demand by initiating a Fault Detection Cycle (Configuration Register bits (D[3:2]) VREFIN- > 0.85 x VBIAS VREFIN- < 0.85 x VBIAS when FORCE- input switch is open VRTDIN- < 0.85 x VBIAS when FORCE- input switch is open FORCE+, FORCE2, FORCE-, RTDIN+, and RTDIN- are protected against input voltages up to Q45V. Signals applied to these pins are gated by analog switches that open when the applied voltage is typically greater than VDD + 100mV or less than GND1 - 400mV. Note that when a voltage fault occurs, the protection circuits may allow approximately 350FA of current flow. This faultinduced leakage current does not cause any damage to the MAX31865. When an overvoltage or undervoltage condition is detected, bit D2 of the Fault Status register is set and the ADC halts conversion updates until the fault is no longer detected, at which point conversions resume. Maxim Integrated 11 MAX31865 RTD-to-Digital Converter FAULT DETECTION ALWAYS ACTIVE FAULT DETECTION MONITOR PINS IS FORCE+, FORCE2, FORCE-, RTDIN+, RTDIN-, PINS > VDD OR < GND EVERY CONVERSION FAULT DETECTION N CONVERSION INITIATED PERFORM CONVERSION IS RTD RESISTANCE VALUE > HIGH THRESHOLD REGISTER Y IS RTD RESISTANCE VALUE < LOW THRESHOLD REGISTER N Y Y PROTECT PINS AGAINST 45V N SET BIT D6 OF FAULT STATUS REGISTER SET BIT D7 OF FAULT STATUS REGISTER SET BIT D2 OF FAULT STATUS REGISTER SET BIT D0 OF RTD DATA LSB REGISTER ADC HALTS UPDATES SET BIT D0 OF RTD DATA LSB REGISTER MASTER-INITIATED FAULT-DETECTION CYCLE - AUTOMATIC MODE MASTER WRITES 100X010Xb TO CONFIGURATION REGISTER FORCE-INPUT SWITCH REMAINS CLOSED IS VREFIN> 0.85 x VBIAS 100s DELAY N 100s DELAY OPEN FORCEINPUT SWITCH IS VREFIN< 0.85 x VBIAS 210s DELAY Y N Y SET BIT D5 OF FAULT STATUS REGISTER SET BIT D4 OF FAULT STATUS REGISTER SET BIT D0 OF RTD DATA LSB REGISTER SET BIT D0 OF RTD DATA LSB REGISTER CONFIGURATION REGISTER SET TO 100X000Xb TO END FAULT DETECTION CYCLE FORCE-INPUT SWITCH CLOSED N IS RTDIN< 0.85 x VBIAS 100s DELAY Y SET BIT D3 OF FAULT STATUS REGISTER SET BIT D0 OF RTD DATA LSB REGISTER MASTER-INITIATED FAULT-DETECTION CYCLE - MANUAL MODE MASTER WRITES 100X100Xb TO CONFIGURATION REGISTER FORCE-INPUT SWITCH REMAINS CLOSED 100s DELAY IS VREFIN> 0.85 x VBIAS N 100s DELAY OPEN FORCEINPUT SWITCH Y DID MASTER WRITE 100X110Xb TO CONFIGURATION REGISTER Y IS VREFIN< 0.85 x VBIAS 100s DELAY N Y N SET BIT D5 OF FAULT STATUS REGISTER SET BIT D4 OF FAULT STATUS REGISTER SET BIT D0 OF RTD DATA LSB REGISTER SET BIT D0 OF RTD DATA LSB REGISTER END FAULT DETECTION CYCLE CONFIGURATION REGISTER SET TO 100X000Xb TO FORCE-INPUT SWITCH CLOSED N IS RTDIN< 0.85 x VBIAS 100s DELAY Y SET BIT D3 OF FAULT STATUS REGISTER SET BIT D0 OF RTD DATA LSB REGISTER Figure 4. Fault Detection Flowcharts www.maximintegrated.com Maxim Integrated 12 MAX31865 RTD-to-Digital Converter Internal Registers Conversion Mode (D6) Communication is through eight 8-bit registers that contain conversion, status, and configuration data. All programming is done by selecting the appropriate address of the desired register location. Table 1 illustrates the addresses for the registers. Write 1 to this bit to select automatic conversion mode, in which conversions occur continuously at a 50/60Hz rate. Write 0 to this bit to exit automatic conversion mode and enter the "Normally Off" mode. 1-shot conversions may be initiated from this mode. The registers are accessed using the 0Xh addresses for reads and the 8Xh addresses for writes. Data is read from or written to the registers MSB first. 1-Shot (D5) When the conversion mode is set to "Normally Off", write 1 to this bit to start a conversion. This causes a single resistance conversion to take place. The conversion is triggered when CS goes high after writing a 1 to this bit. Note that if a multibyte write is performed, the conversion is triggered when CS goes high at the end of the transaction. If VBIAS is on (as selected by the Configuration Register), the RTD voltage is sampled when CS goes high and the conversion begins. Note that if VBIAS is off (to reduce supply current between conversions), any filter capacitors at the RTDIN inputs need to charge before an accurate conversion can be performed. Therefore, enable VBIAS and wait at least 10.5 time constants of the input RC network plus an additional 1ms before initiating the conversion. Note that a single conversion requires approximately 52ms in 60Hz filter mode or 62.5ms in 50Hz filter mode to complete. 1-Shot is a self-clearing bit. Configuration Register (00h) The configuration register selects the conversion mode (automatic or triggered by the 1-shot command), enables and disables BIAS pin output voltage VBIAS, initiates 1-shot conversions, selects the RTD connection (either 3-wire or 2-wire/4-wire), initiates a full fault detection cycle, clears the Fault Status register, and selects the filter notch frequencies. The effects of the configuration bits are described below. BIAS (D7) When no conversions are being performed, VBIAS may be disabled to reduce power dissipation. Write 1 to this bit to enable VBIAS before beginning a single (1-Shot) conversion. When automatic (continuous) conversion mode is selected, VBIAS remains on continuously. Table 1. Register Addresses and POR State READ ADDRESS (HEX) WRITE ADDRESS (HEX) POR STATE READ/WRITE Configuration REGISTER NAME 00h 80h 00h R/W RTD MSBs 01h -- 00h R RTD LSBs 02h -- 00h R High Fault Threshold MSB 03h 83h FFh R/W High Fault Threshold LSB 04h 84h FFh R/W Low Fault Threshold MSB 05h 85h 00h R/W Low Fault Threshold LSB 06h 86h 00h R/W Fault Status 07h -- 00h R Table 2. Configuration Register Definition D7 D6 D5 D4 VBIAS 1 = ON 0 = OFF Conversion mode 1 = Auto 0 = Normally off 1-shot 1 = 1-shot (auto-clear) 3-wire 1 = 3-wire RTD 0 = 2-wire or 4-wire www.maximintegrated.com D3 D2 Fault Detection Cycle Control (see Table 3) D1 D0 Fault Status Clear 1 = Clear (auto-clear) 50/60Hz filter select 1 = 50Hz 0 = 60Hz Maxim Integrated 13 MAX31865 RTD-to-Digital Converter 3-Wire (D4) Fault Detect Cycle bits (D[3:2]) self-clear to 00b upon completion. Write 1 to this bit when using a 3-wire RTD connection. In this mode the voltage between FORCE+ and RTDIN+ is subtracted from (RTDIN+ - RTDIN-) to compensate for the IR errors caused by using a single wire for the FORCEand RTDIN- connections. When using 2-wire or 4-wire connections, write 0 to this bit. To enter the manual fault detection cycle, first ensure that VBIAS has been on for at least 5 time constants. Next, write 100X100Xb to the Configuration register. The ADC is now in "Normally Off" mode. The MAX31865 checks for faults while the FORCE- input switch is closed, and when the check completes, the FORCE-input switch opens. The Fault Detect Cycle bits (D[3:2]), remain set to 10b. Again, wait at least 5 time constants, and then write 100X110Xb to the Configuration register. The MAX31865 now checks for faults while the FORCE- inputs switch is open; when the check completes, the FORCE- input switch closes and the Fault Detect Cycle bits (D[3:2]) self-clear to 00b. Note that if 1 is written to D5 (1-Shot) and D2 or D3 in a single write, both commands are ignored. If 100X110Xb is set without a prior initiation of the first manual step (setting 100X100Xb), the automatic fault detection mode is run instead. Fault Detection Cycle (D3:D2) The master initiated fault detection cycle has two modes of operation, manual and automatic mode timing. If the external RTD interface circuitry includes an input filter with a time constant greater than 100Fs, the fault detection cycle timing should be controlled in the manual mode operation. The fault detection cycle checks for three faults by making the following voltage comparisons and setting the associated bits in the Fault Status Register: 1) Is the voltage at REFIN- greater than 85% x VBIAS? (Fault Status Register bit D5) 2) Is the voltage at REFIN- less than 85% x VBIAS when FORCE- input switch is open? (Fault Status Register bit D4) Fault Status Clear (D1) Write a 1 to this bit while writing 0 to bits D5, D3, and D2 to return all fault status bits (D[7:2]) in the Fault Status Register to 0. Note that bit D2 in the Fault Register, and subsequently bit D0 in the RTD LSB register may be set again immediately after resetting if an over/undervoltage fault persists. The fault status clear bit D1, self-clears to 0. 3) Is the voltage at RTDIN- less than 85% x VBIAS when FORCE- input switch is open? (Fault Status Register bit D3) Note: All voltages are referenced to GND1. 50/60Hz (D0) The Applications Information provides tables for decoding possible causes of set fault status bits. This bit selects the notch frequencies for the noise rejection filter. Write 0 to this bit to reject 60Hz and its harmonics; write 1 to this bit to reject 50Hz and its harmonics. Note: Do not change the notch frequency while in auto conversion mode. To enter the automatic fault detection cycle, write 100X010Xb to the Configuration register. The ADC is now in "Normally Off" mode. The automatic fault detection cycle inserts 100Fs delays before checking for faults, thereby allowing the external input filter to settle. The Table 3. Fault-Detection Cycle Control Bits D3 D2 CONFIGURATION REGISTER WRITE (BINARY) WRITE ACTION READ MEANING 0 0 XXXX00XXb No action Fault detection finished 0 1 100X010Xb Fault detection with automatic delay Automatic fault detection still running Manual cycle 1 still running; waiting for user to write 11 Manual cycle 2 still running 1 0 100X100Xb Run fault detection with manual delay (cycle 1) 1 1 100X110Xb Finish fault detection with manual delay (cycle 2) X = Don't care www.maximintegrated.com Maxim Integrated 14 MAX31865 RTD-to-Digital Converter RTD Resistance Registers (01h-02h) Two 8-bit registers, RTD MSBs and RTD LSBs, contain the RTD resistance data. The data format is shown in Table 4. The data format is simply the 15-bit ratio of RTD resistance to reference resistance. D0 of the RTD LSBs register is a Fault bit that indicates whether any RTD faults have been detected. Table 4. RTD Resistance Registers Definition REGISTER Bit RTD MSBS (01h) REGISTER RTD LSBS (02h) REGISTER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RTD Resistance Data MSB -- -- -- -- -- -- -- -- -- -- -- -- -- LSB Fault Bit Weighting 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 -- 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 -- Decimal Value 16384 8192 Table 5. RTD Resistance-Data Relationship RRTD/RREF BINARY HEX DECIMAL RTD MSBs (01h) RTD LSBs (02h) RTD MSBs (01h) RTD LSBs (02h) 0.025 0000 0110 0110 0110b 06h 66h 819 0.125 0010 0000 0000 0000b 20h 00h 4096 0.25 0100 0000 0000 0000b 40h 00h 8192 0.50 1000 0000 0000 0000b 80h 00h 16,384 0.75 1100 0000 0000 0000b C0h 00h 24,576 0.999 1111 1111 Note: D0 ("Fault") is assumed to be 0. 1111 1110b FFh FEh 32,767 www.maximintegrated.com Maxim Integrated 15 MAX31865 RTD-to-Digital Converter Fault Threshold Registers (03h-06h) The High Fault Threshold and Low Fault Threshold registers select the trip thresholds for RTD fault detection. The results of RTD conversions are compared with the values in these registers to generate the "Fault" (D[7:6]) bits in the Fault Status register. The RTD Data Registers, High Fault Threshold Registers, and Low Fault Threshold Registers all have the same format. The RTD High bit in the Fault Status Register is set if the RTD resistance register value is greater than or equal to the value in the High Fault Threshold register. The POR value of the High Fault Threshold register is FFFFh. The RTD Low bit in the Fault Status Register is set if the RTD resistance value is less than or equal to the value in the Low Fault Threshold register. The POR value of the Low Fault Threshold register is 0000h. Fault Status Register (07h) The Fault Status register latches any detected fault bits; writing a 1 to the Fault Status Clear bit in the Configuration Register returns all fault status bits to 0. Serial Interface The MAX31865 supports SPI modes 1 and 3. Four pins are used for SPI-compatible communications: SDO (serial-data out), SDI (serial-data in), CS (chip select), and SCLK (serial clock). SDI and SDO are the serialdata input and output pins for the devices, respectively. The CS input initiates and terminates a data transfer. SCLK synchronizes data movement between the master (microcontroller) and the slave (MAX31865). The serial clock (SCLK), which is generated by the microcontroller, is active only when CS is low and dur ing address and data transfer to any device on the SPI Table 6. Fault Threshold Registers Definition REGISTER Bit HIGH FAULT THRESHOLD MSB (03h) REGISTER LOW FAULT THRESHOLD MSB (05h) REGISTER HIGH FAULT THRESHOLD LSB (04h) REGISTER LOW FAULT THRESHOLD LSB (06h) REGISTER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RTD Resistance Data MSB -- -- -- -- -- -- -- -- -- -- -- -- -- LSB X Bit Weighting 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 -- 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 -- Decimal 16384 Value X = Don't care Table 7. Fault Status Register Definition D7 RTD High Threshold X = Don't care D6 D5 D4 D3 D2 D1 D0 RTD Low Threshold REFIN- > 0.85 x VBIAS REFIN- < 0.85 x VBIAS (FORCE- open) RTDIN- < 0.85 x VBIAS (FORCE- open) Overvoltage/ undervoltage fault x x www.maximintegrated.com Maxim Integrated 16 MAX31865 RTD-to-Digital Converter bus. The inactive clock polarity is programmable in some microcontrollers. The MAX31865 automatically accommodates either clock polarity by sampling SCLK when CS becomes active to determine the polarity of the inactive clock. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted out on the shift edge (see Table 8 and Figure 5). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight, MSB first. Address and Data Bytes Address and data bytes are shifted MSB-first into the serial-data input (SDI) and out of the serial-data output (SDO). Any transfer requires the address of the byte to specify a write or a read, followed by one or more bytes of data. Data is transferred out of the SDO for a read opera tion and into the SDI for a write operation. The address byte is always the first byte transferred after CS is driven low. The MSB (A7) of this byte determines whether the following byte is written or read. If A7 is 0, one or more byte reads follow the address byte. If A7 is 1, one or more byte writes follow the address byte. For a single-byte transfer, 1 byte is read or written and then CS is driven high (see Figure 6 and Figure 7). For a multiple-byte transfer, multiple bytes can be read or written after the address has been written (see Figure 8). The address continues to increment through all memory locations as long as CS remains low. If data continues to be clocked in or out, the address loops from 7Fh/FFh to 00h/80h. Invalid memory addresses report an FFh value. Attempting to write to a read-only register results in no change to that register's contents. Table 8. Function Table MODE Disable Reset CS High Write Low Read Low SCLK SDI SDO Input disabled Input disabled High impedance Data bit latch High impedance X Next data bit shift** CPOL = 1*, SCLK rising CPOL = 0, SCLK falling CPOL = 1, SCLK falling CPOL = 0, SCLK rising Note: CPHA bit polarity must be set to 1. *CPOL is the clock polarity bit that is set in the control register of the microcontroller. **SDO remains at high impedance until 8 bits of data are ready to be shifted out during a read. CS CPOL = 1 SHIFT INTERNAL STROBE SHIFT INTERNAL STROBE SCLK CS CPOL = 0 SCLK NOTE: CPOL IS A BIT THAT IS SET IN THE MICROCONTROLLER'S CONTROL REGISTER. Figure 5. Serial Clock as a Function of Microcontroller Clock Polarity (CPOL) www.maximintegrated.com Maxim Integrated 17 MAX31865 RTD-to-Digital Converter CS SCLK SDI A7 SDO A6 A5 A4 A3 A2 A1 A0 HIGH-Z D7 D6 D5 D4 D3 D2 D1 D0 Figure 6. SPI Single-Byte Read CS SCLK SDI A7 SDO A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH-Z Figure 7. SPI Single-Byte Write CS SCLK WRITE SDI ADDRESS BYTE SDI ADDRESS BYTE DATA BYTE 0 DATA BYTE 1 DATA BYTE N DATA BYTE 0 DATA BYTE 1 DATA BYTE N READ SDO Figure 8. SPI Multibyte Transfer www.maximintegrated.com Maxim Integrated 18 MAX31865 RTD-to-Digital Converter DRDY The DRDY output goes low when a new conversion result is available in the RTD Data Registers. When a readoperation of the RTD Data Registers completes, DRDY returns high. Applications Information For operation in noisy environments, a filter capacitor may be placed across the RTDIN+ and RTDIN- inputs. After an overvoltage or undervoltage fault, after a fault detection cycle, or after enabling VBIAS, always allow for the settling time of the input filter before restarting the ADC. A delay time of at least five time constants plus an additional 1ms (for the protection devices to stabilize) is recommended to achieve specified accuracy. Converting RTD Data Register Values to Temperature The ratiometric ADC conversion results found in the RTD Data Registers can be converted to temperature with a few calculations. First, the Resistance of the RTD needs to be determined with the following equation: RRTD = (ADC Code x RREF)/215 DRDY RTD REGISTER CONTENTS CONVERSION n CONVERSION n+1 CONVERSION n+2 SDI RTD DATA ADDRESS SDO RTD DATA CS Figure 9. DRDY Operation www.maximintegrated.com Maxim Integrated 19 MAX31865 RTD-to-Digital Converter ADC Code = 15-bit ADC results from RTD Data registers (01h-02h) determine temperature by either calculations or lookup tables. RREF = Resistance of the reference resistor In the typical case of a PT100 RTD with a 400I high precision low drift reference resistor, Table 9 shows examples of temperature and resistance values with the corresponding ADC code results. Once the resistance of the RTD is known, the well-defined resistive properties of the selected RTD can be used to Table 9. Temperature Example for PT100 with 400 RREF TEMPERATURE (C) RTD RESISTANCE () RTD DATA REG (01h-02h) (hex) ADC CODE (dec) ADC CODE/32-256 (C) -200 -175 -150 -125 -100 -75 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 225 250 18.52 29.22 39.72 50.06 60.26 70.33 80.31 84.27 88.22 92.16 96.09 100.00 103.90 107.79 111.67 115.54 119.40 123.24 127.08 130.90 134.71 138.51 142.29 146.07 149.83 153.58 157.33 161.05 164.77 168.48 172.17 175.86 185.01 194.10 0BDAh 12B4h 196Ch 200Ah 2690h 2D04h 3366h 35EEh 3876h 3AFCh 3D7Eh 4000h 4280h 44FCh 4778h 49F2h 4C6Ah 4EE0h 5154h 53C6h 5636h 58A4h 5B12h 5D7Ch 5FE4h 624Ch 64B0h 6714h 6974h 6BD4h 6E30h 708Ch 7668h 7C3Ah 1517 2394 3254 4101 4936 5762 6579 6903 7227 7550 7871 8192 8512 8830 9148 9465 9781 10096 10410 10723 11035 11346 11657 11966 12274 12582 12888 13194 13498 13802 14104 14406 15156 15901 -208.59 -181.19 -154.31 -127.84 -101.75 -75.94 -50.41 -40.28 -30.16 -20.06 -10.03 0.00 10.00 19.94 29.88 39.78 49.66 59.50 69.31 79.09 88.84 98.56 108.28 117.94 127.56 137.19 146.75 156.31 165.81 175.31 184.75 194.19 217.63 240.91 www.maximintegrated.com Maxim Integrated 20 MAX31865 RTD-to-Digital Converter Table 9. Temperature Example for PT100 with 400 RREF (continued) TEMPERATURE (C) RTD RESISTANCE () RTD DATA REG (01h-02h) (hex) ADC CODE (dec) ADC CODE/32-256 (C) 275 300 325 350 375 400 425 450 475 500 525 550 203.11 212.05 220.92 229.72 238.44 247.09 255.67 264.18 272.61 280.98 289.27 297.49 81FEh 87B6h 8D64h 9304h 989Ah 9E24h A3A2h A914h AE7Ah B3D4h B922h BE64h 16639 17371 18098 18818 19533 20242 20945 21642 22333 23018 23697 24370 263.97 286.84 309.56 332.06 354.41 376.56 398.53 420.31 441.91 463.31 484.53 505.56 Detecting RTDIN+ Cable Faults In the 3- and 4-wire RTD connection configuration, a broken or disconnected RTDIN+ cable results in an unbiased ADC+ input into the MAX31865. This causes unpredictable ADC conversion results, which can be influenced by PCB layout, external circuit noise, and ambient temperature. This cable fault condition can go undetected depending upon the values set in the fault threshold registers. If this condition is of interest, add a 10M resistor from the RTDIN+ pin to the BIAS pin. Doing so results in a full-scale RTD resistance measurement if the RTDIN+ lead is broken or disconnected. Decoding RTD and Cable Fault Conditions An open RTD element or a short across the RTD element are detected on every conversion based on the resistance data. An open RTD element results in a full-scale reading. Set the threshold for open RTD element detection using the High Fault Threshold registers. If the conversion result is greater than or equal to the threshold value, the RTD High bit in the Fault Status register is set at the end of the www.maximintegrated.com conversion. An open RTD element can also be detected on demand by testing for VREFIN- > 0.85 x VBIAS. A shorted RTD element produces a conversion result near zero. Set the threshold for shorted RTD detection in the Low Fault Threshold registers. Table 10, Table 11, and Table 12 summarize how RTD and cable faults are detected for 2-, 3-, and 4-wire setups and provide a description for the most common cause. Fault Status bits are latched until the Fault Clear bit in the Configuration register is set. This allows intermittent faults to be captured. Power-Supply Decoupling To achieve the best results when using the device, decouple the VDD and DVDD power supplies with a 0.1F capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Maxim Integrated 21 MAX31865 RTD-to-Digital Converter Table 10. Decoding RTD Faults for 2-Wire Setups When Fault Bit in RTD Data LSB Register = 1 FAULT STATUS BIT SET D7 D6 DESCRIPTION OF POSSIBLE CAUSE Open RTD element Shorted RTD element RTDIN+ shorted low CONDITION DETECTED Measured resistance greater than High Fault Threshold value Full scale Measured resistance less than Low Fault Threshold value Near zero Open RTD D5 RTDIN+ shorted high Full scale VREFIN- > 0.85 x VBIAS RTDIN- shorted high D4 D3 D2 RTDIN- shorted low RTDIN- shorted low RTDIN+ shorted low Overvoltage or undervoltage fault DESCRIPTION OF RESULTING DATA Indeterminate Indeterminate VREFIN- < 0.85 x VBIAS (FORCE- open) VRTDIN- < 0.85 x VBIAS (FORCE- open) Any protected input voltage >VDD or <GND1 Appear to be valid Appear to be valid Near zero Indeterminate Table 11. Decoding RTD Faults for 3-Wire Setups When Fault Bit in RTD Data LSB Register = 1 FAULT STATUS BIT SET DESCRIPTION OF POSSIBLE CAUSE CONDITION DETECTED DESCRIPTION OF RESULTING DATA Open RTD element D7 RTDIN+ shorted high and not connected to RTD Force+ shorted high and connected to RTD Measured resistance greater than High Fault Threshold value Full scale Measured resistance less than Low Fault Threshold value Near zero RTDIN+ shorted to RTDIND6 RTDIN+ shorted low and not connected to RTD Force+ shorted low Open RTD element Full scale Force+ shorted high and connected to RTD D5 Force+ unconnected VREFIN- > 0.85 x VBIAS Force+ shorted high and not connected to RTD Indeterminate RTDIN- shorted high D4 RTDIN- shorted low VREFIN- < 0.85 x VBIAS (FORCE- open) Appear to be valid Force+ shorted low D3 RTDIN+ shorted low and connected to RTD VRTDIN- < 0.85 x VBIAS (FORCE- open) RTDIN- shorted low D2 Overvoltage or undervoltage fault www.maximintegrated.com Near zero Appear to be valid Any protected input voltage >VDD or < GND1 Indeterminate Maxim Integrated 22 MAX31865 RTD-to-Digital Converter Table 12. Decoding RTD Faults for 4-Wire Setups When Fault Bit in RTD Data LSB Register = 1 FAULT STATUS BIT SET DESCRIPTION OF POSSIBLE CAUSE CONDITION DETECTED DESCRIPTION OF RESULTING DATA Open RTD element D7 RTDIN+ shorted high and not connected to RTD Force+ shorted high and connected to RTD Measured resistance greater than High Fault Threshold value Full scale Measured resistance less than Low Fault Threshold value Near zero RTDIN+ shorted to RTDIND6 RTDIN+ shorted low and not connected to RTD RTDIN- shorted high and not connected to RTD Force+ shorted low Open RTD element Full scale Force+ shorted high and connected to RTD Force- unconnected Force+ unconnected D5 Force+ shorted high and not connected to RTD VREFIN- > 0.85 x VBIAS Force- shorted high and not connected to RTD Indeterminate Force- shorted high and connected to RTD Force- shorted low and not connected to RTD D4 Force- shorted low and connected to RTD RTDIN- shorted low and connected to RTD Indeterminate VREFIN- < 0.85 x VBIAS (FORCE- open) Appear to be valid Force+ shorted low Near zero RTDIN+ shorted low and connected to RTD D3 RTDIN- shorted low and connected to RTD VRTDIN- < 0.85 x VBIAS (FORCE- open) Appear to be valid RTDIN- shorted low and not connected to RTD Force- shorted low D2 Overvoltage or undervoltage fault www.maximintegrated.com Any protected input voltage >VDD or < GND1 Indeterminate Maxim Integrated 23 MAX31865 RTD-to-Digital Converter Typical Application Circuits (continued) VDD VDD 2-WIRE SENSOR CONNECTION 0.1F VDD DVDD 0.1F BIAS REFIN+ DRDY REFIN- SDI HOST INTERFACE RREF ISENSOR MAX31865 SCLK FORCE+ CS FORCE2 SDO RTDIN+ N.C. CI* RTD DGND GND2 GND1 RTDINFORCE- *CI = 10nF FOR 1k RTD 100nF FOR 100 RTD 3-WIRE SENSOR CONNECTION VDD VDD VDD 0.1F DVDD 0.1F BIAS REFIN+ DRDY REFIN- SDI HOST INTERFACE SCLK RREF ISENSOR MAX31865 RCABLE FORCE+ CS FORCE2 SDO RTDIN+ N.C. RCABLE CI* RTD RCABLE www.maximintegrated.com DGND GND2 GND1 RTDINFORCE- Maxim Integrated 24 MAX31865 RTD-to-Digital Converter Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX31865AAP+ -40C to +125C 20 SSOP MAX31865AAP+T -40C to +125C 20 SSOP MAX31865ATP+ -40C to +125C 20 TQFN-EP* MAX31865ATP+T -40C to +125C 20 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. www.maximintegrated.com For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 TQFN-EP T2055+5 21-0140 90-0010 A20+1 21-0056 90-0094 20 SSOP Maxim Integrated 25 MAX31865 RTD-to-Digital Converter Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 10/12 Initial release -- 1 1/15 Revised Benefits and Features section 1 2 5/15 Added the SSOP package to the data sheet and updated input voltage protection as 45V. 3 7/15 Updated Table 6 DESCRIPTION 1, 2, 7, 10, 11, 24 16 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2015 Maxim Integrated Products, Inc. 26