MPC17511AEL - Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

Document Number: MPC17511A

Rev. 5.0, 9/2008

Freescale Semiconductor

Technical Data

1.0 A 6.8 V H-Bridge Motor

Driver IC

The 17511A is a monolithic H-Bridge designed to be used in

portable electronic applications to control small DC motors or bipolar

step motors. End applications include head positioners (CDROM or

disk drive), camera focus motors, and camera shutter solenoids.

The 17511A can operate efficiently with supply voltages as low as

2.0V to as high as 6.8V. Its low RDS(ON) H-Bridge output MOSFETs

(0.46 Ω typical) can provide continuos motor drive currents of 1.0A

and handle peak currents up to 3.0A. It is easily interfaced to low-cost

MCUs via parallel 3.0V- or 5.0V- compatible logic. The device can be

pulse width modulated (PWM-ed) at up to 200 kHz.

This device contains an integrated charge pump and level shifter

(for gate drive voltages), integrated shoot-through current protection

(cross-conduction suppression logic and timing), and undervoltage

detection and shutdown circuitry.

The 17511A has four operating modes: Forward, Reverse, Brake,

and Tri-Stated (High Impedance).

Features

• 2.0V to 6.8V Continuous Operation

• Output Current 1.0 A(DC), 3.0A (Peak)

• MOSFETs < 600 mΩ RDS(ON) @ 25°C Guaranteed

• 3.0V/ 5.0V TTL- / CMOS-Compatible Inputs

• PWM Frequencies up to 200 kHz

• Undervoltage Shutdown

• Cross-Conduction Suppression

• Low Power Consumption

• Pb-Free Packaging Designated by Suffix Codes EV and EP

Figure 1. 17511A Simplified Application Diagram

H-BRIDGE MOTOR DRIVER IC

EV SUFFIX (PB-FREE)

98ASA10614D

16-PIN VMFP

17511A

ORDERING INFORMATION

Device Temperature

Range (TA)Package

MPC17511AEV

-20°C to 65°C

16 VMFP

MPC17511AEV/EL

MPC17511AEP

24 QFN

MPC17511AEP/ R2

EP SUFFIX (PB-FREE)

98ARL10577D

24-PIN QFN

VDD

C1L

C1H

C2L

C2H

CRES

GIN

IN1

IN2

GND

GOUT

OUT1

OUT2

5.0V

17511A

MCU

Motor

5.0V

Analog Integrated Circuit Device Data

2Freescale Semiconductor

17511A

INTERNAL BLOCK DIAGRAM

Figure 2. 17511A Simplified Internal Block Diagram

C2H

C1L

GOUT

OUT1

OUT2

PGND

LGND

C2L

C1H

CRES

IN1

IN2

Level

Control

Logic

Shifter

Predriver

Charge Pump

Low-

Voltage

Shutdown

GIN

Analog Integrated Circuit Device Data

Freescale Semiconductor 3

17511A

PIN CONNECTIONS

Figure 3. VMFP Pin Connections

Table 1. VMFP Pin Function Description

Number Pin Name Formal Name Definition

1 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole).

2C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole).

3C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole).

4VM Motor Drive Power Supply Driver power supply voltage input pin.

5 VDD Logic Supply Control circuit power supply pin.

6IN1 Input Control 1 Control signal input 1

7IN2 Input Control 2 Control signal input 2.

8EN Enable Control Enable control signal input pin.

9LGND Logic Ground Logic ground pin.

10 GIN Gate Driver Input LOW = True control signal for GOUT pin.

11 OUT1 H-Bridge Output 1 Driver output 1 (right half of H-Bridge).

12 PGND Power Ground Driver ground pin.

13 OUT2 H-Bridge Output 2 Driver output 2 (left half of H-Bridge).

14 GOUT Gate Driver Output Output gate driver signal to external MOSFET switch.

15 CRES Charge Pump Output Capacitor

Connection

Charge pump reservoir capacitor pin.

16 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole).

CRES

GOUT

OUT2

PGND

OUT1

GIN

LGND

C2L

C1H

C1L

IN1

IN2

C2H

Analog Integrated Circuit Device Data

4Freescale Semiconductor

17511A

PIN CONNECTIONS

Figure 4. QFN Pin Connections

Table 2. QFN Pin Function Description

Number Pin Name Formal Name Definition

1, 2, 3, 4 VM Motor Drive Power Supply Driver power supply voltage input pin.

5, 6, 13, 18 NC No Connect This pin is not used.

7VDD Logic Supply Control circuit power supply pin.

8IN1 Logic Input Control 1 Control signal input 1.

9IN2 Logic Input Control 2 Control signal input 2.

10 EN Enable Control Enable control signal input pin.

11 LGND Logic Ground Logic ground pin.

12 GIN Gate Driver Input LOW = True control signal for GOUT pin.

14 OUT1 Output 1 Driver output 1 (right half of H-Bridge).

15, 16 PGND Power Ground Driver ground pin.

17 OUT2 Output 2 Driver output 2 (left half of H-Bridge).

19 GOUT Gate Driver Output Output gate driver signal to external MOSFET switch.

20 CRES Pre-Driver Power Supply Pre-driver circuit power supply pin.

21 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole).

22 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole).

23 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole).

24 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole).

8 9 10 11 12

IN2

LGND

GIN

IN1

PGND

OUT1

OUT2

2021222324

GOUT

C2H

C2L

C1H

C1L

CRES

Analog Integrated Circuit Device Data

Freescale Semiconductor 5

17511A

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent

damage to the device.

Rating Symbol Value Unit

Motor Supply Voltage VM-0.5 to 8.0 V

Charge Pump Output Voltage VCRES -0.5 to 14.0 V

Logic Supply Voltage VDD -0.5 to 7.0 V

Signal Input Voltage (EN, IN1, IN2, GIN) VIN -0.5 to VDD

+ 0.5 V

Driver Output Current

Continuous

Peak (1)

IOPK

1.0

3.0

ESD Voltage (2)

Human Body Model

Machine Model

VESD1

VESD2

±1800

± 100

Storage Temperature Range TSTG -65 to 150 °C

Operating Ambient Temperature TA-20 to 65 °C

Operating Junction Temperature TJ-20 to 150 °C

Thermal Resistance (3)

24 Pin QFN

16 Pin VMFP

RθJA

150

°C/W

Power Dissipation (4)

24 Pin QFN

16 Pin VMFP

2500

830

Soldering Temperature (5) TSOLDER 260 °C

Peak Package Reflow Temperature During Reflow (6), (7) TPPRT Note 7 °C

Notes

1. TA = 25°C, 10 ms pulse width at 200 ms intervals.

2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

3. QFN24: 45 x 30 x 1 [mm] glass EPOXY board mount. (See: recommended heat pattern) VMFP16: 37 x 50 x 1.6 [mm] glass EPOXY

board mount. When the exposed pad is bonded, Rsj will not be performed.

4. Maximum at TA = 25°C. When the exposed pad is bonded, Rsj will not be performed.

5. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

6Freescale Semiconductor

17511A

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions TA = 25°C, VM = VDD = 5.0V, GND = 0V unless otherwise noted. Typical values noted

reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER

Driver Circuit Power Supply Voltage VM2.0 5.0 6.8 V

Logic Supply Voltage VDD 2.7 5.0 5.7 V

Capacitor for Charge Pump C1, C2, C3 0.01 0.1 1.0 μF

Standby Power Supply Current

Motor Supply Standby Current

Logic Supply Standby Current (8)

VMSTBY

VDDSTBY

–

1.0

μA

Operating Power Supply Current

Logic Supply Current (9)

Charge Pump Circuit Supply Current

VDD

ICRES

–

3.0

0.7

Low VDD Detection Voltage (10) VDDDET 1.5 2.0 2.5 V

Driver Output ON Resistance (11) RDS(ON) – 0.46 0.60 Ω

GATE DRIVE

Gate Drive Voltage (12)

No Current Load

VCRES

12 13 13.5

Gate Drive Ability (Internally Supplied)

ICRES = -1.0 mA

VCRESLOAD

10 11.2 –

Gate Drive Output

IOUT = -50 μA

lIN = 50 μA

VGOUTHIGH

VGOUTLOW

VCRES- 0.5

LGND

VCRES- 0.1

LGND

+ 0.1

VCRES

LGND + 0.5

CONTROL LOGIC

Logic Input Voltage VIN 0–V

DD V

Logic Input Function (2.7V < VDD < 5.7V)

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

VIH

VIL

IIH

IIL

VDD x 0.7

–

-1.0

–

VDD x 0.3

1.0

–

μA

Pull-Up Resistance (EN, GIN)RPU 50 100 200 kΩ

Notes

8. I

VDDSTBY includes current to the predriver circuit.

9. IVDD includes current to the predriver circuit.

10. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the

gate voltage VCRES is applied from an external source, VCRES = 7.5V.

11. IO = 1.0A source + sink.

12. Input logic signal not present.

Analog Integrated Circuit Device Data

Freescale Semiconductor 7

17511A

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions TA = 25°C, VM = VDD = 5.0V, GND = 0V unless otherwise noted. Typical values noted

reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

INPUT (EN, IN1, IN2, GIN)

Pulse Input Frequency fIN – – 200 kHz

Input Pulse Rise Time (13) tR– – 1.0 (14) μs

Input Pulse Fall Time (15) tF– – 1.0 (14) μs

OUTPUT

Propagation Delay Time

Turn-ON Time

Turn-OFF Time

tPLH

tPHL

–

0.55

1.0

μs

GOUT Propagation Delay Time

Turn-ON Time

Turn-OFF Time

tSON

tSOFF

–

0.15

0.5

μs

Charge Pump Circuit (16)

Rise Time (17)

tVCRESON

–0.13.0

Low-Voltage Detection Time tVDDDET ––10ms

Notes

13. Time is defined between 10% and 90%.

14. That is, the input waveform slope must be steeper than this.

15. Time is defined between 90% and 10%.

16. When C1 = C2 = C3 = 0.1 μF.

17. Time to charge CRES to 11V after application of VDD.

Analog Integrated Circuit Device Data

8Freescale Semiconductor

17511A

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 5. tPLH, tPHL, and tPZH Timing Figure 6. Low-Voltage Detection

PLH

10%

EN, IN1, IN2

OUT1, OUT2

50%

90%

(GIN)

(GOUT)

SON

) t

PHL

SOFF

)

DET

50%

90%

DETON

DETOFF

DET

(<1.0

0.8 V/

1.5 V

2.5 V/3.5 V

Table 6. Truth Table

INPUT OUTPUT

EN IN1 IN2 GIN OUT1 OUT2 GOUT

HHHX L L X

HH L XH L X

HLHXLH X

HLLXZZ X

LXXXL L L

HXXHXX L

HXXLXX H

H = High.

L = Low.

Z = High impedance.

X = Don’t care.

Analog Integrated Circuit Device Data

Freescale Semiconductor 9

17511A

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 17511A is a monolithic H-Bridge power IC applicable

to small DC motors used in portable electronics. The 17511A

can operate efficiently with supply voltages as low as 2.0V to

as high as 6.8V, and it can provide continuos motor drive

currents of 1.0A while handling peak currents up to 3.0A. It is

easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0V-

compatible logic. The device can be pulse width modulated

(PWM-ed) at up to 200 kHz. The 17511A has four operating

modes: Forward, Reverse, Brake, and Tri-State (High

Impedance).

Basic protection and operational features (direction,

dynamic braking, PWM control of speed and torque, main

power supply undervoltage detection and shutdown, logic

power supply undervoltage detection and shutdown), in

addition to the 1.0A rms output current capability, make the

17511A a very attractive, cost-effective solution for

controlling a broad range of small DC motors. In addition, a

pair of 17511A devices can be used to control bipolar step

motors. The 17511A can also be used to excite transformer

primary windings with a switched square wave to produce

secondary winding AC currents.

As shown in Figure 2, 17511A Simplified Internal Block

Diagram, page 2, the 17511A is a monolithic H-Bridge with

built-in charge pump circuitry. For a DC motor to run, the

input conditions need to be set as follows: ENable input logic

HIGH, one INput logic LOW, and the other INput logic HIGH

(to define output polarity). The 17511A can execute dynamic

braking by setting both IN1 and IN2 logic HIGH, causing both

low-side MOSFETs in the output H-Bridge to turn ON.

Dynamic braking can also implemented by taking the ENable

logic LOW. The output of the H-Bridge can be set to an open-

circuit high-impedance (Z) condition by taking both IN1 and

IN2 logic LOW. (refer to Table 6, Truth Table, page 8).

The 17511A outputs are capable of providing a continuous

DC load current of up to 1.2A. An internal charge pump

supports PWM frequencies to 200 kHz. The EN pin also

controls the charge pump, turning it off when EN = LOW, thus

allowing the 17511A to be placed in a power-conserving

sleep mode.

FUNCTIONAL PIN DESCRIPTION

OUT1 AND OUT2

The OUT1 and OUT2 pins provide the connection to the

internal power MOSFET H-Bridge of the IC. A typical load

connected between these pins would be a small DC motor.

These outputs will connect to either VM or PGND, depending

on the states of the control inputs (refer to Table 6, Truth

Table, page 8).

PGND AND LGND

The power and logic ground pins (PGND and LGND)

should be connected together with a very low-impedance

connection.

CRES

The CRES pin provides the connection for the external

reservoir capacitor (output of the charge pump). Alternatively

this pin can also be used as an input to supply gate-drive

voltage from an external source via a series current-limiting

resistor. The voltage at the CRES pin will be approximately

three times the VDD voltage, as the internal charge pump

utilizes a voltage tripler circuit. The VCRES voltage is used by

the IC to supply gate drive for the internal power MOSFET

H-Bridge.

The VM pins carry the main supply voltage and current into

the power sections of the IC. This supply then becomes

controlled and/or modulated by the IC as it delivers the power

to the load attached between OUT1 and OUT2. All VM pins

must be connected together on the printed circuit board with

as short as possible traces offering as low impedance as

possible between pins.

VM has an undervoltage threshold. If the supply voltage

drops below the undervoltage threshold, the output power

stage switches to a tri-state condition. When the supply

voltage returns to a level that is above the threshold, the

power stage automatically resumes normal operation

according to the established condition of the input pins.

IN1, IN2, AND EN

The IN1, IN2, and EN pins are input control pins used to

control the outputs. These pins are 5.0 V CMOS-compatible

inputs with hysteresis. The IN1, IN2, and EN work together to

control OUT1 and OUT2 (refer to Table 6, Truth Table).

GIN

The GIN input controls the GOUT pin. When GIN is set

logic LOW, GOUT supplies a level-shifted high-side gate

drive signal to an external MOSFET. When GIN is set logic

HIGH, GOUT is set to GND potential.

C1L AND C1H, C2L AND C2H

These two pairs of pins, the C1L and C1H and the C2L and

C2H, connect to the external bucket capacitors required by

the internal charge pump. The typical value for the bucket

capacitors is 0.1 μF.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

17511A

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

GOUT

The GOUT output pin provides a level-shifted, high-side

gate drive signal to an external MOSFET with CISS up to

500pF.

VDD

The VDD pin carries the 5.0V supply voltage and current

into the logic sections of the IC. VDD has an undervoltage

threshold. If the supply voltage drops below the undervoltage

threshold, the output power stage switches to a tri-state

condition. When the supply voltage returns to a level that is

above the threshold, the power stage automatically resumes

normal operation according to the established condition of

the input pins.

Analog Integrated Circuit Device Data

Freescale Semiconductor 11

17511A

TYPICAL APPLICATIONS

FUNCTIONAL PIN DESCRIPTION

TYPICAL APPLICATIONS

Figure 7 shows a typical application for the 17511A. When

applying the gate voltage to the CRES pin from an external

source, be sure to connect it via a resistor equal to, or greater

than, RG = VCRES / 0.02Ω.

Figure 7. 17511A Typical Application Diagram

CEMF SNUBBING TECHNIQUES

Care must be taken to protect the IC from potentially

damaging CEMF spikes induced when commutating currents

in inductive loads. Typical practice is to provide snubbing of

voltage transients via placing a capacitor or zener at the

supply pin (VM) (see Figure 8).

Figure 8. CEMF Snubbing Techniques

MCU

17511A

5.0 V

GND

C1L

C1H

C2L

C2H

CRES

GIN

IN1

IN2

VDD

OUT1

OUT2

Motor

GOUT

Solenoid

RG > VCRES/0.02 Ω

VCRES < 14 V

0.01 μF

NC = No Connect

17511A

5.0 V 5.0 V

C1L

C1H

C2L

C2H

RES

OUT1

OUT2

17511A

5.0 V 5.0 V

C1L

C1H

C2L

C2H

RES

OUT1

OUT2

GND GND

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

17511A

PACKAGING

SOLDERING

PACKAGING

SOLDERING

THERMAL PERFORMANCE

Below are the recommended heat patterns for the QFN24 Exposed Pad thermal package.

Figure 9. Recomended Heat Patterns for QFN24 EP

Obverse Reverse

Analog Integrated Circuit Device Data

Freescale Semiconductor 13

17511A

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EV (PB-FREE) SUFFIX

16-PIN VMFP

PLASTIC PACKAGE

98ASA10614D

ISSUE B

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

17511A

PACKAGING

PACKAGE DIMENSIONS

PACKAGE DIMENSIONS (CONTINUED)

EP (PB-FREE) SUFFIX

24-PIN QFN

NON-LEADED PACKAGE

98ARL10577D

ISSUE B

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

17511A

PACKAGING

PACKAGE DIMENSIONS

PACKAGE DIMENSIONS (CONTINUED)

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

17511A

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

2.0 4/2007 • Implemented Revision History page

• Converted to Freescale format

• Added Peak Package Reflow Temperature During Reflow (solder reflow) parameter and Note with

instructions from www.freescale.com to Maximum Ratings Table 3

3.0 11/2007 • Replaced 16 pin package drawing with 98ASA10614D, REV. B and replaced 24 pin package

drawing with 98ARL10577D, REV. B.

4.0 2/2008 • Revised Siplified Application Diagram on page 1; Corrected typo - VM voltage from 15V to 5V.

5.0 8/2008 • Further Defined Thermal Resistance and Power Disapation in Table 2, Page 5 for both packages.

MPC17511A

Rev. 5.0

9/2008

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