REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Add Radiation Hardness Assurance limits. Editorial changes throughout. – jak 98-04-20 Monica L. Poelking
B
Add radiation features for device type 01. Add vendor CAGE F8859. Add
case outline X. Add device type 02. Add table III, delta limits. Update drawing
to MIL-PRF-38535 requirements. Editorial changes throughout. – jak
03-03-07
Thomas M. Hess
C
Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. -
LTG
10-03-25
Thomas M. Hess
REV
SHEET
REV C C C C C C C
SHEET 15 16 17 18 19 20 21
REV STATUS REV C C C C C C C C C C C C C C
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Joseph A. Kerby
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 4321 8-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Thomas J. Ricciuti
APPROVED BY
Monica L. Poelking
MICROCIRCUIT, DIGIT AL, ADVANCED CMOS,
4-BIT PRESETTABLE BINARY COUNTER,
SYNCHRONOUS RESET, TTL COMPATIBLE
INPUTS, MONOLITHIC SILICON
DRAWING APPROVAL DATE
92-12-23
AMSC N/A
REVISION LEVEL
C SIZE
A CAGE CODE
67268
5962-91723
SHEET 1 OF 21
DSCC FORM 2233
APR 97 5962-E210-10
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents t wo product assur ance class levels consisting of high reliabilit y (device classes Q and
M) and space application (de vice class V). A choice of case outlines and lead finishes are available and are reflected i n the Part
or Identifying Number (PIN). When availa ble, a choice of Radiation Hardness Assurance (RHA) levels is reflected i n the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 R 91723 01 V E A
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked dev ices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF -38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a n on-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 1/ 54ACT163 4-bit presettable binary counter, synchronous reset,
TTL compatible inputs
02 54ACT163 4-bit presettable binary counter, synchronous reset,
TTL compatible inputs
111111111.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class Device requirements docum entation
M Vendor self-certification to the requireme nts for MIL-STD-883 compliant, non-
JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as desi gnated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
E GDIP1-T16 or CDIP2-T16 16 Dual-in-line
F GDFP2-F16 or CDFP3-F16 16 Flat pack
X CDFP3-F16 16 Flat pack
2 CQCC1-N20 20 Square leadles s chip carrier
1.2.5 Lead finish. The lead finish is as speci fied in MIL-PRF-38535 for device class es Q and V or MIL-PRF-38535,
appendix A for device class M.
1/ Due to internal noise problems, device type 01 does not meet the minimum VIH threshold limit that is characteristic of this
technology family.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 3
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/ 2/
Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc
Input voltage range ............................................................................................. -0.5 V dc to VCC + 0.5 V dc
Output voltage range .......................................................................................... -0.5 V dc to VCC + 0.5 V dc
DC input diode current (IIK) (-0.5 V VIN VCC + 0.5 V) ....................................... 20 mA
DC output diode current (IOK) (-0.5 V VOUT VCC + 0.5 V) ................................. 20 mA
DC output current (IOUT) (per output pin) .............................................................. 50 mA
DC VCC or GND current (ICC, IGND) (per pin) ......................................................... 250 mA 3/
Maximum power dissipation (PD) ......................................................................... 500 mW
Storage temperature range (TSTG) ....................................................................... -65C to +150C
Lead temperature (soldering, 10 seconds) .......................................................... +300C
Thermal resistance, junction-to-case (JC) .......................................................... See MIL-STD-1835
Junction temperature (TJ) .................................................................................... +175C 4/
1.4 Recommended operating conditions. 2/ 5/
Supply voltage range (VCC) .................................................................................. +4.5 V dc to +5.5 V dc
Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT) ................................................................................. +0.0 V dc to VCC
Maximum low level input voltage (VIL).................................................................. 0.8 V dc
Minimum high level input voltage (VIH):
Device type 01 ................................................................................................... 3.0 V dc 6/
Device type 02 ................................................................................................... 2.0 V dc
Case operating temperature rang e (TC) ............................................................... -55C to +125C
Input edge rate (v/t) maximum
(from VIN = 0.8 V to 2.0 V, 2.0 V to 0.8 V) ......................................................... 125 mV/ns
Maximum high level output current (IOH) .............................................................-24 mA
Maximum low level output current (IOL) ...............................................................+24 mA
1.5 Radiation features.
Device t ype 01:
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) ......... 100 Krads (Si)
No Single Event Latch-up (SEL) at effective LET .................................. 100 MeV/(mg/cm2)
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages ar e referenced to GND.
3/ For packages with multiple VCC and GND pins, this value represents the maximum total current flowing into or out of all VCC
and GND pins.
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ Unless otherwise specified, th e values listed above shall appl y over the full VCC and TC recommended operating ra nge.
6/ For dynamic operation, a VIH level between 2.0 V and 3.0 V may be recognized by this device as a hi gh logic level input.
For static operation, a VIH 2.0 V will be recognized by this device as a high logic lev el input. Users are cautioned to verify
that this will not affect their system.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 4
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and han dbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-385 35 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents ar e available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue , Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document (s) form a part of this document to the extent specifie d herein.
Unless otherwise specified, th e issues of these documents cited in the solicitation or contract.
ELECTRONIC INDUSTRIES ALLIANCE (EIA)
JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanc ed High-Speed
CMOS Devices.
(Copies of these documents are available onl ine at http://www.jedec.org or from Electronic Industries Alliance,
2500 Wilson Boulevard, Arli ngton, VA 22201-3834).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations un less a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requ irements for device classes Q and V shall be in accorda nce with
MIL-PRF-38535 and as specif ied herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specif ied
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appen dix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 State diagram. The state diagram shall be as specified on figure 4.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 5
DSCC FORM 2234
APR 97
3.2.6 Ground bounce waveforms and test circuit. The ground bounce waveforms and test circuit shall be as specified on
figure 5.
3.2.7 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 6.
3.2.8 Radiation exposure circ uit. The radiation exposure circuit shall be maintained by the manufactur er under document
revision level control and shall be made avail able to the preparing and acquirin g activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature rang e.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. T he electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the devic e. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF - 38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for devic e classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of complianc e shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of complia nce submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-3853 5 and
herein or for device class M, the requirement s of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38 535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSC C-VA of change of product
(see 6.2 herein) involving devices acquired to this dra wing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acqu iring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the optio n of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 40 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type
and 4/
device
class
VCC Group A
subgroups Limits 5/ Unit
Min Max
Positive input
clamp voltage
3022
VIC+
6/ 7/ For input under test, IIN = 1.0 mA All
Q, V 0.0 V 1 0.4 1.5 V
M, D, P, L, R 01
V 0.0 V 1 0.4 1.5
Negative input
clamp voltage
3022
VIC-
6/ 7/ For input under test, IIN = -1.0 mA All
Q, V Open 1 -0.4 -1.5 V
M, D, P, L, R 01
V Open 1 -0.4 -1.5
High level output
voltage
3006
VOH
6/ 7/ 8/ F or all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
For all other inputs,
All
All 4.5 V 1, 2, 3 4.4 V
All
All 5.5 V 5.4
VIN = VCC or GND IOH
= -50 A M, D, P, L, R 01
All 5.5 V 1 5.4
For all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
All
All 4.5 V 1, 2, 3 3.7
For all other inputs,
VIN = VCC or GND M, D, P, L, R 01
All 4.5 V 1 3.7
IOH = -24 mA All
All 5.5 V 1, 2, 3 4.7
For all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
All
All 5.5 V 1, 2, 3 3.85
For all other inputs,
VIN = VCC or GND 9/
IOH = -50 mA
M, D, P, L, R 01
All 5.5 V 1 3.85
Low level output
voltage
3007
VOL
6/ 7/ 8/ F or all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
For all other inputs,
All
All 4.5 V 1, 2, 3 0.1 V
All
All 5.5 V 0.1
VIN = VCC or GND
IOL = 50 A M, D, P, L, R 01
All 5.5 V 1 0.1
For all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
All
M 4.5 V 1 0.4
2, 3 0.5
For all other inputs,
VIN = VCC or GND M, D, P, L, R 01
All 4.5 V 1 0.4
IOL = 24 mA All
M 5.5 V 1 0.4
2, 3 0.5
All
Q, V 4.5 V 1, 3 0.4
2 0.5
All
Q, V 5.5 V 1, 3 0.4
2 0.5
For all inputs affecting output under
test, VIH = 3.0 V, VIL = 0.8 V device 01
VIH = 2.0 V, VIL = 0.8 V device 02
All
All 5.5 V 1, 2, 3 1.65
For all other inputs,
VIN = VCC or GND 9/
IOL = 50 mA
M, D, P, L, R 01
All 5.5 V 1 1.65
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type
and 4/
device
class
VCC Group A
subgroups Limits 5/ Unit
Min Max
Input capacitance
3012 CIN See 4.4.1c
TC = +25C All
All GND 4 10.0 pF
Power dissipation
capacitance CPD
10/ See 4.4.1c
TC = +25C, f = 1 MHz All
All 5.0 V 4 50
Quiescent supply
current delta,
TTL input levels
3005
ICC
6/ 7/
11/
For input under test,
VIN = VCC - 2.1 V
For all other inputs,
VIN = VCC or GND
All
Q, V 5.5 V 3 1.6
mA
1, 2 1.0
All
M 5.5 V 1, 2, 3 1.6
M, D 01
All 5.5 V 1 1.6
P, L, R 3.5
Quiescent supply
current, outputs
high
3005
ICCH
6/ 7/ For all inputs,
VIN = VCC or GND All
Q, V 5.5 V 1 2.0
A
2 40.0
All
M 5.5 V 1 8.0
2, 3 160.0
M 01
All 5.5 V 1 +100.0
D 1.0 mA
P, L, R 3.5
Quiescent supply
current, outputs
low
3005
ICCL
6/ 7/ For all inputs,
VIN = VCC or GND All
Q, V 5.5 V 1 2.0
A
2 40.0
All
M 5.5 V 1 8.0
2, 3 160.0
M 01
All 5.5 V 1 100.0
D 1.0 mA
P, L, R 3.5
Input leakage
current high
3010
IIH
6/ 7/ For input under test,
VIN = VCC
For all other inputs,
VIN = VCC or GND
All
Q, V 5.5 V 1 0.1
A
2 1.0
All
M 5.5 V 1 0.1
2, 3 1.0
M, D, P, L, R 01
All 5.5 V 1 0.1
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
ML-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type
and 4/
device
class
VCC Group A
subgroups Limits 5/ Unit
Min Max
Input leakage
current low
3009
IIL
6/ 7/ For input under test,
VIN = GND
For all other inputs,
VIN = VCC or GND
All
Q, V 5.5 V 1 -0.1
A
2 -1.0
All
M 5.5 V 1 -0.1
2, 3 -1.0
M, D, P, L, R 01
All 5.5 V 1 -0.1
Low level ground
bounce noise VGBL
12/ VLD = 2.5 V, IOL = +24 mA
See figure 5 All
Q, V 4.5 V 4 1500 mV
High level ground
bounce noise VGBH
12/ VLD = 2.5 V, IOH = -24 mA
See figure 5 All
Q, V 4.5 V 4 1500 mV
Latch-up
input/output
over-voltage
ICC
(O/V1)
13/
tw 100 s, tcool tw
5 s tr 5 ms, 5 s tf 5 ms
Vtest = 6.0 V, VCCQ = 5.5 V
Vover = 10.5 V
All
Q, V 5.5 V 2 200 mA
Latch-up
input/output
positive over-
current
ICC
(O/I1+)
13/
tw 100 s, tcool tw
5 s tr 5 ms, 5 s tf 5 ms
Vtest = 6.0 V, VCCQ = 5.5 V
Itrigger = +120 mA
All
Q, V 5.5 V 2 200 mA
Latch-up
input/output
negative over-
current
ICC
(O/I1-)
13/
tw 100 s, tcool tw
5 s tr 5 ms, 5 s tf 5 ms
Vtest = 6.0 V, VCCQ = 5.5 V
Itrigger = -120 mA
All
Q, V 5.5 V 2 200 mA
Latch-up supply
over-voltage ICC
(O/V2)
13/
tw 100 s, tcool tw
5 s tr 5 ms, 5 s tf 5 ms
Vtest = 6.0 V, VCCQ = 5.5 V
Vover = 9.0 V
All
Q, V 5.5 V 2 100 mA
Functional tests
3014 5/ 6/
14/ Device type 01,
VIL = 0.4 V, VIH = 3.0 V
Device type 02,
VIL = 0.8 V, VIH = 2.0 V
All
All 4.5 V 7, 8 L H
Verify output VOUT
See 4.4.1d M, D, P, L, R 01
All 7 L H
All
M 5.5 V 7, 8 L H
Propagation delay
time, CP to Qn
(count mode)
3003
tPHL1,
tPLH1
6/ 7/
15/
CL = 50 pF minimum
RL = 500 All
M 4.5 V 9 1.0 9.5 ns
See figure 6 M, D, P, L, R 01
All 9 1.0 9.5
All
M 10, 11 1.0 10.5
01
Q, V 9, 11 1.0 9.5
10 1.0 10.5
02
Q, V 9 1.0 10.0
10, 11 1.0 11.0
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 9
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
ML-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type
and 4/
device
class
VCC Group A
subgroups Limits 5/ Unit
Min Max
Propagation delay
time, CP to Qn
(load mode)
3003
tPHL2,
tPLH2
6/ 7/
15/
CL = 50 pF
RL = 500 All
M 4.5 V 9 1.0 9.0 ns
See figure 6 M, D, P, L, R 01
All 9 1.0 9.0
All
M 10, 11 1.0 10.0
01
Q, V 9, 11 1.0 9.0
10 1.0 10.0
02
Q, V 9 1.0 10.0
10, 11 1.0 11.0
Propagation delay
time, CP to TC
(CET = H)
3003
tPHL3,
tPLH3
6/ 7/
15/
CL = 50 pF minimum
RL = 500 All
M 4.5 V 9 1.0 12.0 ns
See figure 6 M, D, P, L, R 01
All 9 1.0 12.0
All
M 10, 11 1.0 13.0
All
Q, V 9, 11 1.0 12.0
10 1.0 13.0
Propagation delay
time, CET to TC
3003
tPHL4,
tPLH4
6/ 7/
15/
CL = 50 pF minimum
RL = 500 All
M 4.5 V 9 1.0 9.0 ns
See figure 6 M, D, P, L, R 01
All 9 1.0 9.0
All
M 10, 11 1.0 9.5
01
Q, V 9, 11 1.0 9.0
10 1.0 9.5
02
Q, V 9 1.0 9.0
10, 11 1.0 10.5
Maximum clock
frequency
3003
fMAX
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 95.0
MHz
10, 11 85.0
All
Q, V 9, 11 95.0
10 85.0
Input setup time,
high or low,
PE to CP
ts1
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 8.5
ns
10, 11 11.5
All
Q, V 9, 11 8.5
10 11.5
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
ML-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type
and 4/
device
class
VCC Group A
subgroups Limits 5/ Unit
Min Max
Input setup time,
high or low,
Pn to CP
ts2
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 10.0
ns
10, 11 13.5
All
Q, V 9, 11 10.0
10 13.5
Input setup time,
high or low,
SR to CP
ts3
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 10.0
ns
10, 11 13.5
All
Q, V 9, 11 10.0
10 13.5
Input setup time,
high or low,
CEP, CET to CP
ts4
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 5.5
ns
10, 11 7.0
All
Q, V 9, 11 5.5
10 7.0
Input hold time,
high or low,
PE to CP
th1
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
All 4.5 V 9, 10, 11 0.0 ns
Input hold time,
high or low,
Pn to CP
th2
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
All 4.5 V 9, 10, 11 0.5 ns
Input hold time,
high or low,
S
R
to CP
th3
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
All 4.5 V 9, 10, 11 0.0 ns
Input hold time,
high or low,
CEP, CET to CP
th4
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
M 4.5 V 9 0.0
ns
10, 11 0.5
All
Q, V 9, 10 0.0
11 0.5
Clock pulse width,
high and low,
(count, load
modes)
tw
16/ CL = 50 pF minimum
RL = 500
See figure 6
All
All 4.5 V 9, 10, 11 5.0 ns
1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test proc edure under the conditions
listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein.
2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits. Output terminals
not designated shall be high l evel logic, low level logic, or open, except as follows:
a. VIC (pos) tests, the GND terminal can be open. TC = +25C.
b. VIC (neg) tests, the VCC terminal shall be ope n. TC = +25C.
c. All ICC and ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be
placed in the circuit such that all current flows through the meter.
3/ RHA devices supplied to this drawing have been ch aracterized through all levels M, D, P, L and R of irradiation.
However, these devices are only tested at the "R" level. Pre and post irradiation values are identica l unless otherwise
specified in table I. When performing post irradiation electri cal measurements for any RHA level, T A = +25C.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
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TABLE I. Electrical performance characteristi c s - Continued.
4/ The word "All" in the device type and device class column, means l imits for all device types and classes.
5/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND
and the direction of current flo w, respectively; and the absolute va lue of the magnitude, not the sign, is relative to the
minimum and maximum limits, as applicable, listed herein. All devices shall meet or exc eed the limits specified in table I,
as applicable, at 4.5 V VCC 5.5 V.
6/ RHA samples do not have to be tested at -55C and +125C prior to irradiation.
7/ When performing postirradiation electrical m easurements for RHA level, TA = +25C. Limits shown are guaranteed at
T
A = +25C 5C.
8/ For dynamic operation, a VIH level bet ween 2.0 V and 3.0 V may be recognized by this devic e as a high logic level input.
For static operation, a VIH 2.0 V will be recognized by this device as a high logic lev el input. Users are cautioned to
verify that this will not affect their system.
9/ Transmission driving tests are performed at VCC = 5.5 V with a 2 ms duration maximum. This test may be performed
using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 3.0 V or 0.8 V for device 01
and VIN = 2.0 V or 0.8 V for device 02.
10/ Power dissipation capacitance (CPD) determines the no load power consumption,
P
D = (CPD + CL) (VCC x VCC) f + (ICC x VCC) + (n x d x ICC x VCC). The dynamic current consumption,
I
S = (CPD + CL) VCCf + ICC + (n x d x ICC).
For both PD and IS, n is the number of device inputs at TTL levels; f is the frequency of the input signal; and d is the duty
cycle of the input signal.
11/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneousl y at
VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using
the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 1.6 mA; and
the preferred method and limits are guaranteed.
12/ This test is for qualification o nly. Ground bounce tests are performed on a nonswitching (quiescent) output and are used
to measure the magnitude of induc ed noise caused by other simultaneousl y switching outputs. The test is performed on
a low noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = i.e, 24 mA) and 50 pF of
load capacitance (see figure 5). The loads must be located as close as possibl e to the device output. Inputs are then
conditioned with 1 MHz pulse (tr = tf = 3.5 1.5ns) switching simultaneously and in phase such that one o utput is forced
low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a
F.E.T. oscilloscope probe with at least 1 M impedance. Measurement is taken from the peak of the largest positive
pulse with respect to the nominal lo w level output voltage (see figure 5). The device inputs are then co nditioned such
that the output under test is at a high nominal VOH level. The high lev el ground bounce measurement is then measured
from nominal VOH level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high
and low level with a maximum numb er of outp uts switching.
13/ See EIA/JEDEC STD. No. 78 for electrica lly induced latch-up test methods and procedures. The values listed for Itrigger
and Vover, are to be accurate within 5 percent.
14/ Tests shall be performed in sequence, attributes data o nl y. Functional tests shall include the truth table and other logic
patterns used for fault detection. Functional tests shall be performed in sequence as ap proved by the qualifying activity
on qualified devices. H 2.5 V, L < 2.5 V, high inputs = 3.0 V, low inputs = 0.4 V for device type 01 and high
inputs = 2.0 V, low inputs = 0.8 V for device type 02. The input voltag e levels have the allowable tolerances in
accordance with MIL-STD-883 already incorporated. The VIH level used for functional te sting shall be 3.0 V 0 percent
for device type 01.
15/ AC limits at VCC = 5.5 V are equal to limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum AC limits
for VCC = 5.5 V are 1.0 ns and guaranteed b y guardbanding the VCC = 4.5 V minimum lim its to 1.5 ns. For propagation
delay tests, all paths must be tested.
16/ This parameter shall be guaranteed, if not tested, to the limits in table I, herein.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
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DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 12
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APR 97
Device type All
Case outlines E, F, X 2
Terminal number Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S
R
CP
P0
P1
P2
P3
CEP
GND
PE
CET
Q3
Q2
Q1
Q0
TC
VCC
- - -
- - -
- - -
- - -
NC
SR
CP
P0
P1
NC
P2
P3
CEP
GND
NC
PE
CET
Q3
Q2
NC
Q1
Q0
TC
VCC
NC = No internal connection
PIN Description
Terminal Symbol Description
CEP
CET
CP
SR
Pn (n = 0 to 3)
PE
Qn (n = 0 to 3)
TC
Count enable parallel control input
Count enable trickle co ntrol input
Clock pulse timing input (active rising edge)
Synchronous master reset control input (active low)
Parallel data inputs
Parallel enable control input (active low)
Flip-flop outputs
Terminal count output
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
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DSCC FORM 2234
APR 97
S
R
PE CET CEP Function
L X X X Reset (Qn = L, TC = L) (See note 1)
H L X X Load (Qn = Pn) (See notes 1 and 2)
H H H H Count (See notes 1, 2, and 3)
H H L X No change (See notes 1, 2, and 4)
H H X L No change (See notes 1, 2, and 4)
H = High voltage level
L = Low voltage level
X = Irrelevant
NOTES:
1. Action occurs on the risi ng edge of the clock (CP) input when the appropriate setup, hold, and pulse width timing
requirements have been met in table I herein.
2. TC = H, whenever the cond itions satisfy the logic equation, TC = Q0 Q1 Q2 Q3 CET are valid. For any
other conditions, TC = L. The TC output will react to the CET input independe nt of the clock input. The T C output is
subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or
asynchronous reset for flip-flo ps, registers, or counters.
3. For the countin g sequence, see the state diagram on figure 4.
4. Outputs maintain their current output state. For TC, the conditions in note 3 app ly.
FIGURE 2. Truth table.
STANDARD
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FIGURE 3. Logic diagram.
FIGURE 4. State diagram.
STANDARD
MICROCIRCUIT DRAWING
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A
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NOTE: Resistor and capacitor tolerances = 10%.
FIGURE 5. Ground bo unce waveforms and test circuit.
STANDARD
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COLUMBUS, OHIO 43218-3990 REVISION LEVEL
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FIGURE 6. Switching waveforms and test circuit .
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MICROCIRCUIT DRAWING
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NOTES:
1. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
2. RT = 50 or equivalent, RL = 500 or equivalent.
3. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 3.0 ns; tf 3.0 ns; duty cycle = 50 percent.
4. Timing parameters shall be tested at a minim um inp ut frequency of 1 MHz.
5. The outputs are measured o ne at a time with one transition per measurement.
FIGURE 6. Switching waveforms and test circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
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APR 97
4. VERIFICATION
4.1 Sampling and i nspection. For device classes Q and V, sampling and inspection proc edures shall be in accordanc e wit h
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures sh all be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. F or device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualific ation and technology conformance inspection. For device class M, screenin g shall be in
accordance with method 5004 of MIL-STD-883, and shal l be conducted on all devices prior to qua lity conformance inspectio n.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document re vision
level control and shall be ma de available to the preparing or acquiring activity upon requ est. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b. Interim and final electrical test parameters shall be as specified in tabl e II herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives sh all be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. T he burn-in test circuit shall be maintained under
document revision level contro l of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in tabl e II herein.
c. Additional screening for device class V beyond the req uirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualificatio n inspection for device classes Q and V shal l be in
accordance with MIL-PRF-38535. Inspectio ns to be performed shall be those specified in MIL-PRF-38 535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Qualit y conformance inspection for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for grou ps A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Latch-up and ground bounce tests are required for device classes Q and V. These tests shall be p erformed only for
initial qualification and after process or design changes which may affect the performance of the device. Latch-up
tests shall be considered destr uctive. For latch-up and ground-bounce tests, test all applicable pins on five devices
with zero failures.
c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be
tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. F or CIN and CPD, test all
applicable pins on five devices with zero failures.
d. For device class M, subgroups 7 and 8 tests shall be sufficient to verif y the truth table in figure 2 herein. The test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible
input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein.
For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 19
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M Device
class Q Device
class V
Interim electrical
parameters (see 4.2) - - - - - - 1
Final electrical
parameters (see 4.2) 1/ 1, 2, 3, 7,
8, 9, 10, 11 1/ 1, 2, 3, 7,
8, 9, 10, 11 2/ 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4) 1, 2, 3, 4, 7,
8, 9, 10, 11 1, 2, 3, 4, 7,
8, 9, 10, 11 1, 2, 3, 4, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4) 1, 2, 3 1, 2, 3 3/ 1, 2, 3, 7,8,
9, 10, 11
Group D end-point electrical
parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3
Group E end-point electrical
parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7, and deltas.
3/ Delta limits as specified in table III shall be required where specified, and the delta limit s shall be completed
with reference to the zero hour electrical parameters.
TABLE III. Burn-in and operating life test, delta parameters (+25C).
Parameter 1/ Symbol Device types Delta Limits
Supply current ICCH, ICCL 01 100 nA 2/
02 300 nA
Supply current delta ICC 02 0.4 mA
Input current low level IIL 02
20 nA
Input current high level IIH 02
20 nA
Output voltage low level
VCC = 5.5 V, IOL = +24 mA VOL 02
0.04 V
Output voltage high level
VCC = 5.5 V, IOH = -24 mA VOH 02
0.20 V
1/ These parameters shall be recorded before and after the require d burn-in and
life tests to determine delta limits.
2/ The limit may not be production tested.
4.4.2 Group C inspection. The group C insp ection end-point electrical parameters shall be as specified in table II herei n.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-91723
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 20
DSCC FORM 2234
APR 97
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the inte nt specified in method 1005 of
MIL-STD-883.
b. TA = +125C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state lif e te st duration, test condition and test temperature,
or approved alternativ es shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under docum ent revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the inte nt specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required onl y for parts intended to be marked as radiation h ardness assured
(see 3.5 herein).
a. End-point electrical parameter s shall be as specified in table II herein.
b. For device classes Q and V, the devices or test vehicl e shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF - 38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,
after exposure, to the subgrou ps specified in table II herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883,
method 1019, condition A, and as specified herein:
Prior to and during total dose irradiation ch aracterization and testing, the devices for characterization shall be biased so that
50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing shall be bi ased to the worst case
condition established during characterization. Devices shall be biased as follows:
1. Inputs tested high, VCC = 5.5 V dc +5%, RCC = 10 20%, VIN = 5.0 V dc +5%, RIN = 1 k 20%, and all outputs are
open.
2. Inputs tested low, VCC = 5.5 V dc +5%, RCC = 10 20%, VIN = 0.0 V dc, RIN = 1 k 20%, and all outputs are open.
4.4.4.1.1 Accelerated annealing testing . Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal e nd-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limits at 25C 5C. Testing shall be performed at initial q ualification and
after any design or process changes which may affect the RHA response of the device.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages giv en are referenced to the microcircuit GND terminal.
Currents given are convention al current and positive when flowing into the referenced terminal.
STANDARD
MICROCIRCUIT DRAWING
SIZE
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5. PACKAGING
5.1 Packaging requirements. The requir eme nts for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming t o this drawing are intended for use for Government microcircuit applicati on s
(original equipment), desig n applications, and lo gistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed chan ges to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control an d which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of chan ges to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-133 1.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of suppl y for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 h ave su bmitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 h ave agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latch-up (SEP).
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-03-25
Approved sources of suppl y for SMD 5962-91723 are listed below for immedi ate acquisition information onl y and
shall be added to MIL-HDBK-103 an d QML-38535 during the next revision. MIL-HDBK-103 and QML-3 8535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this dra wing and a
certificate of compliance has been subm itted to and accepted by DSCC-VA. This information b ulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9172301MEA 0C7V7 54ACT163DMQB
5962-9172301MFA 0C7V7 54ACT163FMQB
5962-9172301M2A 0C7V7 54ACT163LMQB
5962R9172301MEA 3/ 54ACT163DMQB-RH
5962R9172301MFA 3/ 54ACT163FMQB-RH
5962R9172301M2A 3/ 54ACT163LMQB-RH
5962R9172301VEA 3/ 54ACT163JRQMLV
5962R9172301VFA 3/ 54ACT163WRQMLV
5962R9172301V2A 3/ 54ACT163ERQMLV
5962-9172302QXA 3/ 54ACT163K02Q
5962-9172302QXC 3/ 54ACT163K01Q
5962-9172302VXA 3/ 54ACT163K02V
5962-9172302VXC 3/ 54ACT163K01V
1/ The lead finish sho wn for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number m ay not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for conv enience only and the
Government assumes no liability whatsoeve r for any inaccuracies in the
information bulletin.
