MC13234CHT - Freescale Semiconductor

Freescale Semiconductor

Technical Data Sheet Document Number: MC13237

Rev. 1.3, 9/12/2013

1 Introduction

The MC13234/MC13237 is Freescale’s low cost

System-on-Chip (SoC) solution for the IEEE® 802.15.4

Standard that incorporates a complete, low power, 2.4

GHz radio frequency transceiver with TX/RX switch, an

8-bit HCS08 CPU, and a functional set of MCU

peripherals into a 48-pin LGA package. This product

targets wireless RF remote control and other

cost-sensitive applications ranging from home TV and

entertainment systems to medical and supports all

ZigBee node types. The MC13234/MC13237 is a highly

integrated solution, with very low power consumption.

The MC13234/MC13237 contains an RF transceiver that

is an 802.15.4 Standard 2006 compliant radio that

operates in the 2.4 GHz ISM frequency band. The

transceiver includes a low noise amplifier, 1 mW

nominal output power amplifier (PA), internal voltage

controlled oscillator (VCO), integrated transmit/receive

switch, on-board power supply regulation, 12-bit ADC

and full spread-spectrum encoding and decoding.

The on-chip CPU is based on the Freescale HCS08

family of microcontroller units (MCU). The onboard

MC13234/MC13237

Low Cost SoC Remote Control Platform for the 2.4 GHz IEEE®

802.15.4 Standard

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Integrated IEEE 802.15.4 Transceiver (radio

and modem) . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 HCS08 8-bit central processing unit (CPU) 11

5 System clocks . . . . . . . . . . . . . . . . . . . . . . . 12

6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 System and power management . . . . . . . . 12

8 MCU peripherals . . . . . . . . . . . . . . . . . . . . . . 14

9 Development Environment . . . . . . . . . . . . . 19

10Pin Assignment and Connections . . . . . . . 20

11Electrical Specifications . . . . . . . . . . . . . . . 26

12Applications Information . . . . . . . . . . . . . . . 42

13Mechanical Diagrams (Case 212 4-02,

Non-JEDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 46

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

2Freescale Semiconductor

MCU peripheral set has been defined to support the targeted applications. A dedicated DMA block

transfers packet data between RAM and the transceiver to off-load the CPU and allow higher efficiency

and increased performance.

1.1 Ordering information

Table 1 provides ordering information to include RAM, flash, and feature detail differences associated

with the MC1323x family of devices

2Features

This section provides a simplified block diagram and highlights the MC13234/MC13237 features.

2.1 Block diagram

Figure 1 shows a simplified block diagram of the MC13234/MC13237.

Table 1. Orderable parts details

Device Operating

Temp Range

(TA.) Package Memory Options

MC13234CHT –40° to 85° C LGA-48 8 KB RAM, 128 KB flash

MC13234CHTR2 –40° to 85° C LGA-48

Tape and Reel 8 KB RAM, 128 KB flash

MC13237CHT –40° to 85° C LGA-48 8 KB RAM, 128 KB flash

MC13237CHTR2 –40° to 85° C LGA-48

Tape and Reel 8 KB RAM, 128 KB flash

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 3

Figure 1. MC13234/MC13237 simplified block diagram

2.2 Features summary

• Fully compliant IEEE 802.15.4 Standard 2006 transceiver supports 250 kbps O-QPSK data in

5.0 MHz channels and full spread-spectrum encode and decode

— 2.4 GHz

— Operates on one of 16 selectable channels per IEEE 802.15.4

— Programmable output power with 0 dBm nominal output power , programmable from –30 dBm

to +2 dBm typical

— Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE

802.15.4 Standard requirement of –85 dBm

— Partial power down (PPD_RX) Listen mode available to reduce current while in receive mode

and waiting for an incoming frame

• Small RF footprint

— Integrated transmit/receive switch

— Differential input/output port (typically used with a balun)

— Low external component count

• Hardware acceleration for IEEE® 802.15.4 applications

— DMA interface

Balun Switch

Analog

Modem

Digital

Modem

IEEE®802.15.4 Transceiver

RF Oscillator/PLL

Clock Generation

32 MHz 32.768 KHz

(Optional)

Clock &

Reset

Module

(CRM)

HCS08

Core

Bus

Interface &

Memory

Arbitrator

Interrupt

Controller

CPU Complex

5 KB / 8 KB

RAM

(4 Timers,

Each w/1Ch)

Timer

Module

Up to 32 GPIO

Data & Address Buses

Debug

Module

82 KB / 128 KB

FLASH

Keyboard

Interface

SCI/UART

Interface

CMT

(IR)

Module

SPI

Interface

Low

Battery

TX/RX

12x12

MC1323x

Analog Pwr

Management

& Voltage Reg

Advanced

Security

Module

802.15.4

PHY

Sequence

Manager

12-Bit ADC

Module

12 x 12

128 KB

8 KB

NOTE: MC13237 Rev 1.1 does not support SPI module. It is planned to be fixed in a future revision.

The 12-Bit ADC module is available only in MC13237 and not available in MC13234.

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

4Freescale Semiconductor

— AES-128 security module

— 16-bit random number generator

— 802.15.4 auto-sequence support

— 802.15.4 receiver frame filtering

• 32 MHz crystal reference oscillator; onboard load trim capability supplements external load

capacitors

• Onboard 1 kHz oscillator for wake-up timing or an optional 32.768 kHz crystal for accurate low

power timing

• Transceiver event timer module has 4 timer comparators available to help manage the

auto-sequencer and to supplement MCU TPM resources

• HCS08 8-bit, 32 MHz CPU

• Flash memory

— 131072dec bytes organized as 128 segments by 1024 bytes

— Programmable over the full power supply range of 1.8 V–3.6 V

— Automated program and erase algorithms

— Flexible protection scheme to prevent accidental program or erase

— Security feature to prevent unauthorized access to the flash

•RAM

— 8 KBytes of SRAM

• Powerful in-circuit debug and flash programming available via on-chip module (BDM)

— Two comparator and 9 trigger modes

— Eight deep FIFO for storing change-of-flow addresses and event-only data

— Tag and force breakpoints

— In-circuit debugging with single breakpoint

• Multiple low power modes (less than 1 A in Stop3)

• Keyboard interrupt (KBI) modules

— MC13234

– Two keyboard control modules capable of supporting up to a 12 x 12 keyboard matrix

– 12 dedicated KBI pins support a 6 x 6 matrix without impacting other IO resources

– 12 KBI interrupts with selectable polarity

— MC13237

– One keyboard control module capable of supporting up to a 8 x 8 keyboard matrix

– 8 dedicated KBI pins support a 4 x 4 matrix without impacting other IO resources

– 8 KBI interrupts with selectable polarity

• Serial communication interface (SCI)

— Full duplex non-return to zero (NRZ)

— Baud rates as high as 1 Mbps can be supported

— LIN master extended break generation

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 5

— LIN slave extended break detection

— Wake-up on active edge

• Serial peripheral interface (SPI)

— Full-duplex or single-wire bidirectional

— Double-buffered transmit and receive

— Master or slave mode; MSB-first or LSB-first shifting

• Inter-integrated circuit (IIC) interface

— Up to 100 kbps baud rate with maximum bus loading

— Baud rates as high as 800 kbps can be programmed

— Multi-master operation

— Programmable slave address

— Interrupt driven byte-by-byte data transfer

— Supports broadcast mode and 10-bit addressing

• Four 16-bit timer/pulse width modulators (TPM[4:1]) — each TPM module has an assigned GPIO

pin and provides

— Single channel capability

— Input capture

— Output compare

— Buffered edge-aligned or center-aligned PWM

• 8-Channel, 12-bit resolution ADC (available only in MC13237)

— 11.2 Effective Number of Bits (ENOB)

— 2.5 s conversion time

— Internal 1.7 mV/C temperature sensor

— Internal bandgap reference

— Operation in Stop3

— Fully functional from 1.8 V to 3.6 V

• Carrier modulator timer (CMT) — IR remote carrier generator, modulator, and transmitter.

• Real-time counter (RTC)

— 16-bit modulus counter with binary or decimal based prescaler;

— External clock source for precise time base, time-of-day, calendar or task scheduling functions

— Capable of greater than one day interrupt.

• System protection features

— Programmable low voltage warning and interrupt (LVI)

— Optional watchdog timer (COP)

— Illegal opcode detection

• 1.8 V to 3.6 V operating voltage with on-chip voltage regulators.

• Up to 32 GPIO

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

6Freescale Semiconductor

— MC13234: 32 GPIOs

— MC13237: 28 GPIOs

— Hysteresis and selectable pullup resistors on all input pins

— Configurable slew rate and drive strength on all output pins

• –40°C to +85°C operating temperature range

• RoHS-compliant 7 x 7 mm 48-pin LGA package

2.3 Software solutions

Freescale provides a powerful software environment called the Freescale BeeKit Wireless Connectivity

Toolkit. BeeKit is a comprehensive codebase of wireless networking libraries, application templates, and

sample applications. The BeeKit Graphical User Interface (GUI), part of the BeeKit W ireless Connectivity

Toolkit, allows users to create, modify, and update various wireless networking implementations. A wide

range of software functionality is available to complement the MC13234/MC13237 and these are provided

as codebases within BeeKit. The following sections describe the available tools, however due to

continuous updates that occur on FSL software inquiries to applications engineering is recommended.

Table 2. MC13234 and MC13237 Comparison

Feature MC13234 MC13237

Radio IEEE 802.15.4 compliant

CPU 32 MHz HCS08

Flash memory 128K

RAM 8K

BDM Yes

Low power modes Yes

KBI Two (12 interrupts) One (8 interrupts)

SCI Yes

SPI Yes

IIC Yes

TPM Yes

CMT Yes

RTC Yes

LVD Yes

COP Yes

ADC No Yes

GPIO 32 28

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 7

2.3.1 Simple Media Access Controller (SMAC)

The Freescale Simple Media Access Controller (SMAC) is a simple ANSI C based code stack available

as sample source code. The SMAC can be used for developing proprietary RF transceiver applications

using the MC13234/MC13237.

• Supports point-to-point and star network configurations

• Proprietary networks

• Source code and application examples provided

2.3.2 IEEE® 802.15.4 2006 Standard-Compliant MAC

The Freescale 802.15.4 Standard-Compliant MAC is a code stack available as object code. The 802.15.4

MAC can be used for developing MC13234/MC13237 networking applications based on the full IEEE®

802.15.4 Standard that use custom Network Layer and application software.

• Supports star, mesh, and cluster tree topologies

• Supports beaconed networks

• Supports GTS for low latency

• Multiple power saving modes

• AES-128 security module

• 802.15.4 sequence support

• 802.15.4 receiver frame filtering.

2.3.3 SynkroRF platform

The SynkroRF Network is a general purpose, proprietary networking layer that sits on top of the IEEE®

802.15.4 MAC and PHY layers. It is designed for wireless personal area networks (WPANs) and conveys

information over short distances among the participants in the network. It enables small, power ef ficient,

inexpensive solutions to be implemented for a wide range of applications. Some key characteristics of an

SynkroRF network are:

• An over-the-air data rate of 250 kbps in the 2.4 GHz band.

• 3 independent communication channels in the 2.4 GHz band (15, 20, and 25).

• 2 network node types, controller and controlled nodes.

• Channel agility mechanism.

• Low latency TX mode automatically enabled in conditions of radio interference.

• Fragmented mode transmission and reception, automatically enabled in conditions of radio

interference.

• Robustness and ease of use.

• Essential functionality to build and support a CE network.

The SynkroRF network layer uses components from the standard HC(S)08 Freescale platform, which is

also used by the Freescale’s implementations of 802.15.4. MAC and ZigBee™ layers. For more details

about the platform components, see the Freescale Platform Reference Manual.

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

8Freescale Semiconductor

2.3.4 BeeStack Consumer

Freescale’s ZigBee RF4CE stack, called BeeS tack Consumer, is a networking layer that sits on top of the

IEEE® 802.15.4 MAC and PHY layers. It is designed for standards-based wireless personal area networks

(WPANs) of home entertainment products and conveys information over short distances among the

participants in the network. It enables small, power ef ficient, inexpensive solutions to be implemented for

a wide range of applications. T argeted applications include DTV, set top box, A/V receivers, DVD players,

security, and other consumer products.

Some key characteristics of a BeeStack Consumer network are:

• An over-the-air data rate of 250 kbps in the 2.4 GHz band

• 3 independent communication channels in the 2.4 GHz band

• 2 network node types, controller node and target node

• Channel agility mechanism

• Provides robustness and ease of use

• Includes essential functionality to build and support a CE network

The BeeStack Consumer layer uses components from the standard HCS08 Freescale platform, which is

also used by the Freescale implementations of 802.15.4. MAC or ZigBee™ layers. For more details about

the platform components, see the Freescale Platform Reference Manual.

2.3.5 ZigBee-Compliant Network Stack

Freescale’s BeeStack architecture builds on the ZigBee protocol stack. Based on the OSI Seven-Layer

model, the ZigBee stack ensures inter-operability among networked devices. The physical (PHY), media

access control (MAC), and network (NWK) layers create the foundation for the application (APL) layers.

BeeS tack defines additional services to improve the communication between layers of the protocol stack.

At the application layer , the application support layer (ASL) facilitates information exchange between the

application support sub-layer (APS) and application objects. Finally, ZigBee Device Objects (ZDO), in

addition to other manufacturer- designed applications, allow for a wide range of useful tasks applicable to

home and industrial automation.

BeeS tack uses the IEEE 802.15.4-compliant MAC/PHY layer that is not part of ZigBee itself. The NWK

layer defines routing, network creation and configuration, and device synchronization. The application

framework (AF) supports a rich array of services that define ZigBee functionality. ZigBee Device Objects

(ZDO) implement application-level services in all nodes via profiles. A security service provider (SSP) is

available to the layers that use encryption (NWK and APS), i.e., Advanced Encryption Standard (AES)

128-bit security.

The complete Freescale BeeStack protocol stack includes the following components:

• ZigBee Device Objects (ZDO) and ZigBee Device Profile (ZDP)

• Application support sub-layer (APS)

• Application framework (AF)

• Network (NWK) layer

• Security service provider (SSP)

• IEEE 802.15.4-compliant MAC and Physical (PHY) layer

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 9

3 Integrated IEEE 802.15.4 Transceiver (radio and

modem)

The MC13234/MC13237 is a IEEE® 802.15.4 fully-compliant transceiver providing a complete 2.4 GHz

radio solution with 250 kbps offset-quadrature phase shift keying (O-QPSK) data in 5.0 MHz channel

spacings with full spread-spectrum encode and decode. The modem supports the full requirement of the

IEEE® 802.15.4 Standard functionality to transmit, receive, and do clear channel assessment (CCA),

energy detect (ED), and link quality indication (LQI). Some top level transceiver features supported are

listed below:

• Programmable output power with 0 dBm nominal output power, programmable from –30 dBm to

+2 dBm typical

• Receive sensitivity of –93 dBm (typical) at 1% PER, 20-byte packet

• Differential bidirectional RF input/output port

• Integrated transmit/receive switch

• Receive current can be reduced while waiting or listening for an incoming frame using partial

power down (PPD) mode1 (see Table 11)

3.1 RF interface and usage

The MC13234/MC13237 RF interface provides a bidirectional, differential port that connects directly to

a balun. The balun connects directly to a single-ended antenna and converts that interface to a full

differential, bidirectional, on-chip interface with transmit/receive switch, LNA, and complementary PA

outputs. This combination allows for a small footprint and low cost RF solution to be realized.

3.2 Transceiver register interface and operation

The transceiver is controlled by set of interface registers that are memory-mapped into the CPU address

space. MC13234/MC13237 supports independent transmit, receive, or CCA/ED (energy detection) modes

of operation and combinations. Additional features of the transceiver include:

• DMA function that moves data directly between RAM and transceiver buffers during diplexed

transmit and receive operation on a cycle-steal basis. This feature offloads the data transfer from

the CPU, thus providing higher performance.

• Interrupt capability that is dependent on RX packet data availability. An interrupt can be generated

based on a programmed count of RX data bytes that have been received and moved to RAM. This

allows CPU filtering of RX data before completion of the packet reception to accelerate response

to the packet.

• Four (4) transceiver event timer comparators to supplement MCU peripheral timer resources for

PHY and MAC timing requirements.

3.3 IEEE 802.15.4 acceleration hardware

MC13234/MC13237 transceiver has several hardware features to reduce the software stack size, offload

the function from the CPU, and improve performance. A list of features supported is provided below:

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

10 Freescale Semiconductor

• 2003 & 2006 versions of the IEEE® 802.15.4 standard is full supported.

• Slotted and unslotted modes

• Beacon enabled and non-beacon enabled networks

• DMA data transfer between RAM and radio

• Separate AES-128 security module

• 16-bit random number generator

• 802.15.4 sequence support

— RX (conditionally followed by TXAck)

—TX

— CCA (used for CCA and ED cycles)

— TX/RX (TX followed by unconditional RX or RCACK)

— Continuous CCA

• 802.15.4 receiver frame filtering

3.4 Partial Power Down Receive mode (PPD_RX)

The MC13234/MC13237 provides a unique Partial Power Down Receive (PPD_RX) mode. A summary

of PPD_RX mode of operation when selected is described below:

• Whenever a receive cycle is initiated, the receiver is not turned fully on to save current until receive

energy of a preset level is detected

• The receiver will turn fully on only when triggered by ener gy at a pre-determined preset level thus

enabling reception of the expected frame. Afterwards, the receiver will begin operating in the

full-on state that is considered to be the same as the standard receive state

• The preset level can be programmed for various RX input power levels

Use of the PPD_RX mode provides two distinct advantages:

• Reduced “Listen” mode current — The receive current is significantly reduced while waiting for

a frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its

RF-active time waiting for incoming frames from clients or other devices, the net power savings

can be significant.

• Reduced sensitivity as a desired effect — The PPD_RX mode provi des different levels of reduced

sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the

receiver such that the device does not respond to incoming frames with an energy level below the

desired threshold. This could be useful for security, net efficiency, reduced noise triggering, and

many other purposes.

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 11

4 HCS08 8-bit central processing unit (CPU)

The onboard CPU is a 32 MHz 8-bit HCS08 core. It executes a super set of the 68HC08 instruction set

with added BGND instructions. The HCS08 CPU is fully source and object code compatible with the

M68HC08 CPU. Several instructions and enhanced addressing modes are added to improve C compiler

efficiency and to support a new background debug system. It has an 8-bit data bus, a 16-bit address bus,

and a 2-stage instruction pipe that facilitates the overlapping of instruction fetching and execution. There

are 29 vectors for internal interrupt sources and one vector for an external interrupt pin. The debug or BDM

module provides a serial one-wire interface for non-intrusive debugging of application programs.

Features of the HCS08 CPU include:

• Object code fully upward-compatible with M68HC05 and M68HC08 Families

• 64-KB CPU address space with banked memory management unit for greater than 64 KB

• 16-bit stack pointer (any size stack anywhere in 64-KB CPU address space)

• 16-bit index register (H:X) with powerful indexed addressing modes

• 8-bit accumulator (A)

• Many instructions treat X as a second general-purpose 8-bit register

• Seven addressing modes:

— Inherent — Operands in internal registers

— Relative — 8-bit signed offset to branch destination

— Immediate — Operand in next object code byte(s)

— Direct — Operand in memory at 0x0000–0x00FF

— Extended — Operand anywhere in 64-KB address space

— Indexed relative to H:X — Five submodes including auto increment

— Indexed relative to SP — Improves C efficiency dramatically

• Memory-to-memory data move instructions with four address mode combinations

• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on

the results of signed, unsigned, and binary-coded decimal (BCD) operations

• Efficient bit manipulation instructions

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• STOP and WAIT instructions to invoke low-power operating modes

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

12 Freescale Semiconductor

5 System clocks

The primary system reference frequency is a 32 MHz crystal oscillator. The crystal requirements for the

oscillator and oscillator performance must support a +/–40 ppm frequency accuracy to meet the IEEE®

802.15.4 Standard requirements. All system clocks are generated from this source. Features of the clock

system include:

• The 32 MHz reference oscillator has onboard programmable capacitive loading that allows

software tuning of frequency accuracy

• CPU clock as high as 32 MHz

• Bus clock (and peripheral clock) equals 1/2 CPU clock

• Clocks to individual peripherals can be independently disabled for best power management

• CPU clock can be lowered to 500 kHz for lower power (250 kHz bus clock)

An optional 32.768 kHz crystal oscillator is available for accurate low power timing and the real time clock

(RTC). Also, an onboard, low accuracy 1 kHz oscillator is available for sleep timing wake-up.

6Memory

The MC13234/MC13237 memory resources consist of RAM, Flash program memory for nonvolatile data

storage, control/status registers for I/O, peripherals, management, and the transceiver. Features include:

• 128 Kbyte flash

• 8 Kbyte SRAM

• Security circuitry to prevent unauthorized access to RAM and flash contents

7 System and power management

MC13234/MC13237 is a low power device that also supports extensive system control and power

management modes to maximize battery life and provide system protection.

7.1 Modes of operation

The MC13234/MC13237 modes of operation include:

• Active background mode for code development

• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 13

• LPRun mode — CPU clock is set to 500 kHz and peripheral clocks (bus clock) to 250 kHz and the

internal voltage regulators are in standby

• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation

is maintained

• LPWait mode — CPU shuts down to conserve power; peripheral clocks are restricted to 250 kHz

and the internal voltage regulator is in standby

• Stop modes — System clocks are stopped and voltage regulator is in standby

— S top3 — All internal circuits are powered for fast recovery (32 MHz oscillator on-off optional)

NOTE: See Table 9 for further details on modes of operation

7.2 Power management

The MC13234/MC13237 power management is controlled through programming of the modes of

operation. Different modes allow for different levels of power-down. Additional features include:

• The transceiver is powered as required

• The analog radio is only powered-up as required to do a TX, RX, or CCA/ED operation

• Peripheral control clock gating can be disabled on an MCU module-by-module basis to provide

lowest power

• Programmed mode manages

— Degree of chip power down

— Retention of programmed parameters

— Clock management

• Power-down and wake-up (clocks and analog blocks) are gracefully controlled

• RTC can be used as wake-up timer

• Wake-up available through KBI and UART RX asynchronous interrupts

• Real-time counter (RTC) module

— 16-bit modulus counter with binary or decimal based prescaler for precise time base,

time-of-day, calendar or task scheduling functions

— Capable of greater than one day interrupt

— Can also be used for device wake-up

7.3 System protection

The MC13234/MC13237 provides several vehicles to maintain security or a high level of system

robustness:

• Watchdog computer operating properly (COP) reset with option to run from dedicated internal

clock source or bus clock

• Low-voltage warning and detection with reset or interrupt; selectable trip points

• Illegal opcode detection with reset

• Flash block protection

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

14 Freescale Semiconductor

8 MCU peripherals

The MC13234/MC13237 has a functional set of MCU peripherals focused for intended applications. For

further information on application use-cases please refer to the Reference Manual.

8.1 Parallel input/output (GPIO)

MC13234 and MC13237 have 32 and 28 general purpose I/O signals, respectively. These GPIO signals

are distributed among four I/O ports (PTA, PTB, PTC, and PTD). Many of these pins are shared with

on-chip peripherals such as timer systems, communication ports, or keyboard interrupts. When these other

modules are not controlling the port pins, they revert to general-purpose I/O control. For each I/O pin, a

port data bit provides access to input (read) and output (write) data, a data direction bit controls the

direction of the pin, and a pullup enable bit enables an internal pullup device (provided the pin is

configured as an input), and a slew rate control bit controls the rise and fall times of the pins.

Parallel I/O features include:

• A total of 32 or 28 general-purpose I/O pins in four ports (PTA2 is output only)

• Hysteresis input buffers

• Software-controlled pullups on each input pin

• Software-controlled slew rate output buffers

8.2 Keyboard interrupt modules (KBI)

MC13234 has two (2) KBI modules; KBI1 shares eight (8) port B pins and KBI2 shares four (4) port C

pins. MC13237 has one (1) KBI module; KBI1 shares eight (8) port B pins. Any KBI pin can be enabled

as a keyboard input that can act as an interrupt request. As a result, the total 12 KBI inputs (MC13234)

allows as large as a 12x12 keyboard matrix. The total 8 KBI inputs (MC13237) allows as large as a 8x8

keyboard matrix with use of other GPIO pins as outputs to the matrix.

All enabled KBI inputs can be configured for edge-only sensitivity or edge-and-level sensitivity . They also

can be configured for either rising edge / high-level or falling-edge/low-level sensitivity. When enabled

for rising edge / high level sensitivity, a pulldown resistor is enabled, and when enabled for falling edge /

low level sensitivity, a pullup resistor is enabled.

The KBI features include:

• KBI1 has eight (8) keyboard interrupt pins with individual pin enable bits.

• KBI2 (available only in MC13234) has four (4) keyboard interrupt pins with individual pin enable

bits.

• Supports up to a 12x12 (MC13234) or 8x8 (MC13237) keyboard matrix. An 8x8 matrix

(MC13234) or 4x4 (MC13237) matrix can be supported without impacting other I/O functions.

• Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling

edge and low level (or both rising edge and high level) interrupt sensitivity. pullups and pulldowns

enabled by selected mode.

• Individual signal software enabled interrupts for KBI1 and KBI2.

• Can be used for device wake-up

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 15

8.3 Serial communications interface (SCI) module

The MC13234/MC13237 has one serial communications interface module — sometimes called a universal

asynchronous receiver/transmitter (UART). Typically, this port is used to connect to the RS232 serial

input/output (I/O) port of a personal computer or workstation, and it can also be used to communicate with

other embedded controllers.

The SCI module has a single, flexible frac-N (13-bit modulo counter, 5-bit fractional counter) baud rate

generator used both for transmit and receive. With a maximum 16 MHz peripheral clock, baud rates as

high as 1 Mbps can be supported (standard is 921,600 baud).

This SCI system offers many advanced features not commonly found on other asynchronous serial I/O

peripherals on other embedded controllers. The receiver employs an advanced data sampling technique

that ensures reliable communication and noise detection. Hardware parity, receiver wake-up, and double

buffering on transmit and receive are also included.

Features of SCI module include:

• Dedicated TXD and RXD pins

• Full-duplex, standard non-return-to-zero (NRZ) format

• Double-buffered transmitter and receiver with separate enables

• Programmable high accuracy baud rates (frac-N generator)

• Interrupt-driven or polled operation:

— Transmit data register empty and transmission complete

— Receive data register full

— Receive overrun, parity error, framing error, and noise error

— Idle receiver detect

— Active edge on receive pin

— Break detect supporting LIN

• Hardware parity generation and checking

• Programmable 8-bit or 9-bit character length

• Receiver wake-up by idle-line or address-mark

• Optional 13-bit break character generation / 11-bit break character detection

• Selectable transmitter output polarity

8.4 Serial peripheral interface (SPI) module

The MC13234/MC13237 has one serial peripheral interface module. The SPI is a synchronous serial data

input/output port used for interfacing with serial memories, peripheral devices, or other processors. The

SPI allows an 8-bit serial bit stream to be shifted simultaneously into and out of the device at a

programmed bit-transfer rate (called 4-wire mode). There are four (4) pins associated with the SPI port

(SPICLK, MOSI, MISO, and SS).

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

16 Freescale Semiconductor

The SPI module can be programmed for master or slave operation. It also supports a 3-wire mode where

for master mode the MOSI becomes MOMI, a bidirectional data pin, and for slave mode the MISO

becomes SISO, a bidirectional data pin. In 3-wire mode, data is transferred in only one direction at a time.

The SPI bit clock is derived from the peripheral input clock with a maximum 16 MHz operation. A

programmable prescaler (maximum divide-by-8) drives a second baud rate programmable divider

(maximum divide-by-256) to develop the bit clock. The maximum SPI transfer rate is 8 MHz.

Features of the SPI module include:

• Master or slave mode operation

• Full-duplex or single-wire bidirectional option

• 8-bit only transfer size

• Programmable transmit bit rate (8 MHz max)

• Double-buffered transmit and receive

• Serial clock phase and polarity options (supports all 4 options)

• Optional slave select output

• Selectable MSB-first or LSB-first shifting

8.5 Inter-integrated circuit (IIC) interface module

The MC13234/MC13237 has one inter-integrated circuit interface module that provides a method of

communication between a number of other integrated circuits. The IIC Bus interface provides a

bidirectional, 2-pin (SDA bus data and SCL bus clock) serial bus designed to operate up to 100 kbps with

maximum bus loading and timing. The module is capable of operating at higher baud rates, up to a

maximum of peripheral clock/20 (800 kbps), with reduced bus loading.

Features of IIC module include:

• Compatible with IIC bus standard

• Multi-master operation

• Software programmable clock frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• START and STOP signal generation/detection

• Repeated START signal generation

• Acknowledge bit generation/detection

• Bus busy detection

• General call recognition

• 10-bit address extension

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 17

8.6 Timer/PWM (TPM) modules

The MC13234/MC13237 has four (4) independent timer/PWM modules, each with one channel. Each

TPM module is based on a 16-bit counter and provides input capture, output compare, and Pulse Width

Modulation (PWM). Each TPM module has one associated I/O pin for input capture or counter/PWM

output.

TPM module features include:

• Each TPM may be configured for buffered, center -aligned pulse-width modulation (CPWM) on all

channels

• Module clock source is peripheral clock or reference oscillator divided-by-1024

• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128

• 16-bit free-running or up/down (CPWM) count operation

• 16-bit modulus register to control counter range

• Module enable

• One interrupt per channel plus a terminal count interrupt for each TPM module

• Channel features:

— Each channel may be input capture, output compare, or buffered edge-aligned PWM

— Rising-edge, falling-edge, or any-edge input capture trigger

— Set, clear, or toggle output compare action

— Selectable polarity on PWM outputs

8.7 Carrier Modulator Timer (CMT) Module

The MC13234/MC13237 Carrier Modulator Timer module is intended as an IR LED driver for remote

control “blaster” applications. The module consists of a carrier generator, modulator, and transmitter that

drives data to package pin # 31 (PTD4/CMT/AD3) either in baseband or in FSK mode. The CMT.../IRO

pin drives (modulates) the IR diode directly or through a buffer depending on the applications current

requirement. The current drive capability of this pin is specified for 20mA.

The CMT module features include:

• Four (4) modes of operation:

— Time with independent control of high and low times

— Baseband

— Frequency Shift Key (FSK)

— Direct software control of CMT....IRO pin

• Extended space operation in time, baseband, and FSK modes

• Module clock source is peripheral clock (16 MHz max)

• Interrupt on end of cycle

• Ability to disable CMT...IRO pin and use as timer interrupt

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

18 Freescale Semiconductor

8.8 Real Time Counter (RTC) Module

The MC13234/MC13237 Real Time Counter module consists of one(1) 16-bit counter, one(1) 16-bit

comparator, several binary-based and decimal-based prescaler dividers, three (3) clock sources, and one(1)

programmable periodic interrupt. This module can be used for time-of-day, calendar or any task

scheduling functions. It can also serve as a cyclic wake-up from low power modes (Stop2, Stop3, and

Wait). RTC can be clocked from bus clock, the optional 32.768 kHz oscillator or the onboard 1 kHz low

power oscillator.

Features of the RTC module include:

• 16-bit up-counter

— 16-bit modulo match limit

— Software controllable periodic interrupt on match

• Three software selectable clock sources for input to prescaler with programmable 16 bit prescaler

— 32.768 kHz optional crystal oscillator.

— 32 MHz reference oscillator

— 1 kHz low power RC oscillator

• Useful for time base tick or time-of-day clock

• Can be used for device wake-up; capable of greater than one day time-out period.

8.9 12-Bit Analog-to-Digital Conversion (ADC) Module

The MC13237 integrates an 8 channel, 12-bit resolution Successive Approximation Register (SAR)

analog-to-digital conversion (ADC) module. The analog input channels are shared/multiplexed with

standard GPIO pins as shown in Figure 3. The ADC module is available in MC13237 only; not available

in MC13234.

Features of the ADC module include:

• 11.2 Effective Number of Bits (ENOB)

• Linear successive approximation algorithm with 12-bits resolution

• Operation in Stop3 mode

• 2.5 s conversion time

• Internal bandgap reference

• Operation over full VBATT voltage range

• Internal 1.7 mV/°C temperature sensor

• Output data can be formatted in 8-, 10-, or 12-bit justified format

• Single or continuous conversion

• Configurable sample time and conversion speed / power.

• Auto compare for less-than, greater than, or equal to programmable value

• Converter subsystem shut-down

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 19

9 Development Environment

Development support for the HCS08 on the MC13234/MC13237 includes the background debug

controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire (signal BKGD)

debug interface to the MCU that provides a convenient interface for programming the on-chip flash and

other storage. The BDC is also the primary debug interface for development and allows non-intrusive

access to memory data and traditional debug features such as CPU register modify , breakpoints, and single

instruction trace commands.

Address and data bus signals are not available on external pins. Debug is done through commands fed into

the MCU via the single-wire background debug interface. The debug module provides a means to

selectively trigger and capture bus information so an external development system can reconstruct what

happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data

signals. Features include:

• Single-wire background debug interface

• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two

more breakpoints in on-chip debug module)

• On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger

modes.

• Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module

supports both tag and force breakpoints.

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

20 Freescale Semiconductor

10 Pin Assignment and Connections

10.1 Device Pin Assignments

Figure 2. MC13234 Pinout

16 24

18 23

PTC6/MISO

PTD7

VBATT_1

VREG_ANA

RF_BIAS

EXTAL_32M

PTB3/KBIP3

15 17

PTC0/KBI2P0

PTA5/SDA

PTA7/BKGD/MS

PTC5/SS

RF_P

PTA2

PTA3/IRQ

PTA0/XTAL_32K

VBATT_4

PTA6/SCL

PTC4/SPICLK

PTC1/KBI2P1

PTC2/KBI2P2

RESET

39 38 37

4748 4243

45 44 4146

VREG_LO2

VBATT_2

RF_N

VDD_ANA

VREG_VCO

VBATT_3

PTB4/KBIP4

PTB7/KBIP7

PTB5/KBIP5

PTB6/KBIP6

XTAL_32M

PTC7/MOSI

PTD6/RXD

PTD5/TXD

PTD4/CMT

PTD1/TPM1

PTD0/TPM0

PTC3/KBI2P3

PTA1/EXTAL_32K

PTA4/XTAL_32KOUT

PTB2/KBI1P2

PTB1/KBI1P1

PTB0/KBI1P0

MC13234CHT

PTD2/TPM2

PTD3/TPM3

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 21

Figure 3. MC13237 Pinout

16 24

18 23

PTC6/MISO

PTD7/AD6

VBATT_1

VREG_ANA

RF_BIAS

EXTAL_32M

PTB3/KBIP3

15 17

PTC5/SS/AD7

PTA5/SDA

PTA7/BKGD/MS

PTC4/SPICLK

RF_P

PTA2

PTA3/IRQ

PTA0/XTAL_32K

VBATT_4

PTA6/SCL

VDDA_ADC

VSSA_ADC

VREFL

RESET

39 38 37

48 4243

45 44 4146

VREG_LO2

VBATT_2

RF_N

VDD_ANA

VREG_VCO

VBATT_3

PTB4/KBIP4

PTB7/KBIP7

PTB5/KBIP5

PTB6/KBIP6

XTAL_32M

PTC7/MOSI

PTD6/RXD/AD5

PTD5/TXD/AD4

PTD4/CMT/AD3

PTD1/TPM1/AD0

PTD0/TPM0

VREFH

PTA1/EXTAL_32K

PTA4/XTAL_32KOUT

PTB2/KBI1P2

PTB1/KBI1P1

PTB0/KBI1P0

MC13237CHT

PTD2/TPM2/AD1

PTD3/TPM3/AD2

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

22 Freescale Semiconductor

10.2 Pin Definitions

Table 4 details the MC13234 pinout and functionality.

Table 3. MC13234 Pin Function Description

Pin # Pin Name Type Description Functionality

1 PTA0/XTAL_32K Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator

output

2 PT A1/EXT AL_32K Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator input For normal use, 10 kOhm resistor

to ground recommended

3 RESET Digital Input/Output Device asynchronous hardware reset.

Active low. Onboard Pullup Normally input; gets driven low for

a period af ter a reset

4 PTA2 Digital Output Port A Bit 2 / Test Mode enable. TM mode input. Must be biased

low exiting POR for normal

operation

5 PTA3/ IRQ Digital Input/Output Port A Bit 3 / IRQ.

6PTA4/

XTAL_32KOUT Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz clock

output Optional 32.768 kHz output clock

for measuring 32 kHz oscillator

accuracy (ppm)

7 PTA5/SDA Digital Input/Output Port A Bit 5 / IIC Bus data Defaults to open drain for IIC

8 PTA6/SCL Digital Input/Output Port A Bit 6 / IIC Bus clock Defaults to open drain for IIC

9 PT A7/BKGD/MS Digital Input/Output Port A Bit 7 / Background / Mode Select Debug signal

10 PTB0/KBI1P0 Digital Input/Output Port B Bit 0 / KBI1 Input Bit 0 Wake-up capability

11 PTB1/KBI1P1 Digital Input/Output Port B Bit 1 / KBI1 Input Bit 1 Wake-up capability

12 PTB2/KBI1P2 Digital Input/Output Port B Bit 2 / KBI1 Input Bit 2 Wake-up capability

13 PTB3/KBI1P3 Digital Input/Output Port B Bit 3 / KBI1 Input Bit 3 Wake-up capability

14 PTB4/KBI1P4 Digital Input/Output Port B Bit 4 / KBI1 Input Bit 4 Wake-up capability

15 PTB5/KBI1P5 Digital Input/Output Port B Bit 5 / KBI1 Input Bit 5 Wake-up capability

16 PTB6/KBI1P6 Digital Input/Output Port B Bit 6 / KBI1 Input Bit 6 Wake-up capability

17 PTB7/KBI1P7 Digital Input/Output Port B Bit 7 / KBI1 Input Bit 7 Wake-up capability

18 PTC0/KBI2P0 Digital Input/Output Port C Bit 0 / KBI2 Input Bit 0

19 VBATT_4 Power Input VDD supply input 1Connect to system VDD supply

20 PTC1/KBI2P1 Digital Input/Output Pot C Bit 1 / KBI2 Input Bit 1

21 PTC2/KBI2P2 Digital Input/Output Pot C Bit 2 / KBI2 Input Bit 2

22 PTC3/KBI2P3 Digital Input/Output Pot C Bit 3 / KBI2 Input Bit 3

23 PTC4/SPICLK Digital Input/Output Port C Bit 4 / SPI clock

24 PTC5/SS Digital Input/Output Port C Bit 5 / SPI slave select

25 PTC6/MISO Digital Input/Output Port C Bit 6 / SPI MISO

26 PTC7/MO SI/ 32M_O UT Digital Input/Output Port C Bit 7 / SPI MOSI / 32 MHz XT AL

output

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

Freescale Semiconductor 23

27 PTD0/TPM0 Digital Input/Output Port D Bit 0 / TPM0 signal TPM0 timer output / gate input

signal

28 PTD1/TPM1 Digital Input/Output Port D Bit 1/ TPM1 signal TPM1 timer output / gate input

signal.

29 PTD2/TPM2 Digital Input/Output Port D Bit 2 / TPM2 signal TPM2 timer output / gate input

signal.

30 PTD3/TPM3 Digital Input/Output Port D Bit 3 / TPM3 signal TPM3 timer output / gate input

signal.

31 PTD4/CMT Digital Input/Output Port D Bit 4 / CMT output Hi drive output for IR diode.

32 PTD5/TXD Digital Input/Output Port D Bit 5 / UART TXD output UART has no hardware flow

control.

33 PTD6/RXD Digital Input/Output Port D Bit 6 / UART RXD input / AD5

signal UART has no hardware flow

control.

34 PTD7 Digital Input/Output Port D Bit 7

35 XTAL_32M Analog Output 32 MHz reference oscillator output

36 EXTAL_32M Analog input 32 MHz reference oscillator input

37 VBATT_3 Power Input VDD supply input1Connect to system VDD supply

38 VREG_VCO VCO Reg Out / in VCO regulator output and input to VCO

1.8 Vdc VDD Bypass to ground with 220 nF

capacitor.

39 VDD_ANA Analog Power Input Analog 1.8 Vdc Input Connect to VREG_ANA

40 NC No connection to device May be left open or connect to

ground

41 RF_N RF Input/Output Modem RF input/output negative Bi-directional RF port for the

internal LNA an d PA

42 RF_P RF Input/Output Modem RF input/output positive Bi-directional RF port for the

internal LNA an d PA

43 RF_BIAS RF Voltage Output Switched RF bias voltage (1.8 Vdc) High for TX; low for RX

44 VBATT_2 Power Input VDD supply input1Connect to system VDD supply

45 NC May be left open or connect to

ground

46 VREG_LO2 LO2 Reg Out LO2 regulator output @ 1.8 Vdc Bypass to ground with 220 nF

capacitor.

47 VREG_ANA ANA Reg Out Analog regulator output @ 1.8 Vdc Bypass to ground with 220 nF

capacitor. Connect to VDD_ANA

48 VBATT_1 Power Input VDD supply to Analog regulator1Connect to system VDD supply

Flag GND Power Input System ground

1VBATT_1, VBATT_2, VBATT_3 and VBATT_4 signals are not connected onboard MC13234/MC13237.

Table 3. MC13234 Pin Function Description (continue d)

Pin # Pin Name Type Description Functionality

MC13234/MC13237 Advance Information Data Sheet, Rev. 1.3

24 Freescale Semiconductor

Table 4 details the MC13237 pinout and functionality.

Table 4. MC13237 Pin Function Description

Pin # Pin Name Type Description Functionality

1 PTA0/XTAL_32K Digital Input/Output Port A Bit 0 / 32.768 kHz oscillator

output

2 PTA1/EXTAL_32K Digital Input/Output Port A Bit 1 / 32.768 kHz oscillator

input For normal use, 10 kOhm resistor

to ground recommended

3 RESET Digital Input/Output Device asynchronous hardware reset.

Active low. Onboard Pullup Normally input; gets driven low for

a period after a reset

4 PTA2 Digital Output Port A Bit 2 / Test Mode enable. TM mode input. Must be biased

low exiting POR for normal

operation

5 PTA3/IRQ Digital Input/Output Port A Bit 3 / IRQ.

6PTA4/

XTAL_32KOUT Digital Input/Output Port A Bit 4 / Buffered 32.768 kHz

clock output Optional 32.768 kHz output clock

for measuring 32 kHz oscillator

accuracy (ppm)

7 PTA5/SDA Digital Input/Output Port A Bit 5 / IIC Bus data Defaults to open drain for IIC

8 PTA6/SCL Digit al Input/Output Port A Bit 6 / IIC Bus clock Defaults to open drain for IIC

9 PTA7/BKGD/MS Digital Input/Output Port A Bit 7 / Background / Mode

Select Debug signal