Hot Pluggable X9522 Preliminary Information Laser Diode Control for Fiber Optic Modules Triple DCP, Dual Voltage Monitors FEATURES DESCRIPTION * Three Digitally Controlled Potentiometers (DCPs) --64 Tap - 10 k --100 Tap - 10 k --256 Tap - 100 k --Nonvolatile --Write Protect Function * 2-Wire industry standard Serial Interface * Dual Voltage Monitors --Programmable Threshold Voltages * Single Supply Operation --2.7 V to 5.5 V * Hot Pluggable * 20 Pin packages --XBGATM --TSSOP The X9522 combines three Digitally Controlled Potentiometers (DCPs), and two programmable voltage monitor inputs with software and hardware indicators. All functions of the X9522 are accessed by an industry standard 2-Wire serial interface. Two of the DCPs of the X9522 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The third DCP may be used to set other various reference quantities, or as a coarse trim for one of the other two DCPs.The programmable voltage monitors may be used for monitoring various module alarm levels. The features of the X9522 are ideally suited to simplifying the design of fiber optic modules. The integration of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules. BLOCK DIAGRAM RH0 WIPER COUNTER REGISTER RW0 RL0 8 WP 6 - BIT NONVOLATILE MEMORY PROTECT LOGIC RH1 SDA SCL WIPER COUNTER REGISTER DATA REGISTER RW1 RL1 COMMAND DECODE & CONTROL LOGIC 7 - BIT NONVOLATILE MEMORY CONSTAT REGISTER RH2 WIPER COUNTER REGISTER THRESHOLD RESET LOGIC RW2 RL2 2 VTRIP3 + VTRIP 2 + V3 V2 8 - BIT NONVOLATILE MEMORY V3RO V2RO Vcc / V1 (c)2000 Xicor Inc., Patents Pending REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 1 of 30 X9522 - Preliminary Information DETAILED DEVICE DESCRIPTION exceeds it's associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it's associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port. The X9522 combines three Xicor Digitally Controlled Potentiometer (DCP) devices, and two voltage monitors, in one package. These functions are suited to the control, support, and monitoring of various system parameters in fiber optic modules. The combination of the X9522 fucntionality lowers system cost, increases reliability, and reduces board space requirements using Xicor's unique XBGATM packaging. Xicor's unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. Two high resolution DCPs allow for the "set-and-forget" adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolution DCP may be used for setting sundry system parameters such as maximum laser output power (for eye safety requirements). The device features a 2-Wire interface and software protocol allowing operation on an I2CTM compatible serial bus. The dual Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage PIN CONFIGURATION XBGA 20 Pin TSSOP RH2 RW2 1 2 3 4 5 6 RL2 V3 V3RO NC WP SCL 7 8 SDA VSS 9 10 20 19 18 17 16 15 14 13 12 11 1 2 3 4 Vcc / V1 NC A V2RO V2 RL0 RW0 V2RO RL2 V2 NC RH2 V3 RW0 RL0 V3RO WP RH1 RH0 NC SCL VSS RW1 RL1 SDA B C RH0 RH1 V1 / Vcc RW2 D E RW1 RL1 Top View - Bumps Down NOT TO SCALE REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 2 of 30 X9522 - Preliminary Information PIN ASSIGNMENT Pin XBGA Name 1 B3 RH2 Function Connection to end of resistor array for (the 256 Tap) DCP 2. 2 A3 Rw2 Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 2. 3 A4 RL2 Connection to other end of resistor array for (the 256 Tap) DCP2. 4 B4 V3 V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the VTRIP3threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used. 5 C3 V3RO V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than VTRIP3and goes LOW when V3 is less than TRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external "pull-up" resistor. 7 C4 WP Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile "write" operations. Also, when the Write Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to "1"), then no "write" (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal "pull-down" resistor, thus if left floating the write protection feature is disabled. 8 D4 SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 9 E4 SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 10 E1 Vss Ground. 11 E3 RL1 Connection to other end of resistor for (the 100 Tap) DCP 1. 12 E2 Rw1 Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 1 13 D1 RH1 Connection to end of resistor array for (the 100 Tap) DCP 1. 14 D2 RH0 Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0. 15 C1 RW0 Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 0. 16 C2 RL0 Connection to the other end of resistor array for (the 64 Tap) DCP 0. 17 B1 V2 V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used. 18 A1 V2RO V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power up reset delay circuitry on this pin. The V2RO pin requires the use of an external "pull-up" resistor. 20 A2 Vcc / V1 6, 19 B2, D3 NC REV 1.1.6 9/14/01 Supply Voltage. No Connect www.xicor.com Characteristics subject to change without notice. 3 of 30 X9522 - Preliminary Information SCL SDA Data Stable Figure 1. Data Change Data Stable Valid Data Changes on the SDA Bus Serial Stop Condition PRINCIPLES OF OPERATION SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the X9522 operates as a slave in all applications. Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1.On power up of the X9522, the SDA pin is in the input mode. All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 2. Serial Acknowledge An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKNOWLEDGE that it received the eight bits of data. Refer to Figure 3. Serial Start Condition The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an ACKNOWLEDGE after the receipt of each subsequent eight bit word. All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 2. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an ACKNOWLEDGE. If an ACKNOWLEDGE is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will termi- SCL SDA Start Figure 2. REV 1.1.6 9/14/01 Stop Valid Start and Stop Conditions www.xicor.com Characteristics subject to change without notice. 4 of 30 X9522 - Preliminary Information SCL from Master Data Output from Transmitter Data Output from Receiver 1 8 9 Start Figure 3. Acknowledge Acknowledge Response From Receiver nate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state. DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9522 can be split up into two main parts: --Three Digitally Controlled Potentiometers (DCPs) --The next three bits (SA3 - SA1) are the Internal Device Address bits. Setting these bits to 111 internally selects the DCP structures in the X9522. The CONSTAT Register may be selected using the Internal Device Address 010.All other bit combinations are RESERVED. --The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer to Figure 4.) --Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9522 to be addressed, and specifies if a Read or Write operation is to be performed. SA7 SA6 SA5 1 0 1 Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte consists of three parts: --The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9522. SA1 SA0 R/W INTERNAL DEVICE ADDRESS READ / WRITE Internally Addressed Device 010 CONSTAT Register 111 DCP Others RESERVED Bit SA0 Operation 0 WRITE 1 READ Figure 4. www.xicor.com SA2 (SA3 - SA1) Internal Address Slave Address Byte SA3 0 DEVICE TYPE IDENTIFIER It should be noted that in order to perform a write operation to a DCP, the Write Enable Latch (WEL) bit must first be set. REV 1.1.6 9/14/01 SA4 Slave Address Format Characteristics subject to change without notice. 5 of 30 X9522 - Preliminary Information Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence (for either the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the final STOP condition), the X9522 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, no further Read or Write commands can be issued to the device. Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed. To perform acknowledge polling, the master issues a START condition followed by a Slave Address Byte. The Slave Address issued must contain a valid Internal Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is still busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the write operation, an ACKNOWLEDGE will be returned and the host can then proceed with a read or write operation. (Refer to Figure 5.). Issue Slave Address Byte (Read or Write) Issue STOP RESISTOR ARRAY 2 NON VOLATILE MEMORY (NVM) 1 0 RLx RWx Figure 6. DCP Internal Structure At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper (Rwx) output. Within each individual array, only one switch may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register. NO NO Issue STOP YES Continue normal Read or Write command sequence PROCEED REV 1.1.6 9/14/01 "WIPER" FET SWITCHES The X9522 includes three independent resistor arrays. These arrays respectively contain 63, 99 and 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHx and RLx inputs - where x = 0,1,2). YES Figure 5. DECODER DCP Functionality Issue START High Voltage Cycle complete. Continue command sequence? WIPER COUNTER REGISTER (WCR) DIGITALLY CONTROLLED POTENTIOMETERS Byte load completed by issuing STOP. Enter ACK Polling ACK returned? RHx N Acknowledge Polling Sequence On power up of the X9522, wiper position data is automatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The Table below shows the Initial Values of the DCP WCR's before the contents of the NVM is loaded into the WCR. DCP Initial Values Before Recall R0 / 64 TAP VH / TAP = 63 R1 / 100 TAP VL / TAP = 0 R2 / 256 TAP VH / TAP = 255 The data in the WCR is then decoded to select and enable one of the respective FET switches. A "make www.xicor.com Characteristics subject to change without notice. 6 of 30 X9522 - Preliminary Information Vcc Vcc (Max.) VTRIP ttrans tpu t 0 Maximum Wiper Recall time Figure 7. DCP Power up before break" sequence is used internally for the FET switches when the wiper is moved from one tap position to another. Hot Pluggability Figure 7 shows a typical waveform that the X9522 might experience in a Hot Pluggable situation. On power up, Vcc / V1 applied to the X9522 may exhibit some amount of ringing, before it settles to the required value. The device is designed such that the wiper terminal (RWx) is recalled to the correct position (as per the last stored in the DCP NVM), when the voltage applied to Vcc / V1 exceeds VTRIP for a time exceeding tpu. Therefore, if ttrans is defined as the time taken for Vcc / V1 to settle above VTRIP (Figure 7): then the desired wiper terminal position is recalled by (a maximum) time: ttrans + tpu. It should be noted that ttrans is determined by system hot plug conditions. DCP Operations In total there are three operations that can be performed on any internal DCP structure: --DCP Nonvolatile Write --DCP Volatile Write --DCP Read A nonvolatile write to a DCP will change the "wiper position" by simultaneously writing new data to the associated WCR and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after Vcc / V1 of the X9522 is powered down and then powered back up. A volatile write operation to a DCP however, changes the "wiper position" by writing new data to the associated REV 1.1.6 9/14/01 WCR only. The contents of the associated NVM register remains unchanged. Therefore, when Vcc / V1 to the device is powered down then back up, the "wiper position" reverts to that last position written to the DCP using a nonvolatile write operation. Both volatile and nonvolatile write operations are executed using a three byte command sequence: (DCP) Slave Address Byte, Instruction Byte, followed by a Data Byte (See Figure 9) A DCP Read operation allows the user to "read out" the current "wiper position" of the DCP, as stored in the associated WCR. This operation is executed using the Random Address Read command sequence, consisting of the (DCP) Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again (Refer to Figure 10.). Instruction Byte While the Slave Address Byte is used to select the DCP devices, an Instruction Byte is used to determine which DCP is being addressed. The Instruction Byte (Figure 8) is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to 1010111. In this case, the two Least Significant Bit's (I1 - I0) of the Instruction Byte are used to select the particular DCP (0 - 2). In the case of a Write to any of the DCPs (i.e. the LSB of the Slave Address is 0), the Most Significant Bit of the Instruction Byte (I7), determines the Write Type (WT) performed. If WT is "1", then a Nonvolatile Write to the DCP occurs. In this case, the "wiper position" of the DCP is changed by simultaneously writing new data to the associated WCR www.xicor.com Characteristics subject to change without notice. 7 of 30 X9522 - Preliminary Information I7 WT I6 I5 I4 I3 I2 0 0 0 0 0 WRITE TYPE I1 P1 The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9522 after the Slave Address, if it has been received correctly. I0 P0 Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to be written, while the WT bit determines if the Write is to be volatile or nonvolatile. If the Instruction Byte format is valid, another ACKNOWLEDGE is then returned by the X9522. DCP SELECT WT Description 0 Select a Volatile Write operation to be performed on the DCP pointed to by bits P1 and P0 1 Select a Nonvolatile Write operation to be performed on the DCP pointed to by bits P1 and P0 Following the Instruction Byte, a Data Byte is issued to the X9522 over SDA. The Data Byte contents is latched into the WCR of the DCP on the first rising edge of the clock signal, after the LSB of the Data Byte (D0) has been issued on SDA (See Figure 25). This bit has no effect when a Read operation is being performed. Figure 8. Instruction Byte Format The Data Byte determines the "wiper position" (which FET switch of the DCP resistive array is switched ON) of the DCP. The maximum value for the Data Byte depends upon which DCP is being addressed (see Table below). and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after Vcc / V1 of the X9522 has been powered down then powered back up If WT is "0" then a DCP Volatile Write is performed. This operation changes the DCP "wiper position" by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when Vcc / V1 to the device is powered down then back up, the "wiper position" reverts to that last written to the DCP using a nonvolatile write operation. P1- P0 A write to DCPx (x=0,1,2) can be performed using the three byte command sequence shown in Figure 9. In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See "WEL: Write Enable Latch (Volatile)" on page 10.) 0 1 0 1 1 1 0 A WT C K SLAVE ADDRESS BYTE Figure 9. REV 1.1.6 9/14/01 0 0 0 # Taps Max. Data Byte 0 0 x=0 64 3Fh 0 1 x=1 100 Refer to Appendix 1 1 0 x=2 256 FFh 1 1 Reserved Using a Data Byte larger than the values specified above results in the "wiper terminal" being set to the highest tap position. The "wiper position" does NOT roll-over to the lowest tap position. DCP Write Operation S 1 T A R T DCPx For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte maps one to one to the "wiper position" of the DCP "wiper terminal". Therefore, the Data Byte 00001111 (1510) corresponds to setting the "wiper terminal" to tap position 15. Similarly, the Data Byte 00011100 (2810) corresponds to 0 0 P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 INSTRUCTION BYTE A C K DATA BYTE S T O P DCP Write Command Sequence www.xicor.com Characteristics subject to change without notice. 8 of 30 X9522 - Preliminary Information WRITE Operation Signals from the Master SDA Bus Signals from the Slave S t a r t Slave Address Instruction Byte 10101110 W 00000 P P 1 0 T A C K S t a r t READ Operation Slave Address Data Byte S t o p 10101111 A C K "Dummy" write A C K DCPx - - x=0 - x=1 x=2 MSB LSB "-" = DON'T CARE Figure 10. DCP Read Sequence setting the "wiper terminal" to tap position 28. The mapping of the Data Byte to "wiper position" data for DCP1 (100 Tap), is shown in "APPENDIX 1". An example of a simple C language function which "translates" between the tap position (decimal) and the Data Byte (binary) for DCP1, is given in "APPENDIX 2". It should be noted that all writes to any DCP of the X9522 are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits P1=1, P0=1 is a reserved sequence, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA. The factory default setting of all "wiper position" settings is with 00h stored in the NVM of the DCPs. This corresponds to having the "wiper teminal" RWX (x=0,1,2) at the "lowest" tap position, Therefore, the resistance between RWX and RLX is a minimum (essentially only the Wiper Resistance, RW). DCP Read Operation A read of DCPx (x=0,1,2) can be performed using the three byte random read command sequence shown in Figure 10. The master issues the START condition and the Slave Address Byte 10101110 which specifies that a "dummy" write" is to be conducted. This "dummy" write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9522 after the Slave Address if received correctly. Next, an Instruction Byte is issued on SDA. Bits P1-P0 of the Instruction Byte determine which DCP "wiper position" is REV 1.1.6 9/14/01 to be read. In this case, the state of the WT bit is "don't care". If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9522. Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W bit set to 1. Then the X9522 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the "wiper position" (value of the WCR) of the DCP pointed to by bits P1 and P0. It should be noted that when reading out the data byte for DCP0 (64 Tap), the upper two most significant bits are "unknown" bits. For DCP1 (100 Tap), the upper most significant bit is an "unknown". For DCP2 (256 Tap) however, all bits of the data byte are relevant (See Figure 10). CONTROL AND STATUS REGISTER The Control and Status (CONSTAT) Register provides the user with a mechanism for changing and reading the status of various parameters of the X9522 (See Figure 11). The CONSTAT register is a combination of both volatile and nonvolatile bits. The nonvolatile bits of the CONSTAT register retain their stored values even when Vcc / V1 is powered down, then powered back up. The volatile bits however, will always power up to a known logic state "0" (irrespective of their value at power down). A detailed description of the function of each of the CONSTAT register bits follows: www.xicor.com Characteristics subject to change without notice. 9 of 30 X9522 - Preliminary Information CS7 0 CS6 CS5 CS4 CS3 V2OS V3OS 0 DWLK CS2 CS1 CS0 RWEL WEL 0 It must be noted that the RWEL bit can only be set, once the WEL bit has first been enabled (See "CONSTAT Register Write Operation"). The RWEL bit will reset itself to the default "0" state, in one of two cases: NV Bit(s) Description CS7 Always set to "0" (RESERVED) V2OS V2 Output Status flag --After a successful write operation to any bits of the CONSTAT register has been completed (See Figure 12). --When the X9522 is powered down. V3OS V3 Output Status flag CS4 Always set to "0" (RESERVED) DWLK Sets the DCP Write Lock RWEL Register Write Enable Latch bit WEL Write Enable Latch bit CS0 Always set to "0" (RESERVED) NOTE: Bits belled NV are nonvolatile (See "CONTROL AND STATUS REGISTER"). Figure 11. CONSTAT Register Format DWLK: DCP Write Lock bit - (Nonvolatile) The DCP Write Lock bit (DWLK) is used to inhibit a DCP write operation (changing the "wiper position"). When the DCP Write Lock bit of the CONSTAT register is set to "1", then the "wiper position" of the DCPs cannot be changed - i.e. DCP write operations cannot be conducted: DWLK DCP Write Operation Permissible 0 YES (Default) 1 NO WEL: Write Enable Latch (Volatile) The factory default setting for this bit is DWLK= 0. The WEL bit controls the Write Enable status of the entire X9522 device. This bit must first be enabled before ANY write operation (to DCPs, or the CONSTAT register). If the WEL bit is not first enabled, then ANY proceeding (volatile or nonvolatile) write operation to DCPs, or the CONSTAT register, is aborted and no ACKNOWLEDGE is issued after a Data Byte. IMPORTANT NOTE: If the Write Protect (WP) pin of the X9522 is active (HIGH), then nonvolatile write operations to the DCPs are inhibited, irrespective of the DCP Write Lock bit setting (See "WP: Write Protection Pin"). The WEL bit is a volatile latch that powers up in the disabled, LOW (0) state. The WEL bit is enabled / set by writing 00000010 to the CONSTAT register. Once enabled, the WEL bit remains set to "1" until either it is reset to "0" (by writing 00000000 to the CONSTAT register) or until the X9522 powers down, and then up again. Writes to the WEL bit do not cause an internal high voltage write cycle. Therefore, the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence (See Figure 12). V2OS, V3OS: Voltage Monitor Status Bits (Volatile) Bits V2OS and V3OS of the CONSTAT register are latched, volatile flag bits which indicate the status of the Voltage Monitor reset output pins V2RO and V3RO. At power up the VxOS (x=2,3) bits default to the value "0". These bits can be set to a "1" by writing the appropriate value to the CONSTAT register. To provide consistency between the VxRO and VxOS however, the status of the VxOS bits can only be set to a "1" when the corresponding VxRO output is HIGH. Once the VxOS bits have been set to "1", they will be reset to "0" if: --The device is powered down, then back up, RWEL: Register Write Enable Latch (Volatile) --The corresponding VxRO output becomes LOW. The RWEL bit controls the (CONSTAT) Register Write Enable status of the X9522. Therefore, in order to write to any of the bits of the CONSTAT Register (except WEL), the RWEL bit must first be set to "1". The RWEL bit is a volatile bit that powers up in the disabled, LOW ("0") state. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 10 of 30 X9522 - Preliminary Information SCL SDA S T A R T 1 0 1 0 0 1 0 R/W A C K 1 1 1 1 1 1 1 1 A C K ADDRESS BYTE SLAVE ADDRESS BYTE CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CONSTAT REGISTER DATA IN A C K S T O P Figure 12. CONSTAT Register Write Command Sequence CONSTAT Register Write Operation The CONSTAT register is accessed using the Slave Address set to 1010010 (Refer to Figure 4.). Following the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh. Only one data byte is allowed to be written for each CONSTAT register Write operation. The user must issue a STOP, after sending this byte to the register, to initiate the nonvolatile cycle that stores the DWLK bit. The X9522 will not ACKNOWLEDGE any data bytes written after the first byte is entered (Refer to Figure 12.). When writing to the CONSTAT register, the bits CS7, CS4 and CS0 must all be set to "0". Writing any other bit sequence to bits CS7, CS4 and CS0 of the CONSTAT register is reserved. Prior to writing to the CONSTAT register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps --Write a 02H to the CONSTAT Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP). Signals from the Master SDA Bus Signals from the Slave S t a r t --Write a 06H to the CONSTAT Register to set the Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP). --Write a one byte value to the CONSTAT Register that has all the bits set to the desired state. The CONSTAT register can be represented as 0xy0t010 in binary, where xy are the Voltage Monitor Output Status (V2OS and V3OS) bits, and t is the DCP Write Lock (DWLK) bit. This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (0xy0 t110) then the RWEL bit is set, but the DWLK bit will remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and the X9522 does not return an ACKNOWLEDGE. For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset the nonvolatile (DWLK) bit in the CONSTAT Register to "0". READ Operation WRITE Operation Slave Address S t Slave a r Address t Address Byte S t o p CS7 ... CS0 10 1 0 0 1 01 10 1 0 0 1 0 0 A C K A C K A C K Data "Dummy" Write Figure 13. CONSTAT Register Read Command Sequence REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 11 of 30 X9522 - Preliminary Information It should be noted that a write to nonvolatile bit (DWLK) of CONSTAT register will be ignored if the Write Protect pin of the X9522 is active (HIGH) (See "WP: Write Protection Pin"). CONSTAT Register Read Operation The contents of the CONSTAT Register can be read at any time by performing a random read (See Figure 13). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each register read operation. The X9522 resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol. After setting the WEL and / or the RWEL bit(s) to a "1", a CONSTAT register read operation may occur, without interrupting a proceeding CONSTAT register write operation. When reading the contents of the CONSTAT register, the bits CS7, CS4 and CS0 will always return "0". DATA PROTECTION There are a number of levels of data protection features designed into the X9522. Any write to the device first requires setting of the WEL bit in the CONSTAT register. A write to the CONSTAT register itself, further requires the setting of the RWEL bit. The DCP Write Lock of the device enables the user to inhibit writes to all DCPs. One further level of data protection in the X9522, is incorporated in the form of the Write Protection pin. WP: Write Protection Pin When the Write Protection (WP) pin is active (HIGH), it disables nonvolatile write operations to the X9522. The table below (X9522 Write Permission Status) summarizes the effect of the WP pin (and DCP Write Lock), on the write permission status of the device. VTRIPx Vx 0V VxRO 0V Vcc / V1 VTRIP 0 Volts (x = 2,3) Figure 14. Voltage Monitor Response Additional Data Protection Features In addition to the preceding features, the X9522 also incorporates the following data protection functionality: --The proper clock count and data bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle. VOLTAGE MONITORING FUNCTIONS V2 monitoring The X9522 asserts the V2RO output HIGH if the voltage V2 exceeds the corresponding VTRIP2 threshold (See Figure 14). The bit V2OS in the CONSTAT register is then set to a "0" (assuming that it has been set to "1" after system initilization). The V2RO output may remain active HIGH with Vcc down to 1V. X9522 Write Permission Status Write to CONSTAT Register Permitted DWLK (DCP Write Lock bit status) WP (Write Protect pin status) 1 1 NO NO YES NO 0 1 YES NO YES NO 1 0 NO NO YES YES 0 0 YES YES YES YES REV 1.1.6 9/14/01 DCP Volatile Write Permitted DCP Nonvolatile Write Permitted www.xicor.com Volatile Bits Nonvolatile Bits Characteristics subject to change without notice. 12 of 30 X9522 - Preliminary Information VTRIPx V2, V3 VP WP 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCL 00h SDA A0h S T A R T 09h sets VTRIP1 0Dh sets VTRIP2 Data Byte All others Reserved. Figure 15. Setting VTRIPx to a higher level (x=1,2). V3 monitoring The X9522 asserts the V3RO output HIGH if the voltage V3 exceeds the corresponding VTRIP3 threshold (See Figure 14). The bit V3OS in the CONSTAT register is then set to a "0" (assuming that it has been set to "1" after system initilization). The V3RO output may remain active HIGH with Vcc down to 1V. VTRIPX THRESHOLDS (X=2,3) The X9522 is shipped with pre-programmed threshold (VTRIPx) voltages. In applications where the required thresholds are different from the default values, or if a higher precision / tolerance is required, the X9522 trip points may be adjusted by the user, using the steps detailed below. Setting a VTRIPx Voltage (x=2,3) There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to "reset" the VTRIPx voltage before setting the new value. VP WP 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCL 00h SDA A0h S T A R T 0Bh Resets VTRIP2 0Fh Resets VTRIP3 Data Byte Figure 16. Resetting the VTRIPx Level (x=2,3) REV 1.1.6 9/14/01 www.xicor.com All others Reserved. Characteristics subject to change without notice. 13 of 30 X9522 - Preliminary Information Setting a Higher VTRIPx Voltage (x=2,3) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin (V2 or V3). Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 09h for VTRIP3, and 0Dh for VTRIP3, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 16). The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence. Setting a Lower VTRIPx Voltage (x=2,3) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be "reset" according to the procedure described below. Once VTRIPx has been "reset", then VTRIPx can be set to the desired voltage using the procedure described in "Setting a Higher VTRIPx Voltage". Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 16).The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence. After being reset, the value of VTRIPx becomes a nominal value of 1.7V. VTRIPx Accuracy (x=2,3) The accuracy with which the VTRIPx thresholds are set, can be controlled using the iterative process shown in Figure 17. If the desired threshold is less that the present threshold voltage, then it must first be "reset" (See "Resetting the VTRIPx Voltage"). The desired threshold voltage is then applied to the appropriate input pin (V2 or V3) and the procedure described in Section "Setting a Higher VTRIPx Voltage" must be followed. REV 1.1.6 9/14/01 Once the desired VTRIPx threshold has been set, the error between the desired and (new) actual set threshold can be determined. This is achieved by applying Vcc / V1 to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the voltage monitor circuit whose VTRIPx was programmed. For example, if VTRIP2 was set to a desired level of 3.0 V, then a test voltage of 3.4 V may be applied to the voltage monitor input pin V2. In all cases, care should be taken not to exceed the maximum input voltage limits. After applying the test voltage to the voltage monitor input pin, the test voltage can be decreased (either in discrete steps, or continuously) until the output of the voltage monitor circuit changes state. At this point, the error between the actual / measured, and desired threshold levels is calculated. For example, the desired threshold for VTRIP2 is set to 3.0 V, and a test voltage of 3.4 V was applied to the input pin V2 (after applying power to Vcc / V1). The input voltage is decreased, and found to trip the associated output level of pin V2RO from a LOW to a HIGH, when V2 reaches 3.09 V. From this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09 V. If the error between the desired and measured VTRIPx is less than the maximum desired error, then the programming process may be terminated. If however, the error is greater than the maximum desired error, then another iteration of the VTRIPx programming sequence can be performed (using the calculated error) in order to further increase the accuracy of the threshold voltage. If the calculated error is greater than zero, then the VTRIPx must first be "reset", and then programmed to the a value equal to the previously set VTRIPx minus the calculated error. If it is the case that the error is less than zero, then the VTRIPx must be programmed to a value equal to the previously set VTRIPx plus the absolute value of the calculated error. Continuing the previous example, we see that the calculated error was 0.09V. Since this is greater than zero, we must first "reset" the VTRIP2 threshold, then apply a voltage equal to the last previously programmed voltage, minus the last previously calculated error. Therefore, we must apply VTRIP1 = 2.91 V to pin V2 and execute the programming sequence (See "Setting a Higher VTRIPx Voltage (x=2,3)"). Using this process, the desired accuracy for a particular VTRIPx threshold may be attained using a successive number of iterations. www.xicor.com Characteristics subject to change without notice. 14 of 30 X9522 - Preliminary Information Note: X = 1,2,3. VTRIPx Programming NO Let: MDE = Maximum Desired Error MDE+ Desired VTRIPx < present value? Desired Value YES Acceptable Error Range MDE- Execute VTRIPx Reset Sequence Error = Actual - Desired Set Vx = desired VTRIPx Execute Set Higher VTRIPx Sequence New Vx applied = Old Vx applied + | Error | New Vx applied = Old Vx applied - | Error | Execute Reset VTRIPx Sequence Apply Vcc & Voltage > Desired VTRIPx to Vx Decrease Vx NO Output switches? YES Error < MDE- Actual VTRIPx - Desired VTRIPx Error >MDE+ = Error | Error | < | MDE | DONE Figure 17. VTRIPx Setting / Reset Sequence (x=1,2,3) REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 15 of 30 X9522 - Preliminary Information ABSOLUTE MAXIMUM RATINGS Parameter Temperature under Bias Storage Temperature Voltage on WP pin (With respect to Vss) Voltage on other pins (With respect to Vss) | Voltage on RHx- Voltage on RLx | (x=0,1,2. Referenced to Vss) D.C. Output Current (SDA,V2RO,V3RO) Lead Temperature (Soldering, 10 seconds) Supply Voltage Limits (Applied Vcc / V1 voltage, referenced to Vss) Min. Max. Units -65 -65 -1.0 -1.0 2.7 +135 +150 +15 +7 Vcc / V1 5 300 5.5 C C V V V mA C V Min. Max. Units 0 70 -40 +85 C C 0 RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Figure 18. Equivalent A.C. Circuit Vcc / V1 = 5V 2300 SDA V2RO V3RO 100pF Figure 19. DCP SPICE Macromodel RTOTAL RHx CH CL RW RLx 10pF CW 10pF 25pF (x=0,1,2) RWx REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 16 of 30 X9522 - Preliminary Information TIMING DIAGRAMS Figure 20. Bus Timing tF SCL tHIGH tLOW tR tSU:DAT tSU:STA SDA IN tHD:DAT tHD:STA tSU:STO tA tDH tBUF SDA OUT Figure 21. WP Pin Timing START SCL Clk 1 Clk 9 SDA IN WP tSU:WP tHD:WP Figure 22. Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition REV 1.1.6 9/14/01 www.xicor.com Start Condition Characteristics subject to change without notice. 17 of 30 X9522 - Preliminary Information Figure 23. V2, V3 Timing Diagram t tFx Rx Vx V TRIPx tRPDx tRPDx tRPDx 0 Volts tRPDx VxRO 0 Volts Vcc / V1 V TRIP V RVALID 0 Volts Note : x = 2,3. Figure 24. VTRIPX Programming Timing Diagram (x=2,3) V2, V3 VTRIPx tTSU tTHD VP WP tVPS tVPO SCL twc SDA 00h tVPH NOTE : Vcc / V1 must be greater than V2, V3 when programming. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 18 of 30 X9522 - Preliminary Information Figure 25. DCP "Wiper Position" Timing Rwx (x=0,1,2) Rwx(n+1) Rwx(n) Rwx(n-1) twr Time n = tap position SCL SDA S 1 T A R T 0 1 0 1 1 1 SLAVE ADDRESS BYTE REV 1.1.6 9/14/01 0 A WT C K 0 0 0 0 0 INSTRUCTION BYTE www.xicor.com P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE Characteristics subject to change without notice. A C K S T O P 19 of 30 X9522 - Preliminary Information D.C. OPERATING CHARACTERISTICS Symbol Parameter Min Typ Max Unit Test Conditions / Notes 0.4 1.5 mA fSCL = 400KHz A VSDA = Vcc / V1 WP = Vss or Open/Floating VSCL= Vcc / V1 (when no bus activity else fSCL = 400kHz) 10 A VIN (4) = GND to Vcc / V1. 1 A 10 A 4.70 V Current into Vcc / V1 Pin (X9522: Active) Read memory array (3) Write nonvolatile memory ICC1(1) Current into Vcc / V1 Pin (X9522:Standby) With 2-Wire bus activity (3) No 2-Wire bus activity ICC2(2) 30.0 30.0 0.1 Input Leakage Current (SCL, SDA) ILI Input Leakage Current (WP) VOUT (5) = GND to Vcc / V1. X9522 is in Standby(2) ILO Output Leakage Current (SDA, V2RO, VTRIPxPR VTRIPx Programming Range (x=1,2) 1.8 VTRIP1 (6) Pre - programmed VTRIP1 threshold 1.75 2.95 1.8 3.0 1.85 3.05 V Factory shipped default option A Factory shipped default option B VTRIP2 (6) Pre - programmed VTRIP2 threshold 1.75 2.95 1.8 3.0 1.85 3.05 V Factory shipped default option A Factory shipped default option B IVx V2 Input leakage current V3 Input leakage current 1 1 A VIL (7) Input LOW Voltage (SCL, SDA, WP) -0.5 0.8 V VIH (7) Input HIGH Voltage (SCL,SDA, WP) 2.0 Vcc / V1 +0.5 V VOLx V2RO, V3RO, SDA Output Low Voltage 0.4 V Notes: 1. Notes: 2. Notes: Notes: Notes: Notes: Notes: 0.1 V3RO) 3. 4. 5. 6. 7. VSDA=VSCL=Vcc / V1 Others=GND or Vcc / V1 ISINK = 2.0mA The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t WC after a STOP that initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte. Current through external pull up resistor not included. VIN = Voltage applied to input pin. VOUT = Voltage applied to output pin. See "ORDERING INFORMATION" on page 30. VIL Min. and VIH Max. are for reference only and are not tested REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 20 of 30 X9522 - Preliminary Information A.C. CHARACTERISTICS (See Figure 20, Figure 21, Figure 22) 400kHz Symbol Parameter Min Max Units 400 KHz fSCL SCL Clock Frequency 0 tIN (5) Pulse width Suppression Time at inputs 50 tAA SCL LOW to SDA Data Out Valid 0.1 tBUF Time the bus free before start of new transmission 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR (5) SDA and SCL Rise Time 20 +.1Cb (2) 300 ns tF (5) SDA and SCL Fall Time 20 +.1Cb (2) 300 ns tSU:WP WP Setup Time tHD:WP WP Hold Time Cb Capacitive load for each bus line ns s 0.9 0.6 s 0 s 400 pF A.C. TEST CONDITIONS Input Pulse Levels 0.1Vcc to 0.9Vcc Input Rise and Fall Times 10ns Input and Output Timing Levels 0.5Vcc Output Load See Figure 18 NONVOLATILE WRITE CYCLE TIMING Symbol tWC(4) Parameter Min. Typ.(1) Max. Units 5 10 ms Nonvolatile Write Cycle Time CAPACITANCE (TA = 25C, F = 1.0 MHZ, VCC / V1 = 5V) Symbol Parameter Max Units Test Conditions COUT (5) Output Capacitance (SDA, V2RO, V3RO) 8 pF VOUT = 0V CIN (5) Input Capacitance (SCL, WP) 6 pF VIN = 0V Notes: Notes: Notes: Notes: 1. 2. 3. 4. Notes: 5. Typical values are for TA = 25C and Vcc / V1 = 5.0V Cb = total capacitance of one bus line in pF. Over recommended operating conditions, unless otherwise specified tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. This parameter is not 100% tested. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 21 of 30 X9522 - Preliminary Information POTENTIOMETER CHARACTERISTICS Limits Symbol Parameter Min. Typ. Max. Units Test Conditions/Notes RTOL End to End Resistance Tolerance -20 +20 % VRHx RH Terminal Voltage (x=0,1,2) Vss Vcc / V1 V VRLx RL Terminal Voltage (x=0,1,2) Vss Vcc / V1 V 10 mW RTOTAL = 10 K (DCP0, DCP1) 5 mW RTOTAL = 100 K (DCP2) 200 400 IW = 1mA, Vcc / V1 = 5 V, VRHx = Vcc / V1, VRLx = Vss (x=0,1,2). 300 700 IW = 1mA, Vcc / V1 = 3.3 V, VRHx = Vcc / V1, VRLx = Vss (x=0,1,2), 400 1000 IW = 1mA, Vcc / V1 = 2.7 V, VRHx = Vcc / V1, VRLx = Vss (x=0,1,2) 4.4 mA PR Power Rating (1) RW DCP Wiper Resistance IW Wiper Current Noise RTOTAL = 100 k (DCP2) +1 MI(4) Rw(n)(actual) - Rw(n)(expected) Relative Linearity (3) -0.2 +0.2 MI(4) Rw(n+1) - [Rw(n)+MI] Potentiometer Capacitances twr Wiper Response time VTRIP Vcc / V1 power up DCP recall threshold tPU Vcc / V1 power up DCP recall delay time 3. 4. 5. 6. mV / sqt(Hz) -1 CH/CL/ CW Notes: Notes: Notes: Notes: RTOTAL = 10 k (DCP0, DCP1) Absolute Linearity (2) RTOTAL Temperature Coefficient Notes: 1. Notes: 2. mV / sqt(Hz) 300 ppm/C RTOTAL = 10 k (DCP0, DCP1) 300 ppm/C RTOTAL = 100 k (DCP2) 10/10/ 25 pF 200 s See Figure 19. See Figure 25. V 25 50 75 ms Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x=0,1,2). Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R wx(n)(actual) - Rwx(n)(expected)) = 1 Ml Maximum (x=0,1,2). Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = 0.2 Ml (x=0,1,2) 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1). Typical values are for TA = 25C and nominal supply voltage. This parameter is periodically sampled and not 100% tested. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 22 of 30 X9522 - Preliminary Information VTRIPX (X=1,2) PROGRAMMING PARAMETERS (See Figure 24) Parameter Description Min Typ Max Units tVPS VTRIPx Program Enable Voltage Setup time 10 s tVPH VTRIPx Program Enable Voltage Hold time 10 s tTSU VTRIPx Setup time 10 s tTHD VTRIPx Hold (stable) time 10 s tVPO VTRIPx Program Enable Voltage Off time (Between successive adjustments) 1 ms twc VTRIPx Write Cycle time VP Programming Voltage 5 10 ms 10 15 V +0.2 V Vta1(1) Initial VTRIPx Program Voltage accuracy (Vx applied - VTRIPx) (Programmed at 25oC.) -0.1 Vta2(1) Subsequent VTRIPx Program Voltage accuracy [(Vx applied - Vta1) - VTRIPx. Programmed at 25oC.) -25 +10 +25 mV VTRIP Program variation after programming (-40 - 85oC). (Programmed at 25oC.) -25 +10 +25 mV Vtv Notes: 1. This parameter is not 100% tested. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 23 of 30 X9522 - Preliminary Information V2RO, V3RO OUTPUT TIMING. (See Figure 23) Symbol Description Condition Min. Typ. Max. Units 20 s tRPDx V2, V3 to V2RO, V3RO propagation delay (respectively) tFx V2, V3 Fall Time 20 mV/s tRx V2, V3 Rise Time 20 mV/s VRVALID Vcc / V1 for V2RO, V3RO Valid (3). 1 V Notes: 1. Notes: 2. Notes: 3. See Figure 23 for timing diagram. See Figure 18 for equivalent load. This parameter describes the lowest possible Vcc / V1 level for which the outputs V2RO, and V3RO will be correct with respect to their inputs ( V2, V3). REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 24 of 30 X9522 - Preliminary Information APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Data Byte Tap Position Decimal Binary 0 0 0000 0000 1 1 0000 0001 . . . . . . 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 . . . . . . 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 . . . . . . 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 . . . . . . 98 97 0110 0001 99 96 0110 0000 REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 25 of 30 X9522 - Preliminary Information APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1) unsigned { int int int int DCP1_TAP_Position(int tap_pos) block; i; offset; wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } } } return((unsigned)01100000); } REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 26 of 30 X9522 - Preliminary Information APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2) unsigned DCP100_TAP_Position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); else if (tap_pos >99) return ((unsigned) 96); /* set to min val */ /* set to max val */ /* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); } REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 27 of 30 X9522 - Preliminary Information 20 Ball BGA (X9522) a a l j m 1 2 3 4 4 3 2 A 1 A B B b b k C C D D f E E Top View (Bump Side Down) Bottom View (Bump Side Up) Note: Drawing not to scale d = Die Orientation mark c e Ball Matrix 4 3 2 1 A RL2 RW2 V1/VCC V2RO B V3 RH2 NC V2 C WP V3RO RLO RWO D SCL NC RH0 RH1 E SDA RL1 RW1 VSS Side View (Bump Side Down) Millimeters Inches Symbol Min Nom Max Min Nom Max Package Body Dimension X a 2.524 2.554 2.584 0.09938 0.10056 0.10174 Package Body Dimension Y b 3.794 3.824 3.854 0.14938 0.15056 0.15174 Package Height c 0.654 0.682 0.710 0.02575 0.02685 0.02795 Body Thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850 Ball Height e 0.210 0.225 0.240 0.00827 0.00886 0.00945 Ball Diameter f 0.316 0.326 0.336 0.01244 0.01283 0.01323 Ball Pitch - X Axis j 0.5 0.01969 Ball Pitch - Y Axis k 0.5 0.01969 Ball to Edge Spacing - Distance Along X l 0.497 0.527 0.557 0.01957 0.02075 0.02193 Ball to Edge Spacing - Distance Along Y m 0.882 0.912 0.942 0.03473 0.03591 0.03709 REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 28 of 30 X9522 - Preliminary Information 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .252 (6.4) .260 (6.6) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) (4.16) (7.72) .010 (.25) Gage Plane 0 - 8 Seating Plane .019 (.50) .029 (.75) (1.78) (0.42) Detail A (20X) (0.65) ALL MEASUREMENTS ARE TYPICAL .031 (.80) .041 (1.05) See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 29 of 30 X9522 - Preliminary Information ORDERING INFORMATION X9522 P T - y Preset (Factory Shipped) VTRIPx Threshold Levels (x=2,3) A = Optimized for 3.3 V system monitoring B = Optimized for 5 V system monitoring Device Temperature Range I = Industrial -40C to +85C Package V20 = 20-Lead TSSOP B20 = 20-Lead XBGA XBGA PART MARK CONVENTION 20 Lead XBGA Top Mark X9522B20I-A XACM X9522B20I-B XACN For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS" LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.6 9/14/01 www.xicor.com Characteristics subject to change without notice. 30 of 30