ANALOG Quad, Voltage Output, 12-Bit DEVICES BiCMOS DACs with Readback DAC-8412/DAC-8413 REV. B 1.1 Scope. This specification covers the detail requirements for a quad, voltage output, 12-bit BKCMOS DAC with readback. It is highly recommended that this data sheet be used as a baseline for new military or aero- space spec control drawings. 1.2 Part Number. The complete part numbers per Table 1 of this specification are as follows: Device Part Number Package -1 DAC-8412AT/883 T 2 DAC-8412BT/883 T -2 DAC-8412BTC/883 TC 3 DAC-8413AT/883 T -4 DAC-8413BT/883 T -4 DAC-8413BTC/883 TC 1.2.3 Case Outline. Letter Case Outline (Lead Finish Per MIL-M-38510) T 28-Lead Ceramic Dual-in-Line Package (Cerdip) TC 28-Contact Hermetic Leadless Chip Carrier (LCC) 1.3 Absolute Maximum Ratings.* (T, = +25C unless otherwise noted) Veg tO Vpp cee ccc eee eee ee eee eee eee eee e eee eens 0.3 V, +33.0 V Veg tO Viogig cee ee eee tee ee nee eet e tent tenes 0.3 V, +23.5 V Vpp tO DGND 2... cc een nee nee beeen een nenteenee +16.5V Vsg 0 DGND 201 ee eee ence nen e eee nee e etn enneeee -16.5V Viuogic tO DGND 2... eee eee ne eee -0.3V,4+7V Vsg tO VREFL ce ee ce ee eee ee ene ee eee tenet n eens -0.3.V, +Vpp 2.0 V VREFH to Vop CS +2.0 Vv, +33.0 Vv VREFH to VREFL Ce +2.0 Vv; Vpp - Vss Current into Any Pin 0... cece ce tc ete ee tne eee t eee eee enn enne +15 mA Digital Input Voltage to DGND ........ 2... ec eee tenes ~0.3 V, Viogic + 0.3 V Digital Output Voltage to DGND .......... 00. ec ee eee eeee -0.3 V, +7.0 V Operating Temperature Range (AT, BT, BTC) ........ 0.0... ccc eee eee eee 55C to +125C Junction Temperature (Ty) 2... cee ee eect neta ees +150C Storage Temperature 2.0... ce eee ete erent ete eees 65C to + 150C Power Dissipation 0.0... ccc ee eee eee eee ee tet e ee eee teenies 1000 mW Lead Temperature (Soldering 60 sec)... 0... ccc cece cee eee ene e bene +300C *CAUTION: a. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation at above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. b. Analog and digital inputs and out- puts are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. c. Remove power before inserting or removing units from their sockets. DIGITAL-TO-ANALOG CONVERTERS 8-229 DIGITAL-TO-ANALOG CONVERTERS aDAC-8412/DAC-8413 SPECIFICATIONS Table 1. Device Limits Group A Test Symbol Types | Min Max Subgroups|Conditions' Units Integral Linearity INL -1,3 +3/4 1 Ta = +25C LSB 2,3 Ta = S5C, +125C -2,4 +15 1 T, = +25C LSB 2,3 Ta = 55C, +125C Differential Linearity DNL All +1 1 Ty = +25C LSB 2,3 Ty = 55C, +125C Min-Scale Error Vise All +2 1 R, = 2kN; Ty = +25C LSB 2,3 Ry = 2k; Ty = -55C, +125C Full-Scale Error VesE All +2 1 Ry, = 2 kO; T, = +25C LSB 2,3 Ry = 2k; Ty = 55C, +125C Linearity Matching All +1 1 Ta = +25C LSB Min-Scale Offset Matching All +] 1 Ty = +25C LSB Full-Scale Offset Matching All +2 1 Ta = +25C LSB Reference Input Current TREFH All 2.75 +2.75 1, 2, 3 Code 555;, & 000.3 T, = +25C, 55C, +125C|mA TREFL 0 +2.75 1, 2, 3 Code 555}, & 000,43 Ty = +25C, 55C, +125C Output Voltage Swing Vout (min) |All 10.0098] 9.9902 |1, 2, 3 Ta = 425C, ~55C, +125C; Ry = 2 kO Vv Vout max) +9,9853 |+10.0048]1, 2, 3 Ta = +25C, 55C, +125C; Ry = 2 kN Settling Time ts All 15 9 10 V Step to 0.01%; T, = +25C ps Logic Input High Voltage Ving All 2.4 1 Ta = +25C Vv 2,3 Ta = 55C, +125C Logic Input Low Voltage Vin All 0.8 1 Ta = +25C Vv 2,3 Ta = 55C, +125C Logic Output High Voltage [Voy All 2.4 1 Toy = +0.4 mA; T, = +25C v 2,3 low = +0.4 mA; T, = 55C, +125C Logic Input Low Voltage VoL All 0.4 1 Io, = 1.6 mA; Ty = +25C v 2,3 Io, = 1.6 mA; T, = 55C, +125C Logic Input Current In All 10 1 Ty = +25C BA 2,3 Ty = 55C, +125C Slew Rate SR All [2 7 Ta = +25C Vius LOGIC TIMING CHARACTERISTICS? WRITE Chip Select Write Pulse Width?| tyes All 90 9 Ty, = +25C ns 10, 11 Ta = 55C, +125C Write Setup tws All 0 9 twes = 90 ns; Ty = +25C ns 10, 11 twos = 90 ns, T, = 55C, +125C Write Hold? tw Al [0 9 twcs = 90 ns; T, = +25C ns 10, 11 twes = 90 ns; Ty = 55C, +125C Address Setup tas All [0 9 T, = +25C ns 10, 11 Ta = SS5C, +125C Address Hold? tan All [0 9 Ta = +25C ns 10, 11 Ta = 55C, +125C Load Setup? tis All 70 9 Ta = +25C ns 10, 11 Ta = 55C, +125C 8-230 DIGITAL-TO-ANALOG CONVERTERS REV. BDAC-8412/DAC-8413 Device Limits Group A Test Symbol Types |Min Max Subgroups|Conditions' Units WRITE (Continued) Load Hold? tty All 30 9 Ta, = +25C ns 10, 11 Ta = 55C, +125C Write Data Setup? twos All 20 9 twos = 90 ns; Ty = +25C ns 10,11 |twcs = 90 ns; T, = 55C, +125C Write Data Hold? two All [0 9 twos = 90 ns; T, = +25C ns 10, 11 twes = 90 ns; T, = 55C, +125C Load Pulse Width? ttwp All 170 9 Ta = +25C ns 10, 11 Ta = ~55C, +125C Reset Pulse Width? treser All 200 9 Ta = +25C ns 10, 11 Ta = 55C, +125C READ Chip Select Read Pulse Width? | tacs All 130 9 Ta = +25C ns 10, 11 Ta = 55C, +125C Read Data Hold* troy Al [0 9 trcs = 130 ns; T, = +25C ns 10, 11 tpcs = 130 ns; Ty = 55C, + 125C Read Data Setup? taps All 10 9 trcs = 130 ns; T, = +25C ns 10, 11 trcs = 130 ns; Ty = 55C, +125C Data to Hi Z? tpz All 200 9 Ty = +25C ns 10,11 [T, = 55C, +125C Chip Select to Data tesp All 200 9 Ty = +25C ns 10,11 |T, = 55C, +125C SUPPLY CHARACTERISTICS Power Supply Sensitivity PSS All 150 1 14.25 VEVpp=15.75 V3 Ta = +25C ppm/v 2,3 14.25 VEVpp=15.75 V3 Ta, = 55C, +125 | Power Supply Current Ipp All 13 1 Veera = +10 V; Ta = +25C mA 2,3 Varru = 110 V; Ta = 55G, +125 Negative Supply Current Iss. All -10 1 Ty, = +25C mA 2,3 T, = 55C, +125 Logic Supply Current TLoaic All 100 1 Ta, = +25C pA Power Dissipation* Poss All 345 1 Ta = +25C mW 2,3 Ta = 55C, +125 NOTES All supplies can be varied +5% and operation is guaranteed. Voy = +15 V, Vgg = ~15 Vy. Viogic = +5 V. Vasey = +10 V, Vrer, = -10V. ?Guaranteed but not 100% tested. >All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. *Power dissipation (Pp;s5) guaranteed by supply current testing. REV. B DIGITAL-TO-ANALOG CONVERTERS 8-231 DIGITAL-TO-ANALOG CONVERTERS aDAC-8412/DAC-8413 1.4 Recommended Operating Conditions. Supply Voltage Range .... 20.0... 0.0 cee eee ee eee eee nent enee +15V Logic Supply Voltage 2.0.6... ee eee tenet teens +5V Positive Reference Voltage (Vpppy) oe eee nee ten aae +2.5V to +10V Negative Reference Voltage (Vappy) .-.- ee ee eens -10Vt00V Ground Potential (GND) 1.0.0.0... 0.0 ccc ee ee eee tenet eee OV Ambient Operating Temperature Range (Ty)... 0.6. ee cee ~55C to +125C 1.5 Thermal Characteristics.! Thermal Resistance, Cerdip (T) Package: Junction-to-Case (6;) = 7C/W max Junction-to-Ambient (6,4) = 50C/W max Thermal Resistance, LCC (TC) Package: Junction-to-Case (@;-) = 28C/W max Junction-to-Ambient (6;,) = 70C/W max NOTE 1@yq is specified for device in socket for cerdip and mounted to PC board for LCC. Table 2. Electrical Test Requirements MIL-STD-883 Test Requirements Group A Subgroups (See Table 1) Interim Electrical Parameters (Pre-Burn-In) | 1 Final Electrical Test Parameters 1,* 2,3 Group A Test 1, 2, 3, 7, 9, 10, 11 *PDA applies to Subgroup 1 only. No other subgroups are included in PDA. 3.2.1 Functional Block Diagram and Terminal Assignments. Voie Yop VaerH > DATA VO 72 pour DGND CONTROL| Logic 8-232 DIGITAL-TO-ANALOG CONVERTERS REV. BDAC-8412/DAC-8413 28-Position LCC 28-Pin Ceramic DIP (TC Suffix) (T Suffix) fee ee . 3 3 8 #3 3 Vacew 1] 4 [28] Vance 28] Yours [2] [27] Youre 25] V55 Voura e [26] Youre 24] Vioaic Vss ig [25] Yop DAC-8412/ [23] cs peno [5] 124] Voce DAC-8413 [22| ao Reset [e| DAC-8412/ = [23] as (Not to Scale) [21] Al [pac Gr] DAC-8413 22] a0 _ TOP VIEW Aw pBo(LsB) [s| _(Not to Scale) Figs D611 (MSB) bet in Bo Riv DB2 [10] Al DB11 (MSB) bes fa] [18] DB10 OB4 [ra] [a7] DBS DBS [3] [16] DB8 pes [14 115] DB7 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (92). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (C). +15V TOkQ g 10kQ 10kQ2 5k EW TTT Tr rt tt RESET DBO------~------- rrr nnn nnn DB11 V, ogic Yop +10V ET Vacen ao VrerL DAC-8412/8413 $y iee TOLoGNo RW Ss Ao At = + + ga Sse -15V + + REV. B DIGITAL-TO-ANALOG CONVERTERS 8-233 -TO-ANALOG CONVERTERS 5 DIGITALDAC-8412/DAC-8413 4.3 AC Timing Diagram 8 KA tres ! - > Lat- tans RW DATA Out DATA VALID tcso Data Output (Rea d Timing) batt wos DATA IN treser RESET Data Write (input and Output Registers) Timing pat twos Om cs ' twsl<e- aw | twa tas N- | ta AO/AI fis mt LDAC Table 3. Logic Table INPUT | INPUT Al | AO | R/W | CS | RS | LDAC | REG REG MODE DAC LjLyeu L IH UL WRITE | WRITE | WRITE A L j|HYL L JH IL WRITE | WRITE | WRITE B HjLIL LIH UL WRITE | WRITE | WRITE Cc H|HiL LIH IL WRITE | WRITE | WRITE D LyYLYAL L /H {H WRITE | HOLD WRITE INPUT | A Lj)H{L LIH IH WRITE | HOLD WRITE INPUT |B H|LUL Lj|H IH WRITE | HOLD WRITE INPUT | C H|H{L L {|H |H WRITE | HOLD | WRITEINPUT | D L{|LiH L j|}H{H READ | HOLD | READ INPUT A L {HH |H L j|H |H READ HOLD | READ INPUT B Hj|L j|H L iH |H READ |} HOLD | READ INPUT Cc H |H | L |H IH READ | HOLD READ INPUT D X |X |X H |H|{L HOLD | Update All Output Registers | All X |X |X H |H |H HOLD | HOLD | HOLD All KX {|X |X X ;L |X *All Registers Reset to Mid/Zero Scale All X | K |X H |d {|X *All Registers Latched to Mid/Zero Scale ; All *DAC-8412 resets to mid-scale, and DAC-8413 resets to zero scale. L is a logic Low; H is a logic High; X is dont care. 8-234 DIGITAL-TO-ANALOG CONVERTERS REV. B