SST31LF041-70-4E-WI - Silicon Storage Technology

S71107-06-EOL 6/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

ComboMemory is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Preliminary Specifications

FEATURES:

• Monolithic Flash + SRAM ComboMemory

– SST31LF041/041A: 512K x8 Flash + 128K x8 SRAM

• Single 3.0-3.6V Read and Write Operations

• Concurrent Operation

– Read from or Write to SRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 10 mA (typical) for Flash and

20 mA (typical) for SRAM Read

– Standby Current: 10 µA (typical)

• Flash Sector-Erase Capability

– Uniform 4 KByte sectors

• Latched Address and Data for Flash

• Fast Read Access Times:

– SST31LF041/041A Flash: 70 ns

SRAM: 70 ns

– SST31LF041A Flash: 300 ns

SRAM: 300 ns

• Flash Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Bank-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Bank Rewrite Time: 8 seconds (typical)

• Flash Automatic Erase and Program Timing

– Internal VPP Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Packages Available

– 32-lead TSOP (8mm x 14mm) SST31LF041A

– 40-lead TSOP (10mm x 14mm) SST31LF041

PRODUCT DESCRIPTION

The SST31LF041/041A devices are a 512K x8 CMOS

flash memory bank combined with a 128K x8 CMOS

SRAM memory bank manufactured with SST’s proprietary,

high performance SuperFlash technology. The

SST31LF041/041A devices write (SRAM or flash) with a

3.0-3.6V power supply. The monolithic SST31LF041/041A

devices conform to Software Data Protect (SDP) com-

mands for x8 EEPROMs.

Featuring high performance Byte-Program, the flash mem-

ory bank provides a maximum Byte-Program time of 20

µsec. The entire flash memory bank can be erased and

programmed byte-by-byte in typically 8 seconds, when

using interface features such as Toggle Bit or Data# Polling

to indicate the completion of Program operation. To protect

against inadvertent flash write, the SST31LF041/041A

devices have on-chip hardware and Software Data Protec-

tion schemes. Designed, manufactured, and tested for a

wide spectrum of applications, the SST31LF041/041A

devices are offered with a guaranteed endurance of 10,000

cycles. Data retention is rated at greater than 100 years.

The SST31LF041/041A operate as two independent mem-

ory banks with respective bank enable signals. The SRAM

and flash memory banks are superimposed in the same

memory address space. Both memory banks share com-

mon address lines, data lines, WE# and OE#. The memory

bank selection is done by memory bank enable signals.

The SRAM bank enable signal, BES# selects the SRAM

bank and the flash memory bank enable signal, BEF#

selects the flash memory bank. The WE# signal has to be

used with Software Data Protection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alteration.

The SST31LF041/041A provide the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Byte-Program concurrently. All flash

memory Erase and Program operations will automatically

latch the input address and data signals and complete the

operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the SRAM

bank can be accessed for Read or Write.

The SST31LF041/041A devices are suited for applications

that use both nonvolatile flash memory and volatile SRAM

memory to store code or data. For all system applications,

the SST31LF041/041A devices significantly improve per-

formance and reliability, while lowering power consumption,

when compared with multiple chip solutions. The

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

SST31LF041 / 041A4Mb Flash (x8) + 1Mb SRAM (x8) Monolithic ComboMemory

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

SST31LF041/041A inherently use less energy during

Erase and Program than alternative flash technologies.

When programming a flash device, the total energy con-

sumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter Erase time, the total energy consumed dur-

ing any Erase or Program operation is less than alternative

flash technologies. The monolithic ComboMemory elimi-

nates redundant functions when using two separate mem-

ories of similar architecture; therefore, reducing the total

power consumption.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

The SST31LF041/041A devices also improve flexibility by

using a single package and a common set of signals to

perform functions previously requiring two separate

devices. To meet high density, surface mount requirements,

the SST31LF041 device is offered in 40-lead TSOP pack-

age and the SST31LF041A device is offered in 32-lead

TSOP package. See Figures 1 and 2 for the pinouts.

Device Operation

The ComboMemory uses BES# and BEF# to control oper-

ation of either the SRAM or the flash memory bank. Bus

contention is eliminated as the monolithic device will not

recognize both bank enables as being simultaneously

active. If both bank enables are asserted (i.e., BEF# and

BES# are both low), the BEF# will dominate while the

BES# is ignored and the appropriate operation will be exe-

cuted in the flash memory bank. SST does not recommend

that both bank enables be simultaneously asserted. All

other address, data, and control lines are shared which

minimizes power consumption and area. The device goes

into standby when both bank enables are raised to VIHC.

See Table 3 for SRAM operation mode selection.

For SST31LF041A only: BES# and OE# share pin 32.

During SRAM operation, pin 32 will function as BES#. Dur-

ing flash operation, pin 32 will function as OE#. When pin 32

(OE#/BES#) is high, the data bus is in high impedance state.

SRAM Operation

With BES# low and BEF# high, the SST31LF041/041A

operate as a 128K x8 CMOS SRAM with fully static opera-

tion requiring no external clocks or timing strobes. The

SRAM is mapped into the first 128 KByte address space of

the device for 041/041A. Read and Write cycle times are

equal.

SRAM Read

The SRAM Read operation of the SST31LF041/041A are

controlled by OE# and BES#, both have to be low with

WE# high, for the system to obtain data from the outputs.

BES# is used for SRAM bank selection. When BES# and

BEF# are high, both memory banks are deselected. OE#

is the output control and is used to gate data from the out-

put pins. The data bus is in high impedance state when

OE# is high. See Figure 3 for the Read cycle timing dia-

gram.

SRAM Write

The SRAM Write operation of the SST31LF041/041A is

controlled by WE# and BES#; both have to be low for the

system to write to the SRAM. BES# is used for SRAM

bank selection. During the Byte-Write operation, the

addresses and data are referenced to the rising edge of

either BES# or WE#, whichever occurs first. The Write time

is measured from the last falling edge to the first rising edge

of BES# and WE#. OE# can be VIL or VIH, but no other

value, for SRAM Write operations. See Figure 4 for the

SRAM Write cycle timing diagram.

Flash Operation

With BEF# active, the SST31LF041/041A operate as a

512K x8 flash memory. The flash memory bank is read

using the common address lines, data lines, WE# and

OE#. Erase and Program operations are initiated with the

JEDEC standard SDP command sequences. Address and

data are latched during the SDP commands and internally

timed Erase and Program operations. See Table 3 for flash

operation mode selection.

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

Flash Read

The Read operation of the SST31LF041/041A devices are

controlled by BEF# and OE#; both have to be low, with

WE# high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# and BES# are high, both banks are deselected and

only standby power is consumed. OE# is the output control

and is used to gate data from the output pins. The data bus

is in high impedance state when OE# is high. See Figure 5

for the Read cycle timing diagram.

Flash Erase/Program Operation

SDP commands are used to initiate the flash memory bank

Program and Erase operations of the SST31LF041/041A.

SDP commands are loaded to the flash memory bank

using standard microprocessor write sequences. A com-

mand is loaded by asserting WE# low while keeping BEF#

low and OE# high. The address is latched on the falling

edge of WE# or BEF#, whichever occurs last. The data is

latched on the rising edge of WE# or BEF#, whichever

occurs first.

Flash Byte-Program Operation

The flash memory bank of the SST31LF041/041A devices

are programmed on a byte-by-byte basis. Before the Pro-

gram operations, the memory must be erased first. The

Program operation consists of three steps. The first step is

the three-byte load sequence for Software Data Protection.

The second step is to load byte address and byte data. Dur-

ing the Byte-Program operation, the addresses are latched

on the falling edge of either BEF# or WE#, whichever

occurs last. The data is latched on the rising edge of either

BEF# or WE#, whichever occurs first. The third step is the

internal Program operation which is initiated after the rising

edge of the fourth WE# or BEF#, whichever occurs first.

The Program operation, once initiated, will be completed,

within 20 µs. See Figures 6 and 7 for WE# and BEF# con-

trolled Program operation timing diagrams and Figure 17 for

flowcharts. During the Program operation, the only valid

Flash Read operations are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perform additional tasks. Any SDP commands loaded dur-

ing the internal Program operation will be ignored.

Flash Sector-Erase Operation

The Sector-Erase operation allows the system to erase

the flash memory bank on a sector-by-sector basis. The

sector architecture is based on uniform sector size of 4

KByte. The Sector-Erase operation is initiated by execut-

ing a six-byte command load sequence for Software

Data Protection with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The address

lines A18-A12 will be used to determine the sector

address. The sector address is latched on the falling

edge of the sixth WE# pulse, while the command (30H)

is latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE#

pulse. The End-of-Erase can be determined using either

Data# Polling or Toggle Bit methods. See Figure 10 for

timing waveforms. Any SDP commands loaded during

the Sector-Erase operation will be ignored.

Flash Bank-Erase Operation

The SST31LF041/041A flash memory bank provides a

Bank-Erase operation, which allows the user to erase the

entire flash memory bank array to the ‘1’s state. This is use-

ful when the entire bank must be quickly erased. The Bank-

Erase operation is initiated by executing a six-byte Software

Data Protection command sequence with Bank-Erase com-

mand (10H) with address 5555H in the last byte sequence.

The internal Erase operation begins with the rising edge of

the sixth WE# or BEF# pulse, whichever occurs first. During

the internal Erase operation, the only valid Flash Read oper-

ations are Toggle Bit and Data# Polling. See Table 4 for the

command sequence, Figure 11 for timing diagram, and Fig-

ure 20 for the flowchart. Any SDP commands loaded during

the Bank-Erase operation will be ignored.

Flash Write Operation Status Detection

The SST31LF041/041A flash memory bank provides two

software means to detect the completion of a flash memory

bank Write (Program or Erase) cycle, in order to optimize

the system Write cycle time. The software detection

includes two status bits: Data# Polling (DQ7) and Toggle Bit

(DQ6). The End-of-Write detection mode is enabled after

the rising edge of WE#, which initiates the internal Program

or Erase operation. The actual completion of the nonvola-

tile write is asynchronous with the system; therefore, either

a Data# Polling or Toggle Bit Read may be simultaneous

with the completion of the Write cycle. If this occurs, the

system may possibly get an erroneous result, i.e., valid

data may appear to conflict with either DQ7 or DQ6. In

order to prevent spurious rejection, if an erroneous result

occurs, the software routine should include a loop to read

the accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

Flash Data# Polling (DQ7)

When the SST31LF041/041A flash memory bank is in the

internal Program operation, any attempt to read DQ7 will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ7 will produce true data.

Note that even though DQ7 may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. During inter-

nal Erase operation, any attempt to read DQ7 will produce

a ‘0’. Once the internal Erase operation is completed, DQ7

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the fourth WE# (or BEF#) pulse for Program opera-

tion. For Sector or Bank-Erase, the Data# Polling is valid

after the rising edge of the sixth WE# (or BEF#) pulse. See

Figure 8 for Data# Polling timing diagram and Figure 18 for

a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The flash memory bank is then ready for the next

operation. The Toggle Bit is valid after the rising edge of the

fourth WE# (or BE#) pulse for Program operation. For Sec-

tor or Bank-Erase, the Toggle Bit is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 9 for

Toggle Bit timing diagram and Figure 18 for a flowchart.

Flash Memory Data Protection

The SST31LF041/041A flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Flash Software Data Protection (SDP)

The SST31LF041/041A provide the JEDEC approved

Software Data Protection scheme for all flash memory

bank data alteration operations, i.e., Program and Erase.

Any Program operation requires the inclusion of a series of

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST31LF041/041A devices are shipped with the Software

Data Protection permanently enabled. See Table 4 for the

specific software command codes. During SDP command

sequence, invalid SDP commands will abort the device to

the Read mode, within TRC.

Concurrent Read and Write Operations

The SST31LF041/041A provide the unique benefit of

being able to read from or write to SRAM, while simulta-

neously erasing or programming the flash. The device will

ignore all SDP commands when an Erase or Program

operation is in progress. This allows data alteration code to

be executed from SRAM, while altering the data in flash.

The following table lists all valid states. SST does not rec-

ommend that both bank enables, BEF# and BES#, be

simultaneously asserted.

Note that Product Identification commands use SDP;

therefore, these commands will also be ignored while an

Erase or Program operation is in progress.

CONCURRENT READ/WRITE STATE TABLE

Flash SRAM

Program/Erase Read

Program/Erase Write

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

Product Identification

The Product Identification mode identifies the devices as

either SST31LF041 or SST31LF041A and the manufac-

turer as SST. This mode may be accessed by hardware or

software operations. The hardware device ID Read opera-

tion is typically used by a programmer to identify the correct

algorithm for the SST31LF041/041A flash memory banks.

Users may wish to use the software Product Identification

operation to identify the part (i.e., using the device ID) when

using multiple manufacturers in the same socket. For

details, see Table 3 for hardware operation or Table 4 for

software operation, Figure 12 for the software ID entry and

read timing diagram and Figure 19 for the ID entry com-

mand sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software reset command is ignored during an

internal Program or Erase operation. See Table 4 for soft-

ware command codes, Figure 13 for timing waveform and

Figure 19 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from VDD to VSS should be placed within 1 cm of

the VDD pin.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST31LF041 0001H 17H

SST31LF041A 0001H 16H

T1.2 1107

I/O Buffers

1107 B1.6

Address Buffers

DQ7 - DQ0

OE#

BEF#

WE#

SuperFlash

Memory

SRAM

Control Logic

BES#

AMS - A0

AMS = Most Significant Address

Address Buffers

& Latches

FUNCTIONAL BLOCK DIAGRAM

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 14MM) - SSTLF041

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) - SSTLF041A

A16

A15

A14

A13

A12

A11

WE#

BES#

A18

A17

VSS

A10

DQ7

DQ6

DQ5

DQ4

VDD

DQ3

DQ2

DQ1

DQ0

OE#

VSS

BEF#

1107 40-tsop P1.2

Standard Pinout

Top View

Die Up

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

OE#/BES#

A10

BEF#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1107 32-tsop P2.1

Standard Pinout

Top View

Die Up

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses. A18-A0 to provide flash address

A16-A0 to provide SRAM addresses for

SST32LF041/041A

During flash Sector-Erase, A18-A12 address lines will select the sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle.

The outputs are in tri-state when OE# or BES# and BEF# are high.

BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.

Note: For SST31LF041A, BES# and OE# share pin 32.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low.

OE# Output Enable To gate the data output buffers.

Note: For SST31LF041A, BES# and OE# share pin 32.

WE# Write Enable To control the Write operations.

VDD Power Supply 3.0-3.6V Power Supply

VSS Ground

T2.11 1107

1. AMS = Most significant address

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

TABLE 3: OPERATION MODES SELECTION

Mode BES#1BEF#1OE# WE# A9DQ Address

Flash

Read X2VIL VIL VIH AIN DOUT AIN

Program X VIL VIH VIL AIN DIN AIN

Erase X VIL VIH VIL X X Sector address,

XXH for Bank-Erase

SRAM

Read VIL VIH VIL VIH AIN DOUT AIN

Write VIL VIH XV

IL AIN DIN AIN

Standby VIHC VIHC X X X High Z X

Flash Write Inhibit X X VIL X X High Z / DOUT X

XXXV

IH X High Z / DOUT X

IH X X X High Z / DOUT X

Product Identification

Hardware Mode X VIL VIL VIH VHManufacturer’s ID (BFH)

Device ID3

A18-A1=VIL, A0=VIL

A18-A1=VIL, A0=VIH

Software Mode X VIL VIL VIH AIN ID Code See Table 4

T3.9 1107

1. BES# and BEF# cannot be asserted simultaneously. For SST31LF041A BES# and OE# share pin 32.

When flash is active, pin 32 becomes OE#. When flash is inactive, pin 32 becomes BES#.

2. X can be VIL or VIH, but no other value.

3. Device ID 17H for SST31LF041 and 16H for SST31LF041A.

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1

1. Address format A14-A0 (Hex), Address A18-A15 can be VIL or VIH, but no other value, for the Command sequence.

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2

2. BA = Program Byte address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3

3. SAX for Sector-Erase; uses A18-A12 address lines

30H

Bank-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5

4. The device does not remain in Software Product ID mode if powered down.

5. With A18-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST31LF041 Device ID = 17H, is read with A0 = 1,

SST31LF041A Device ID = 16H, is read with A0 = 1

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H

T4.7 1107

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

Extended -20°C to +85°C 3.0-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 15 and 16

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

TABLE 5: DC OPERATING CHARACTERISTICS (VDD = 3.0-3.6V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input = VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 12 mA BEF#=VIL, BES#=VIH

SRAM 40 mA BEF#=VIH, BES#=VIL

Concurrent Operation 55 mA BEF#=VIH, BES#=VIL

Write OE#=VIH, WE#=VIL

Flash (Program) 15 mA BEF#=VIL, BES#=VIH

SRAM 40 mA BEF#=VIH, BES#=VIL

ISB1Standby VDD Current 30 µA BEF#=BES#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.4 V VDD=VDD Min

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VHSupervoltage for A9 pin 11.4 12.6 V BEF#=OE#=VIL, WE#=VIH

IHSupervoltage Current for A9 pin 200 µA BEF#=OE#=VIL, WE#=VIH, A9=VH Max

T5.15 1107

1. Specification applies to commercial temperature devices only. This parameter may be higher for extended devices.

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T6.2 1107

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.2 1107

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.4 1107

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

AC CHARACTERISTICS

TABLE 9: SRAM MEMORY BANK CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)

Symbol Parameter

SST31LF041/041A-70 SST31LF041A-300

UnitsMin Max Min Max

TRCS Read Cycle Time 70 300 ns

TBES Bank Enable Access Time 70 300 ns

TAAS Address Access Time 70 300 ns

TOES1

1. No TOES value for SST31LF041A

Output Enable Access Time 35 150 ns

TBLZS2

2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 0 ns

TOLZS1Output Enable to Active Output 0 0 ns

TBHZS1BES# to High-Z Output 25 30 ns

TOHZS1Output Disable to High-Z Output 25 30 ns

TOHS Output Hold from Address Change 0 10 ns

T9.8 1107

TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)

Symbol Parameter

SST31LF041/041A-70 SST31LF041A-300

UnitMin Max Min Max

TWCS Write Cycle Time 70 300 ns

TBWS Bank Enable to End-of-Write 60 230 ns

TAWS Address Valid to End-of-Write 60 230 ns

TASTS Address Set-up Time 0 0 ns

TWPS Write Pulse Width 60 200 ns

TWRS Write Recovery Time 0 0 ns

TDSS Data Set-up Time 30 150 ns

TDHS Data Hold from Write Time 0 0 ns

T10.5 1107

TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)

Symbol Parameter

SST31LF041/041A-70 SST31LF041A-300

UnitsMin Max Min Max

TRC Read Cycle Time 70 300 ns

TBE Bank Enable Access Time 70 300 ns

TAA Address Access Time 70 300 ns

TOE Output Enable Access Time 40 150 ns

TBLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BEF# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TBHZ1BEF# High to High-Z Output 15 60 ns

TOHZ1OE# High to High-Z Output 15 60 ns

TOH1Output Hold from Address Change 0 0 ns

T11.5 1107

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)

Symbol Parameter

SST31LF041/041A-70 SST31LF041A-300

UnitsMin Max Min Max

TBP Byte-Program Time 20 20 µs

TAS Address Setup Time 0 0 ns

TAH Address Hold Time 30 50 ns

TBS WE# and BEF# Setup Time 0 0 ns

TBH WE# and BEF# Hold Time 0 0 ns

TOES OE# High Setup Time 0 0 ns

TOEH OE# High Hold Time 10 10 ns

TBP BEF# Pulse Width 40 100 ns

TWP WE# Pulse Width 40 100 ns

TWPH WE# Pulse Width High 30 50 ns

TBPH BEF# Pulse Width High 30 50 ns

TDS Data Setup Time 40 50 ns

TDH Data Hold Time 0 0 ns

TIDA Software ID Access and Exit Time 150 150 ns

TSE Sector-Erase 25 25 ms

TSBE Bank-Erase 100 100 ms

TBS Bank Enable Setup Time for

Concurrent Operation

00ns

T12.4 1107

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM

1107 F02.10

ADDRESS A16-0

DQ7-0

WE#

OE#1

BES#1

TBES

TRCS TAAS

TOES

TOLZS

VIH

HIGH-Z

TBLZS TOHS TBHZS

HIGH-Z

DATA VALIDDATA VALID

TOHZS

BEF#

Note 1: For SST31LF041A.

BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#.

1107 F03.11

ADDRESS A16-0 ADDRESS

DQ7-0

OE#1

WE#

BES#1

TBWS

TWCS

TAWS

TASTS

TWPS TWRS

TDSS TDHS

DATA VALID

BEF#

Note 1: For SST31LF041A.

BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#.

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM

FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1107 F18.6

ADDRESS A

18-0

7-0

WE#

OE#

BEF#

BES#

OLZ

HIGH-Z

BLZ

BHZ

HIGH-Z

DATA VALIDDATA VALID

OHZ

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

1107 F04.7

ADDRESS A

18-0

7-0

TWPH

BEF#

BES#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM

FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM

1107 F05.7

ADDRESS A18-0

DQ7-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#1

BEF#

TBP

BES#1

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

1107 F06.7

ADDRESS A18-0

DQ7DD# D# D

WE#

OE#1

BEF#

TOEH

TOE

TCE

TOES

BES#1

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM

FIGURE 10: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

1107 F07.7

ADDRESS A18-0

DQ6

WE#

OE#1

BEF#

TOE

TOEH

TBE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

BES#1

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

1107 F08.9

ADDRESS A18-0

DQ7-0

WE#

SW0

Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

SAX = Sector Address

SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

OE#

BES#

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 11: WE# CONTROLLED FLASH BANK-ERASE TIMING DIAGRAM

FIGURE 12: FLASH SOFTWARE ID ENTRY AND READ

1107 F17.9

ADDRESS A18-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

BEF#

SIX-BYTE CODE FOR BANK-ERASE

TSBE

TWP

Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are

interchangeable as long as minimum timings are met. (See Table 12)

OE#1

BES#1

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

1107 F09.8

ADDRESS A

14-0

IDA

7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

BEF#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

WPH

Device ID

55AA 90

OE#

BES#

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

Note: Device ID = 16H for SST31LF041A and 17H for SST31LF041.

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 13: FLASH SOFTWARE ID EXIT AND RESET

FIGURE 14: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH/SRAM AND SRAM/FLASH

1107 F10.8

ADDRESS A14-0

DQ7-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

BEF#

AA 55 F0

OE#1

BES#1

Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.

1107 F22.0

ADDRESS A18-0

TBS

DQ7-0

BEj#

BEj1#

WE#

OE#

Note: j = F or S

j1 = S or F

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 16: A TEST LOAD EXAMPLE

1107 F11.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Tes t

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1107 F12.2

TO TESTER

TO DUT

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 17: BYTE-PROGRAM ALGORITHM

1107 F13.2

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 18: WAIT OPTIONS

1107 F14.0

Wait TBP,

TSBE, or TSE

Byte

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte

Program/Erase

Initiated

Byte

Program/Erase

Initiated

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS

1107 F15.2

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

FIGURE 20: ERASE COMMAND SEQUENCE

1107 F16.2

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

Wait TSBE

Chip erased

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

Wait TSE

Sector erased

to FFH

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

PRODUCT ORDERING INFORMATION

Valid combinations for SST31LF041

SST31LF041-70-4C-WI

SST31LF041-70-4E-WI

Valid combinations for SST31LF041A

SST31LF041A-70-4C-WH

SST31LF041A-300-4C-WH

SST31LF041A-70-4E-WH

SST31LF041A-300-4E-WH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST31LF04xx- XXX -XX-XX

Package Modifier

H = 32 leads

I = 40 leads

Package Type

W = TSOP (type 1, die up, 8mm x 14mm)

(type 1, die up, 10mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

300 = 300 ns

Version

A = 32-lead TSOP Package

Density

041 = 4 Mbit Flash + 1 Mbit SRAM

Voltag e

L = 3.0-3.6V

Product Series

31 = Monolithic ComboMemory

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EOL Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

PACKAGING DIAGRAMS

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

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Preliminary Specifications

4 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF041 / SST31LF041A

40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM

SST PACKAGE CODE: WI

TABLE 13: REVISION HISTORY

Number Description Date

03 •2002 Data Book Feb 2002

04 •Removed the 256 SRAM parts (SST31LF043/043A) and associated MPNs

•Corrected the Test Conditions for IDD in Table 5 on page 10

•Added Revision History

Sep 2003

05 •2004 Data Book Dec 2003

06 •End of Life for all valid combinations Jun 2008

12.50

12.30

14.20

13.80

0.70

0.50

10.10

9.90

0.27

0.17

1.05

0.95

0.15

0.05

0.70

0.50

40-tsop-WI-7

Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

Pin # 1 Identifier

0.50

BSC

1.20

max.

1mm

0˚- 5˚

DETAIL

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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