FO e-Front runners FA5516/FA5517/FA5518 Quality is our message Fuji Switching Power Control I C FA5516 FAS517 FA5S518 Application Note Aug-2005 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message Warnin g > 1. This Data Book contains the product specifications, characteristics, data, materials and structures as of August 2005. The contents are subject to change without prior notice for specification changes or other reasons. When using a product listed in this Data Book, be sure to obtain the latest specifications and check the data. 2. All applications described in this Data Book give examples of applications of Fuji Electrics products for your reference. No right or license, either express or implied, under any patent, copyright, trade secret or other intellectual property right owned by Fuji Electric Co., Ltd. shall be granted. 3. Although Fuji Electric Device Technology Co., Ltd. continually strives to enhance product quality and reliability, a small percentage of semiconductor products may become faulty. When using Fuji Electric semiconductor products in your equipment, be sure to take adequate safety measures such as redundant, flame-retardant and fail-safe design in order to prevent a semiconductor product failure from leading to a physical injury, property damage or other problems. 4. The products introduced in this Data Book are intended for use in the following electronic and electrical equipment which requires ordinary reliability: Computers -OAequipment - Communications equipment (terminal devices) Measurement equipment + Machine tools - Audiovisual equipment : Electrical home appliances + Personal equipment - Industrial robots, etc. 5. lf you need to use a semiconductor product in this Data Book for equipment requiring higher reliability than normal, such as listed below, be sure to contact Fuji Electric Device Technology Co., Ltd. to obtain prior approval. When using these products, take adequate safety measures such as a backup system to prevent the equipment from malfunctioning when a Fuji Electrics product incorporated in the equipment becomes faulty. Transportation equipment (mounted on vehicles and ships) + Trunk communications equipment : Traffic-signal control equipment ~- Gas leakage detectors with an auto-shutoff function - Disaster prevention / security equipment - Safety devices 6. Do not use a product in this Data Book for equipment requiring extremely high reliability such as: - Space equipment - Airborne equipment +* Atomic control equipment - Submarine repeater equipment ~- Medical equipment 7. All rights reserved. No part of this Data Book may be reproduced without permission in writing from Fuji Electric Device Technology Co., Ltd. 8. lf you have any question about any portion of this Data Book, ask Fuji Electric Device Technology Co., Ltd. or its sales agencies. Neither Fuji Electric Device Technology Co., Ltd. nor its agencies shall be liable for any injury or damage caused by any use of the products not in accordance with instructions set forth herein. \ / Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message Contents 1. Outline sae 2. Features nae 3. External dimension diagram ao 4. Block diagram nee 5. Pin assignments ee 6. Line of FA1516/17/18 series me 7. Ratings and characteristics se 8. Characteristic curves te 9. Description of block circuits sae 10. Design advice cae 1.1. Examples of application circuits nae Note) - The contents of this Data Book are subject to change reasons. - Application examples and parts constants listed in this wee - 4 wees weoeee 4 wee eee - 4 wee eee - 5 eee - 5 eee sees ese ee 6~9 ees eee eee ee . 10~13 eee ene n ne ne = 14~23 ees es eee noes . 24~31 wee eee eee - 32 without prior notice for improvement or other Data Book are intended for design reference, without giving due consideration to unevenness in parts characteristics and usage conditions. When using, be sure to design the relevant circuit giving due consideration to unevenness in parts characteristics and usage conditions. Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message 1. Outline FA5516/17/18 series are current-mode switching power control ICs that can directly drive power MOSFETs. Low-power dissipation is achieved due to adoption of high-withstand voltage CMOS process. In addition, stand-by power consumption can substantially be reduced due to a built-in start-up circuit. Many functions are incorporated in an eight pin package, reducing the number of external parts and allowing compact and high cost performance power supply 2. Features - Built-in start-up circuit of 500V withstand voltage that is cut off after start-up (input current after cutoff: 2OyA (typ.)) Low power dissipation due to adoption of high-withstand voltage CMOS process During operation : 1.2mA (typ.) (for FA5518) * Built-in frequency-decreasing function at light load - Oscillating frequency FA5516 : 130kHz(typ.),FA5517 : 100kHz(typ.),FA5518 : 6OkHz(typ.) - Built-in latch-mode cutoff function at overload - Built-in latch-mode cutoff function at overvoltage - Built-in malfunction-protective circuit at low voltage (13V ON/9V OFF) * 8 pin package (DIP / SOP) 3. External dimension diagram Unit : mm SOP-8 (FA5516N/FA5517N/FA5518N) DIP-8 (FAS516P/FA5517P/FA5518P) i 0.1840.08 8 5 Db co 7) wo L ee 4 9.4 4.040.3 1.540.3 l} bd Zz | ! o | T 0.40+0.1 2.54*3=7.62 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message 4. Block diagram cs (1 o~ SV reo 1OpA/5pA VCC Latch HAIOU 5V Ot LI off VH ENB 4 VP 8 Wh] pee START (8) ! UVLO 8.2V/7.5V = eovec P r UVLO (6) ok > 74.0V/3.5V u [30V 2.8V Buf 13V/9V 300k 100k L 7.4k] Ct v = " + = ENB OUT OverLoad ~ OSC uf ) (5) aoe Tye Tahoe our fout_ TH+ TRG Q = PUT Av CLR | 7 S$ Q em ap 60k FF GND F. 4 ok tT IS comp {? (4) > 0.5V tL 2.7k t ~ () IS (3) 5. Pin assignments Pin Symbol | Function Description 1 cs Soft start/latch-mode stop | Soft start, latch-mode stop 2 FB Feedback input Input for controlling current comparator threshold voltage 3 IS Current sensor input Input for monitoring MOSFET current 4 GND Ground Power supply ground 5 OUT Output Output for directly driving a MOSFET 6 Vcc Power supply Power supply for ICs 7 (NC) No connection No connection 8 VH High voltage input Input terminal for start-up circuit 6. Line-up of FA5516/17/18 series Switching Type Frequency (kHz) Package FA5516P 130 (typ.) DiP-8 FA5516N SOP-8 FA5517P DIP-8 100 . FA5517N (tyP.) SOP-8 FA5518P DIP-8 60 . FA5518N (typ) SOP-8 Fuji Electric Device TechnologyFCO e-Front runners FA5516/FA5517/FA5518 Quality is our message 7. Ratings and characteristics * In defining a current, -- represents a sink current and a source current. (1) Absolute maximum ratings Item Symbol | Rating Unit Low impedance source Vec1 28 V Supply (Icc>15mA) voltage Built-in Zener clamp (Icc<15mA) Vcc2 Self Limiting Vv lou -0.5 A OUT pin peak current IOL +1.0 A OUT pin voltage Vout -0.3~VCC+0.3 Vv FB/ IS pin voltage VLT -0.3~5.0 Vv CS pin current Ics 2.0 mA CS pin minimum voltage VcsL -0.3 Vv VH pin Voltage WH -0.3~500 Vv 800 (DIP-8) Total issipati =25C otal power dissipation (Ta ) Pd 400 (SOP-8) mw Ambient temperature Ta -30~+85 C Maximum junction temperature Tj 125 C Storage temperature Tstg 040~+150 C Permissible power dissipation decreasing characteristics 400mW(SOP) 800mV\(DIP) s 8 33 2D a5 &8 0 { -30 25 85 125 Ambient temperature Ta (C) (2) Recommended operating conditions Item Symbol MIN TYP MAX Unit Supply voltage Vec 10 18 26 Vv DC WHC) 80 450 Voc) Half-wave WVH(AC1) 80 288 Vac) VH pin voltage rectification Full-wave VWVH(AC2) 80 288 Vac) rectification VH pin series resistor RVH 2.2 47 ko CS pin capacitor Ccs 0.01 1 HF VCC pin capacitor Cvcc 10 33 YF Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message (3) Electrical characteristics (Vcc=18V, Tj=25C, unless otherwise specified) Oscillator (FB pin) Item Symbol | Condition MIN TYP MAX Unit FA5516 | 117 130 143 Oscillating frequency Fosc FB=3V FA5517 =| 90 100 110 kHz FA5518 | 54 60 66 Supply voltage stability Fdv Vec=10~26V -2 2 % Temperature stability FdT Ta=-30~85C -0.07 %PC Fa pi votage forthe vin o9 fio [sav ARLAVEB FA5516 310 Frequency reduction ratio | kf FB=0.8V ~ | FA5517 240 kHz/V 0.9V | FA5518 140 a FA5516 13 ight load frequency at! Fog FB=0.6V | FA5517 __ [0 kHz FA5518 7 Minimum frequency Fmin 0.5 1.5 4.0 kHz Pulse width modulator (FB pin) Item Symbol | Condition MIN TYP MAX Unit Maximum duty cycle DMAX FB=3V,CS=3V 76 80 84 % Minimum duty cycle DMIN FB=0V,CS=3V 0 % FB voltage for pulse stop VTHFBO Duty cycle=0% 230 330 430 mV FB pin current Ifo FB=0V -620 -520 -420 yA Current sensor (IS pin) Item Symbol | Condition MIN TYP MAX Unit Voltage gain Avis AVEBIAVIS 3.8 4.0 42 VN Maximum threshold voltage | Vthis1 FB=4V,duty=10% 450 500 550 mV ; FA5516 36.0 Com ponaation Starting slope | ngs FA5517 34.6 % FA5518 31.7 FA5516 -24 Slope compensation value | SLP FB=4V FA5517 -17.5 mV/s FA5518 -10 VIS=0V FA5516 -8.5 Input bias current lls Average FA5517 -9.0 pA current FA5518 -9.5 FB=3V FA5516 0.4 Minimum ON pulse width =| Tmin CS=0V FA5517 0.6 Us IS=1V FA5518 0.8 FA5516 0.2 Blanking time Tblank FA5517 0.4 ys FA5518 0.6 Output delay time Tpdis IS to OUT 200 ns Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message Soft-start circuit (CS pin) Item Symbol | Condition MIN TYP MAX Unit Charging current Icso CS=0V -14 -10 -5 HA Threshold voltage for VTHcst 3 V changing charging current Input threshold voltage VtHcso | OUT=Tmin, FB=3V 0.6 Vv Latch-mode cutoff circuit (CS pin) Item Symbol | Condition MIN TYP MAX Unit Charging current Ics4 CS=4V -7 -6 -2.5 yA Sink current Isink CS=6V 20 35 50 HA VTHCSF | ON-OFF 7.7 8.2 8.7 Vv Cutoff threshold voltage VTHCSN | OFF>ON 7.0 7.5 8.0 Vv Hysteresis width VTHHYS 0.7 V Clamp voltage at latch mode | Vcs2 FB=open 8.8 V Cutoff circuit at overload (FB pin) Item Symbol | Condition MIN TYP MAX Unit Detection threshold voltage VTHFB 3.2 3.5 3.8 Vv Cutoff circuit at overvoltage (VCC pin) Item Symbol | Condition MIN TYP MAX Unit Threshold voltage VTHVCC 26.0 28.0 30.0 Vv CS pin charging current Isocs2 CS=4V -1.0 mA Malfunction-protective circuit at low voltage (VCC pin) Item Symbol | Condition MIN TYP MAX Unit ON threshold voltage VCCON 11.5 13.0 14.5 Vv OFF threshold voltage VCCOFF 8.0 9.0 10.0 Vv Hysteresis width VHYS 3.0 4.0 5.0 Vv Output section (OUT pin) Item Symbol | Condition MIN TYP MAX Unit Low output voltage VOL loL=100mMA 0.3 0.6 Vv High output voltage VoH loH=-100mA,Vcc=18V 14.8 16.4 Vv Rise time tr CL=1nF 50 ns Fall time tf CL=1nF 40 ns Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message High voltage input section (VH pin, VCC pin) Item Symbol | Condition MIN TYP MAX Unit . IHrun VH=450V,Vcc> Vecon 10 20 30 pA VH pin input current IHstb VH=100V,Vcc=0V 3.4 mA VCC voltage at latch mode | VccL VH=100V 22 V Ipret Vec=10V,VH=100V -2.4 -1.4 mA VCC pin charging current = = Pp ging Ipre2 Vec=13V,VH=100V 47 09 mA at latch mode Consumption current (VCC pin) Item Symbol | Condition MIN TYP MAX Unit Duty cycle FA5516 1.4 2.0 iccop: | =DMAX, FA5517 13 2.0 mA Supply current during FB=3V, operation no load FAS518 1.2 2.0 Duty cycle=0%, Iccop2 EB-0V 1.3 2.0 mA Consumption current at _ _ latch mode IccL FB=open, CS=open 270 350 HA Zener voltage Vz Iz=2mA 30 V Fuji Electric Device TechnologyFO e-Front runners 8. Characteristic curves - Unless otherwise specified, Ta=25C, Vec=18V - In defining a current, + represents a sink current and - a source current. FA5516/FA5517/FA5518 Quality is our message * The data stated in this chapter are intended for giving typical IC characteristics and not for guaranteeing performance. S835 AAEM (Afosc) vs. BIRBE (Vcc) 1.0 0.5 & Oo 3 0.0 XN -0.5 -1.0 10 15 20 25 Voc (V) SRR (fosc) vs. FBsa- RE (VFB) 140 FA5516 120 FA5517 100 80 FA5518 60 fosc (kHz) 40 20 0 0.0 1.5 VFB (V) 0.5 1.0 2.0 2.5 BAT 1F4F 4 DI (Dmax) vs. YYUIY aL (Tj) 81. 80. 80. 80. 80. 80. 79. 79. 79. 79. 79. Dmax (%) OM FF MDAONM FD O 50 100 Tj (C) 1 oa o oO 30 3.0 150 3235 A RE IL (Afosc) vs, Deyo] VIBE (Tj) s 3 2 NX -50 0 50 100 150 Tj Cc) mA RM (fmin) vs. Vervgy;y VIBE (Tj) 3.5 3 2.5 / = 2 / = = ts ee J 1 0.5 0 -50 0 50 100 150 Tj Co) mA DH (Tmin) vs. VervV oD a VIBE (T)) 900 FA5518 800 700 z FA5517 cc c 600 z 500 400 300 -50 FA5516 0 50 T (C) 100 150 10 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message CSHB BR (ics) vs. Vervgva VBE (Tj) 50 40 30 20 Ics (uA) 13.5 Vocon V) . 00 25 CS=0V 50 LO 715 4 a 00 a N_] 25 50 -50 0 50 100 150 Tj (Cc) CSigF BR (los) vs. CS#a#-F BE (Ves) FB=open 0 2 4 6 8 10 12 Ves (V) UVLO ONAL 2} 3 BE (Vecon) Vs. VYU9OL3a VBE (T)) ~50 0 50 Tj (C) 100 150 CSHHFRBBRA (lcs) vs. VervavavwK (Tj) -4.25 CS=4V -4. 50 2 YS a -4.75 / 8 a _ Z| 5.00 -5. 25 -50 0 50 100 150 Tj CC) CSteF Bi (lcs) vs. CSd#i- FEE (Ves) 50 FB=3V 40 30 20 10 Ios (A) 0 -10 -20 0 2 4 6 8 10 12 Vos (V) UVLO OFFAL 2) 3 SE (VCCOFF) Vs. YrU9Ya Vis (Tj) 9.5 9.3 9.1 VccorF (V) 8.9 8.7 8.5 100 150 Tj (CC) " Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality 1s our message Voc-V 0H (V) Vthis1 (mV) iFB ( A) OUT## HH WBE (Von) vs. BIR (Vcc) 1.7 lon=-100mA 1. 66 1.62 _ oo 1.58 pe 1.54 1.5 10 15 20 25 30 Voc (V) ISH#F BAADAL YL 32BE (Vthisl) VS. DeUOYa VEE (T)) 515 Duty cycle 510 =10% 505 500 495 490 485 480 475 -50 0 50 100 150 Tj (C) FBS 38 (IFB) vs. FBaa ASE (VFB) 0 -100 LO -200 fo -300 VA -400 -500 ZO ~600 0 1 2 3 4 5 VFB (V) OUTMFLHi EE (VOL) vs. BIRR (Vcc) 0. 35 loL=100mA 0.33 _ 0.31 s a > 09.29 0.27 0. 25 10 15 20 25 30 Voc (V) SMF ANALY La BE (Vthis) vs. FBii-F #85 (VeB) 500 uty cycle -50% 400 S 300 y = / 5 200 = / 100 / 0 0.0 1.0 2.0 3.0 4.0 VFB (V) VCCiat SRG RHERER AL y > aE (VtTuvcc) 08.6 vs. Yervugya VBE (Tj) 28. 4 28.2 TZ 28.0 ZO 27.8 LO | ex 27.6 VtHvee (V) 27.4 -50 0 50 100 150 Tj (C) 12 Fuji Electric Device TechnologyFCO e-Front runners FA5516/FA5517/FA5518 Quality is our message HAR VCCmtitE BH (pre) HBG VCCI BSH (pre) VS. SIRBE (Voc) vs. DyV9gy; VBE (Tj) -2.0 0.0 - yg | WHE100V VVH=100 2b Vee=0V 0.5 -2.4 -1.0 ~2.6 ~ = 2.8 E'S = -3.0 5 -2.0 a & 3.2 ~2 5 V4 -3.4 eo -3.6 -3.0 = -3.8 35 -4.0 0 5 10 15 -50 0 50 100 150 Voc (V) Tj (C) HOR VCCI Bs (Ipre) IStaF MAADALYL) aBeE (Vthis1) vs. vs. VHig--7SE (VvH) FaF4-v4Aw) -2. 80 - , Veo=0 0. 50 VeB=4V -3.00 \ \ 0. 48 -3. 20 > = \ ES 0.46 -3. 40 \ 3 FaSs16] / a Ss FA5517 -3. 60 SX = 0.44 FAS518) -S__ -3. 80 0. 42 ~4. 00 0. 40 0 100 200 300 400 0.0 0.2 0.4 0.6 0.8 1.0 VvH (V) D SR BIR (Iccopl) vs. BIRBE (Vcc) SER BMBR(lccopl) vs. Very aya VBE (Tj) 1.5 15 FA5516 ee | FA5516 1.4 1.4 | FA5517 - fo _| FAST ze 13 / 1.3 =< = = FA5518 8 aL FAB g 8 12y 81.2 1.1 1.1 1 1.0 10 15 20 25 30 -50 0 50 100 150 Voc (V) Tj CC) Fuji Electric Device Technology 13FO e-Front runners FA5516/FA5517/FA5518 Quality is our message 9. Description of block circuits (1) Start-up circuit The FA5516/17/18 has built-in start-up circuits with maximum rated voltage of 500V. Wiring is shown in Figs.1 to 3. When power is turned on, a current is supplied to the VCC pin from the start-up circuit, charging the capacitor, C2, connected to the VCC pin, increasing its voltage, activating the IC, and the power supply starts operation. The current supplied to the VCC pin from the VH pin is approximately 3mA at Voc=0V, decreases as Vcc aDER sl start 6 increases and becomes approximately 1.7mA at the on/offfss + start-up voltage. A resistor is connected in series to the VH pin to prevent the IC from being damaged due to surge voltage in AC and other lines. Fig.1 shows the commonest wiring, connecting the VH pin to half-wave rectified AC input voltage and taking the longest start-up time of the three ways of wiring. When AC input voltage is turned off after the circuit changed to a latch mode due to overload or overvoltage protection, the latch mode can be reset in a relatively short time of several seconds because a current is not supplied from the VH pin. In Fig.2, the VH pin is connected to full-wave rectified AC input voltage, reducing start-up time to approximately half as compared to half-wave rectification circuit shown in Fig.1. The latch mode can be reset in a short time same as in Fig.1 because AC input voltage is cut off. In Fig.3, the VH pin is connected to rectified and smoothed AC input voltage, resulting in the shortest start-up time of the three ways of wiring. In this way of wiring, it takes time for the latch mode to be reset because charged C1 voltage is applied to the VH pin even if the IC have changed to the latch mode. Depending on usage conditions, in general it takes several minutes. When VCC pin voltage exceeds ON threshold voltage of the low-voltage malfunction-protective circuit and the IC is activated, the start-up circuit is cut off and VH pin input current becomes 20,A (typ.). on/offfE Ss +/C2 When the IC changes to the latch mode due to overload KEE : BIOMEL, ACANSBRLTL. or overvoltage protection, the start-up circuit is activated FIFEFOU CIN BRA BE again, the latch condition is maintained and Vcc voltage is Fig.3 Start-up circuit 3 (DC) held at approximately 22V. (See 9.-(8) Overload protection, 9.-(9) Overvoltage protection.) 14 Fuji Electric Device TechnologyFC e-Front runners FA5516/FA5517/FA5518 Quality is our message (2) Oscillator The oscillator determines switching frequency. For normal operation, the oscillating frequency is set at 130kHz for FA5516, 100kHz for FA5517 or 6O0kHz for FA5518 inside the IC. In addition, the IC has a function to automatically decrease oscillating frequency at light load to reduce standby power dissipation. When FB pin voltage becomes 1.0V or less at light load, the frequency starts decreasing. At light load, as FB pin voltage drops, the frequency ; _ ; 0.33V 1.0V FBiaF decreases almost linearly to the minimum operating =z frequency (Fig.4). The minimum operating frequency, Fmin, is set at 1.5kHz. Fig.4 Oscillating frequency The oscillator generates a trigger signal for determining the switching frequency, a pulse signal for determining the maximum duty cycle and a ramp signal for slope compensation. (3) Current comparator and PWM latch FA5516/17/18 are current mode comparators. Fig.5 OSC FF Blanking shows a block diagram for basic operation and Fig.6 a Rs timing chart. IS comp. s a 5 A trigger signal is generated by the oscillator and input to R the PWM latch (F.F.) as a set signal through a blanking FF. Circuit, increasing PMW latch output and also OUT pin voltage. vi 3 On the other hand, the current comparator (IS comp.) monitors a MOSFET current and generates a reset signal when OUT pin voltage reaches the threshold voltage. Fig.5 Current-mode basic operation circuit block Then, PWM latch (F.F.) output and OUT pin voltage go into low state Blanking HA The output is controlled through varying IS comparator {set pulse) | threshold voltage due to a feedback signal. As shown in Fig.7, FB pin voltage and CS pin voltage auth are level-shifted and input to the current comparator (IS (OUTH A) comp.) as threshold voltage. In addition, the reference voltage of 0.5V is input to the IC to determine IS pin toone IS comp. ALyY sR maximum threshold voltage. MOSFET Bit The lowest of the three inputs is given a high priority. 1S comp. a (reset pulse) ja awe a we ww og we ee em eed wee Fig.6 Timing chart for current-mode basic operation 415 Fuji Electric Device TechnologyFCO e-Front runners FA5516/FA5517/FA5518 Quality is our message At start-up, soft start can be realized through gradually increasing the threshold voltage based on CS pin voltage. At normal operation, the threshold voltage is varied based on FB pin voltage to keep power supply output voltage constant. in addition, the maximum IS pin threshold voltage limits MOSFET overcurrent. The maximum threshold voltage is 500mvV (typ.) over the range where the duty cycle is 30% or less. When the duty cycle exceeds 30%, the maximum threshold voltage varies due to slope compensation as described later. For details, refer to the mid right diagram IS pin maximum input threshold voltage vs. duty cycle in p.13. The oscillator generates a pulse to determine the maximum duty cycle of an OUT pulse and the maximum duty cycle is set at 80% (typ.) using this pulse.. Fig.7 Current comparator For details, refer to 9-(12) Timing chart in p.21. (4) Blanking When MOSFET turns on, a surge current is generated due to discharge current from the capacitor in the main circuit or gate drive current. If the surge current reaches the IS pin threshold voltage, current comparator output | ~--p-~--f- IS could be inverted and normal pulses would not be Abyya LEE istat enerated from the OUT pin. - g p 2 To avoid this, a blanking function is incorporated into the current comparator. When a trigger signal is input from the oscillator, the blanking circuit outputs a certain-width pulse signal as a PWM latch (F.F.) set signal. Since the set signal is given a high priority in PWM latch input signals, the output of PWM latch (F.F.) will not be a. inverted while the set signal is input from the blanking an circuit, even if a rest signal is input from the current comparator (IS comp.). As a result, the IS pin input voltage is ignored for a l blanking time (200ns for FA5516, 400ns for FA5517 and FOYEVTIZEY, 600ns for FA5518) immediately after an output pulse has COTH A ULAIS ) y pure FRIELZEL, been generated from the OUT pin and does not respond to a surge current at turn-on. Fig.8 Blanking (See Fig.8.) In general, the blanking circuit eliminates the need for a noise filter at the IS pin. 416 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message (5) Minimum ON pulse width As described in (4) Blanking, the input voltage at the IS pin is ignored during a blanking period right after turn-on. Consequently, the sum of blanking time and output delay time (200ns) is the minimum ON pulse width at the OUT pin of the IC. The minimum ON pulse width for FA5516, FA5517 and FA5518 are 400ns, 600ns and 800ns, respectively. In addition, a dedicated comparator is incorporated not to generate pulses at no load. When FB pin voltage is below 0.33V or less, the output of the comparator is inverted and a clear signal CLR is input to the blanking circuit. Then, the blanking circuit will not output a set signal and no set signals will be input to PMW latch (F.F.), keeping the output voltage low. (See 9-(12) Timing chart.) >. i=] (6) Slope compensation osc VFS In the current mode control, subharmonic oscillation may fout 14414< occur at a continuous current mode operation with a duty a iS comp. cycle of 50% or more. 100k To avoid this, FA5516, FA5517 and FF5518 have built-in slope compensation circuits. For details of subharmonic oscillation phenomenon and 3 I slope compensation effect, see p.31. |" As shown in Fig.9, a ramp signal generated from the oscillator and an MOSFET source current signal are _ Fig.9 Slope compensation circuit combined and input to the current comparator (IS comp.) 2.7k J to realize slope compensation. When the duty cycle exceeds 50%, slope compensation AOTF HED is needed to prevent subharmonic oscillation. Therefore, a ots oa iste= ramp signal is set to be added only when the duty cycle . Loe exceeds 30%. (slope compensation start duty cycle: 36% en sof! aL . fo AR LF BEE ~ t for FA5516, 34.6% for FA5517 and 31.7% for FA5518) 4 While the ramp signal is added, the threshold voltage at the FB pin gradually decreases with time within each switching cycle as shown in Fig.10 even when voltages at the FB pin and CS pin are constant. Fig.10 Slope compensation (See 9-(12) Timing chart.) 7 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Qua L ity is our messa Ze (7) Soft start circuit The CS pin is connected to a built-in constant current source. The current for soft start is 10pA. The capacitor externally connected to the CS pin is charged by the constant current source, gradually increasing CS pin voltage. MOSFET current gradually increases at start-up because CS pin voltage is input to the current comparator (IS comp.), realizing soft start. FB As a guide for soft start time, the time tss taken until CS pin voltage increases from OV to 3V is given by the following equation. 60k tss(s)=0.3 x Cs[yF] ( typical value ) where Cs is CS pin capacitance (pF). 20k In normal operation, CS pin voltage is clamped at approximately 4V by a zener diode in the IC. The FB pin is provided with a built-in circuit to stop pulses when FB pin voltage is 0.33V or less, but the CS pin Fig.11 Soft start circuit is not provided with such a circuit. As a result, OUT pulses of minimum ON width are output even when CS pin voltage is OV. (See 9-(12) Timing chart.) (8) Overload protection % | FA5516, FA5517 and FA5518 have built-in time-latch - th VES VY type overload protection. Fig.12 shows its block diagram on 6) and Fig.13 its Timing chart. 10pA/SpA In normal operation, FB pin voltage is 3V or less and CS pin voltage is clamped at 4V by a zener diode in the IC. | ENB out OD of the CS pin is canceled, increasing CS pin voltage again due to a built-in constant current source. The current Fig.12 Overload protection circuit When power supply voltage drops on account of overload or short-circuit on the load side, FB pin voltage increases. If the voltage exceeds the threshold voltage for overload protection, 3.5V, output voltage of a comparator for overload detection (Overload) is inverted and 4V clamp supplied from the CS pin becomes 5pA. If the power supply voltage continues to decrease and CS pin voltage reaches the threshold voltage (8.2V) of the comparator (Latch), the output of the comparator (Latch) is inverted, turning off a 5V circuit in the IC and forcing OUT pin voltage to be low. This status is the latch mode of the IC. In the latch mode, the start-up circuit resumes operation to supply current to Vcc and to hold the latch mode. 18 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message When the output voltage momentarily drops due to abrupt load change and FB pin voltage restores to normal voltage before CS pin voltage reaches 8.2V, the 4V clamp circuit restarts, producing no latch mode. The latch mode can be reset through cutting off input voltage or through forcibly decreasing CS pin voltage to 7.0V or less. Cutting off the input voltage decreases VH pin voltage, ER supplying no current to the VCC pin. Thereafter, the latch Hi 73 SE VY mM ' mode is reset when Vcc drops below the OFF threshold voltage, 8.0Vmin. In addition, when CS pin voltage is forcibly decreased, the latch mode comparator is re-inverted and the IC re-starts switching operation. ' tt t | , In the case of typical IC, delay time td (OLP), the time from CSiat \ bee 8.2V a ' ' (oY 1 ' overload detection to the latch mode, is given by the following equation. td (OLP) (s)=0.84 x Cs[yF] (typical value ) OUT Sa-F Where Cs is CS pin capacitance (uF). Delay time td(OLP) is inversely proportional to CS B58 BAT AA ee charging current and proportional to the difference between CS pin clamp voltage and latch-mode threshold Fig.13 Overload protection timing chart voltage at normal condition. Pay attention to variations in delay time resulting from variations in numerical values. In addition, be aware that when the VH pin is connected after rectification, it takes rather long time, approximately several minutes, before the latch mode is reset. (See 9-(1) Start-up circuit.) 19 Fuji Electric Device TechnologyFC e-Front runners FA5516/FA5517/FA5518 Quality is our message (9) Overvoltage protection forced to be low to shut down the MOSFET. FA5516, FA5517 and FA5518 have built-in overvoltage protection circuits to monitor Vcc voltage. Fig.14 shows its block diagram and Fig.15 its timing chart. When VCC voltage increases and exceeds comparator (OVP) reference voltage, 28V, an internal 1mA constant current source is tuned on. Since sink capability of the zener diode which clamps the CS pin at 4V is 35p/A, CS pin voltage quickly increases when the imA constant current source is turned on. When CS voltage exceeds comparator (Latch) reference voltage, 8.2V, the IC changes to the latch mode. In the case of typical IC, delay time td (OLP), the time from overload detection to the latch mode, is given by the following equation. td (OLP) (ms)=4.2 x Cs[uF] ( typical value ) Where Cs is CS pin capacitance (uF). In the latch mode, an intemal power supply source, 5V Reg circuit, is turned off and OUT pin voltage is held to be low., and the current form the CS pin changes to 5y/A. The latch mode can be reset through decreasing Vcc voltage due to cutting off of input voltage or through forcibly decreasing CS pin voltage to 7.0V or less. Moreover, pay attention to the relationship between wiring at the VH pin and reset time in the latch mode. (See 9-(1) Start-up circuit.) (10) Undervoltage lockout circuit The IC has a built-in undervoltage lockout circuit to prevent malfunction when Vcc voltage drops. When Vcc voltage increases from OV, the IC starts operation at Vcc=13V(typ.). As the supply voltage decreases, the IC stops operation at Vcc=9V(typ.). When the undervoltage lockout circuits operates and the IC stops operation, OUT pin and CS pin voltage are forced to be low, resetting soft start, and overload and overvoltage timer latch protection. (11) Output circuit The output circuit consists of push-pull configuration, capable of directly driving a MOSFET. The maximum peak currents at the OUT pin are 0.5A for source current and 1.0A for sink current. If the IC stops operation when the undervoitage lockout circuit operates or in the latch mode, OUT pin voltage is 50 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message 7 dos U, 5V Reg. VCC Latch 5V ENB ++ a mA 5V Reg. 8.2V/7.5V = UVLO UVLO ovPp 2.8V FB = av ENB 2 Overload = sa - R = FF. VCC ia F | oT ON HABE ' OUTSa-F | S EI ER . Fig.15 Overvoltage protection timing chart 34 Fuji Electric Device TechnologyQuality is our message FA5516/FA5517/FA5518 e-Front runners (12) Timing chart Bianking CLRIES osc THA Blanking Quy (set pulse) FBint BE \ mee ee oe ee ee eee (Qe = me (fe mm am eee iStay BE IS comp. HA (reset pulse) FF awn osc Quin OUTSE+ WHA Timing chart at normal operation Fig.16 Fuji Electric Device Technology 22Quality is our message FA5516/FA5517/FA5518 e-Front runners i} 1 ' ' ' 1 t t mame - - - ~~ ---- ~~ qo eww mem mene ge we meee ee He fe ee ee ee eh 1 \ ' ' ' ' ee ee ee we ee ew ow eee J44---------jJ----~-~---}----~...-} - 2 ey 3 | oD oR eur ERS ie @ Hs R oR te 3 z lea z Ne i oa iL D #R Sede gBS UU BROS oo ao~ o a a o3 mn - - - - -----p.--- _ --} -----4-| sms Le | __| wef = -P ot --} -----4-| memes Le --- wef - - ~~ ---p ~~ ..--} -----]-. -saemns _ ee e --- I | ao ao OR ee OUeRE oe w a3 R oR s oO we we Ne aa ms RR # rr ae _ Es S$ 386 58 ao a~ 2 a o 38 Fig.18 Timing chart at FB<0.33V Fig.17 Timing chart when Dmax operates Fuji Electric Device Technology 23Quality is our message FA5516/FA5517/FA5518 e-Front runners > 1< osc THA Blanking CLRIES Blanking Quy (set pulse) FB Sat BE CSitat BE (stat BE iS comp. WH (reset pulse) FF QnhnA osc QnA ISVSU IR BEAU Fav 7 Bl + HH 5 ESF) Timing chart at start-up (soft start) Fig.19 Fuji Electric Device Technology 24FO e-Front runners FA5516/FA5517/FA5518 Quality is our message 10. Design advice (1) Start-up and stop To properly start up and stop the power supply, optimum values shall be set for capacitors connected to the CS pin and VCC pin. (1-1) At start-up (1) It takes certain time until the output voltage reaches to the set voltage after the IC has been activated. During this period, FB pin voltage reaches its maximum voltage and the 4V clamp circuit does not operate. As a result, with proper CS pin capacitance and proper start-up, CS pin voltage waveform during start-up will be as shown in Fig.20. On the other hand, when CS pin capacitance is too small, CS pin voltage may reach the threshold voltage of the latch mode as shown in Fig.21 before the output voltage increases to the set value. The IC changes into a latch mode and the power supply cannot start properly. In cases like this, increase CS pin capacitance. (1-2) At start-up (2) Fig.22 shows Vcc voltage at start-up when proper capacitance is connected. When input power is turned on, the Vcc capacitor is charged by the current supplied from the start-up circuit and its voltage increases. Then, when Vcc reaches the ON threshold voltage, the IC starts operation. In normal operation, the IC operates at the voltage supplied from an auxiliary winding. Right after ICs start-up, however, Vcc drops until the auxiliary voltage increases sufficiently. Determine the value of Vcc capacitance so that Vcc does not drop to the OFF threshold voltage. To be specific, determine the value of Vcc pin capacitance so that the lower limit of Vcc becomes 11V or more. HrIt EE Bi uo SH aH FA a Hl FBint = ! a 4 . i g.2V csiiF pone n bpoonn nto. BE VO notre ICE Ick) Fig.20 CS pin voltage waveform at start-up (1) (at normal start) Si HE s FB iat Lid CSiat BE i] J ' 1 / >> ict) | SYFEK Fig21 CSpin voltage waveform at start-up (2) (when the power supply cannot start up) Vec ONALY | fh. VaBeE OFFALY 1B ERG FLEW! OFFALY (HIVELE FES) VaABE HAR + 45 e Beef] t Fig.22 Vcc waveform at start-up (1) (at normal start-up) 95 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message When Vcc capacitance is too small, Vcc drops to the OFF threshold voltage as shown in Fig.23 before the Vec auxiliary winding voltage increases sufficiently. In this case, ONALY Vcc repeatedly goes up and down between the ON and vale OFF threshold voltages, and the power supply cannot start OFFALY up. VaABE (1-3) At stopping When the power supply is turned off by shutdown of t input voltage, output voltage remains low for certain period Fra of time before the IC stops operation. Fig.23 Vcc waveform at start-up (2) During this period, FB pin voltage increases and the CS (when the power supply cannot start up) pin clamp circuit is cancelled because output voltage remains low. As a result, CS pin voltage increases as shown in Fig.24. ea 1 ; HABE \ ' CS pin voltage shall not reach the threshold voltage of 1 the latch mode. As shown in Fig.25, if CS pin voltage | reaches the threshold voltage, the latch mode is held for a VCC Tae period of time until Vcc capacitor voltage drops to OFF SE aiez SE threshold voltage. As a result, the power supply cannot be re-started even if input voitage is turned on again. In such a case, the following measures shall be taken: FBigt - Reduce the time taken until the IC stops operation after BE the output voltage has dropped through reducing Vcc capacitance. atalaatanetenenetete 8.2V - Suppress CS pin voltage rise through increasing CS pin CSiaF 1 capacitance. ee | (2) Hold time of Vcc Fig.24 Waveform at stopping (1) In some cases, VCC pin capacitance shall be increased to hold Vcc above the OFF threshold voltage at abrupt load change after the power supply has started up. However, when VCC pin capacitance becomes larger, start-up time gets longer. In such a case, the circuit shown in Fig.26 is effective. Reducing C2 shortens start-up time, and hold time can OFFALY be kept long because power is supplied via C4 after vaBe start-up. FA5516 M78 -~-8.2V Fig.26 Vcc circuit (Ha CEG AR) Fig.25 Waveform at stopping (2) 96 Fuji Electric Device TechnologyFO e-Front runners FA5516/FAS517/FA5518 Quality is our message (3) Protection using CS pin ; In normal operation, the CS pin voltage is clamped by a 4V zener diode. Externally forcing CS pin voltage to increase to the threshold voltage, 8.2V, for the latch mode allows the IC to stop its operation for protection. In this case, a current of more than the sink capacity of 4V zener diode, 50pA, shall be applied to the CS pin. Set the input current to the CS pin at 1mA or less as a guide. The following shows examples of overvoltage protection at an arbitrary voltage using the CS pin. (3-1) Overvoltage detection on the secondary side Fig.27 shows an example of an overload detection circuit on the secondary side to change the IC into the latch mode. (3-2) Detection of Vcc (1) Fig.28 shows a circuit where the IC is stopped in the latch mode upon detecting Vcc overvoltage. In this case, Vcc voltage is latched at approximately ZD+8.2V. Use a ZD whose voltage is larger than the ON threshold voltage of the low-voltage malfunction preventive circuit. FA5516 A7TH8 Otherwise, the IC cannot start. (3-3) Detection of Vcc (2) Fig.29 shows another circuit to detect Vcc overvoltage. In this case, Vcc voltage is latched approximately at ZD voltage. Use a ZD whose voltage is larger than the ON threshold voltage of the low-voltage malfunction preventive circuit. Otherwise, the IC cannot start. Fig.29 Overvoltage protection (3) (4) When not using an overload protection function As_ shown in Fig.30, connect a resistor R3 of 18kQ between FB pin and GND. As a result, FB pin voltage does not increase to the threshold voltage for overload protection and the IC does FA5516 A718 not change to the latch mode even at overload. In this case, the latch protection for overvoltage is also available. Fig.30 When not using overload protection 97 Fuji Electric Device TechnologyFO e-Front runners (5) Correction of overload detection current If the power supply output becomes overload, the current of the MOSFETIS is limited by the maximum threshold voltage of the IS pin and power supply voltage drops. If the state continues as it is, an overload protection function operates to stop the IC in the latch mode. For details of an overload protection function, see 9-(8) Overload protection function. When the overload protection operates, the output current of the power supply varies depending on the input voltage; and the higher the input voltage is, the larger the output current. In such a case, connect R4 between the current detection resistor Rs and IS pin, and add a correction resistor R5 as shown in Fig.31. The typical resistance of R5 is several hundreds of kQ to several MegQ. Note that the above correction slightly decreases the value of overload current limit to stop the IC in the latch mode even if input voltage is low. In addition, be aware that the added resistance R4 affects slope compensation. (See 10-(6) Slope compensation.) (6) Slope compensation As described in 9.-(6) Slope compensation, slope compensation is implemented by adding a ramp signal generated from the oscillator to IS pin voltage using resistors 100kQ and 2.7kO as shown in Fig.32. Adding R4 can change the magnitude of slope compensation as shown in Fig.33. Adjusted slope compensation is calculated by the following equation: R7+R4 X SLPa = SLP Where, SLPa is adjusted slope compensation; SLP slope of compensation initially set in the IC; and R4 resistance between the {S pin and R3 At the same time, the maximum threshold voltage of R3 voltage varies and the maximum threshold voltage after adjustment is calculated by the following equation. VthiSta =| 1+ R4 R6 }. VthiS1 +R7 Where, Vthis 1a is the maximum threshold voltage after adjustment. FA5516/FA5517/FA5518 Quality is our message FA5516 A7THN8 Fig.31 Correction of overload detection current osc R6 fout_| 490k0 IS comp. R7 2.7kQ | 3 es 7 LS R4 Rs Fig.32 Adjustment of slope compensation EX i ALyvV 28 E P| fen - ----------- VthiSta DL UX ---------- VthIS1 > i SBT ei (R47ZL) S a . wee a SLPa- (RABY) rd 0 FaTF1F 4 Iw Fig.33 Maximum threshold voltage after adjustment 98 Fuji Electric Device TechnologyFO e-Front runners FA5S516/FA5517/FA5518 Quality is our message (7) Improvement of input power at light load This IC is provided with a function to lower switching frequency at light load in order to reduce power dissipation. However, depending on the circuit used, switching frequency cannot be sufficiently reduced, leading to insufficient reduction of power dissipation at light load. In such a case, connect R6 between the auxiliary winding and the 1S pin as shown in Fig.34. When R4 is 1kQ, R6 is several hundreds of kQ to 1MegQ. The smaller the R6 is, the lower the switching frequency at light load. However, negative voltage is applied to the IS pin due to R6 for some time while MOSFET is ON. Be aware that the negative voltage shall not be lower than absolute maximum rating, -0.3V. In addition, when switching frequency is set too low at light load, transformer or other apparatus may produce noise. (8) Prevention of malfunction caused by noise This IC is an analog IC, and noise applied to anyone of the pins may cause malfunction. If malfunction is detected, use the IC through referring to the following description and fully checking a power supply unit. In addition, arrange the capacitors connected to pins as close to the IC as possible and take great care of wiring, for effective noise suppression. (8-1) FB pin The FB pin sets the threshold voltage of the current comparator. Any noise applied to the FB pin may disturb output pulses. Usually the capacitor C5 is connected as shown in Fig.35 to suppress noise. (8-2) IS pin As described in 9.-(4) Blanking, this |C has a blanking function, and malfunction caused by a surge current produced at turn-on of the MOSFET is hard to occur. A malfunction, however, may occur when a surge current is excessively large or when any noise is externally applied at other than turn-off. In such a case, add a CR filter to the |S pin as shown in Fig.36. Choose a CR filter with resistance as small as possible (preferably 1000 or less) because the value of resistance affects the magnitude of slope. (See 10.-(6) Slope compensation.) FA5516 7/18 Fig34 Input power improvement circuit at light load FA5506 107/08 Fig.35 Prevention of malfunction caused by noise (FB pin) FA5516 (7/18 Fig36 Prevention of malfunction caused by noise (IS pin) 39 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message (8-3) VCC pin . Relatively large noise may occur at the VCC pin because a large current flows from the VCC pin at the instant of driving the MOSFET. If noise is excessively large, a malfunction may occur of the IC. Pay full attention to capacitance and characteristics of the capacitor between the VCC pin and GND to reduce noise as much as possible. (9) Prevention of malfunction caused by negative voltage applied to pins When a large negative voltage is applied to a pin, a FA5516 17/18 parasitic element in the IC may operate and cause a malfunction. Be sure that voltage applied to a pin shall not be -0.3V or less. = = Voltage oscillation generated at turn-off of the MOSFET Fig.37 Negative voltage prevention circuit may be applied to the OUT pin via the parasitic capacitance of the MOSFET, resulting in the negative voltage applied to the OUT pin. In such a case, connect a Shottky diode between each pin and GND. Forward voltage of the Shottky diode can suppress negative voltage at each pin. Use a Shottky diode with low forward voltage. Fig.37 shows an example of a circuit with a Shottky diode connected to the OUT pin. (10) Gate circuit configuration A resistor is generally inserted between the gate terminal of the MOSFET and the OUT pin of the IC for adjustment of switching speed, suppression of voltage FA5516 N78 oscillation at the gate terminal and other purposes. Sometimes, the drive currents for turning-on and -off must independently determined. Fig.38 Gate circuit (1) In such a case, connect the gate terminal of the MOSFET and OUT pin of the IC as shown in Fig.38 or Fig.39. Rg1 Rg2 Rg2 FA5516 ~ 17/118 In Fig.38, the driving current is limited by Rg1+Rg2 at turn-on and by only Rg2 at tumn-off Fig.39 Gate circuit (2) In Fig.39, the driving current is limited by only RG1 at turn-on and by parailel-connected Rg1 and Rg2 at turn-off. 30 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message (11) Loss calculation IC loss shall be determined to use the iC within its rating. Since it is hard to directly measure IC loss, an example of calculating approximate IC loss is given below. Total IC loss, Pd, is obtained by the following equation: Pd = Vec x (Iccop1 + Qg x fsw)+ Vy x IHrun Where Vcc is the supply voltage to the IC, Iccop1 is consumption current of the IC, Qg is total gate charge of the MOSFET, fsw is switching frequency, Vvi is VH pin voltage and IHrun is a current flowing into the VH pin when the IC operates. This equation gives an approximate value of Pd, which is normally a little greater than the actual loss. Take into consideration variation and temperature characteristics of each value (Example) When the VH pin is connected to half-wave rectification waveform at power supply of AC100V, average VH pin voltage is approximately 45V. Under this condition, let us suppose Vcc=18V and Qg=80nC at Tj=25C. When using FA5518, according to the specifications IHrun = 20pA(typ.), Iccop1 = 1.2mA(typ.) and fsw = 60kHz(typ.). Thus, typical IC loss Pd: Pd=18Vx(1.2mA+80nCx60kHz)+45Vx20pA =109mW 31 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message (Reference) Subharmonic oscillation and slope compensation In a peak-value-control current mode, when the converter operates in an inductor-current continuous mode and at duty cycle of 50% or more, the current may oscillate at an integral multiple of switching frequency. This oscillation is called subharmonic oscillation. Fig. 40 shows an example of inductor current waveform when a subharmonic oscillation occurs. It is found that ON and OFF periods vary while the peak 7 we ~~! i ~1 ee! value of an inductor current, switching cycle and current /\ *. /\ . *. /\ *. / slopes during ON and OFF periods remain unchanged. ] } } The harmonic oscillation may increase ripple voltage contained in the output voltage or cause an unusual! noise. oe ae i wi .! ' T a T T ' T 1 The subharmonic oscillation can be prevented by giving Fig.41 Inductor current with slope compensation _ a certain gradient to the threshold of the peak current as shown in Fig. 41. This is called slope compensation. IL Generally, the gradient of slope compensation required [7 ~~~-__ 7 . . ge gf fA :-Ke ' for preventing a subharmonic oscillation is given by the fT ! following relational expression: Py ae ' . =~ a Ld-Lu {AS :Lu . Ke > 3 #fAX:-Ld 8 Where L . Sf Lu : Gradient of an inductor current during the ON period Ld : Gradient of an inductor current during the OFF period Ke : Gradient of slope compensation ON OFF t Fig.42 Inductor current without slope compensation 39 Fuji Electric Device TechnologyFO e-Front runners FA5516/FA5517/FA5518 Quality is our message 11. Example of an application circuit 100 1000pF R210 C210 D201 2200pF c113 AC80 to sD11 tt seared 3.3yH ote . OOpF D5SBA60 3b 264V 1MQ 0.22uF 2200pF 74H THI C201 C203 L201 Oto 5A R101 C101 C103 14 Dt THI 1 a. ED elb9pe OO e L202 yy _ | c105 e RIF] om Bead 400V 33kQ 3300pF D202 220pF YG862C15*2 Sy Sy & c204 F414 R102 C104 D2 1000uF 3A IMO 2200pF ERA38-06 e FG 4.7ka c206 GND o_______ D3 R103 R207 EAR15-01 10k R110 |Feat oozzur | 2200 R201 2SK3687 200kn 214 0.1pF Pct R206 10k R202 R12 18kQ DS : 10k2 0.01 F $C902-02 R205 C205 Ic2 ter LMVv431 1 sr ERA22-02 2 7 D4 ge 11 6 NY | 4 5 q 3 > FA5518 C109 C110 Src 106 0.22uF 33yF Pct o0OpF T 4 Note The example of an application circuit is intended to be used only for reference and not to guarantee performance or characteristics. 33 Fuji Electric Device Technology