APU0066 PRELIMINARY 16 COM / 40 SEG Driver & Controller for Dot Matrix LCD FEATURES * * Internal Memory Display Character Pattern : - Character Generator ROM : 8320 bits - 5 x 7dots format : 192 kinds - Character Generator RAM : 512 bit - 5 x 10 dots format : 32 kinds - Display Data RAM : 80 x 8 bits for 80 digits (The special character pattern can be * Power Supply Voltage : 3V/5V 10% programmable by Character Generator RAM * Supply Voltage for Display : 0 ~ -5V (V5) directly.) * CMOS Process * 1/8 duty, 1/11 duty or 1/16 duty : Selectable * Programmable by Mask Option - 1/8 duty : 5 x 7dots format 1 line * Automatic Power on Reset Function - 1/11 duty: 5 x 10 dots format 1 line * It is Possible to Read Both Character Generator - 1/16 duty : 5 x 7dots format 2 line * A Customer Character Pattern Can be and Display Data RAM from MPU 80 QFP or Bare Chip Available APPLICATIONS GENERAL DESCRIPTION * The APU0066 is a dot matrix LCD driver & controller LSI that is fabricated by low power CMOS technology. Character Type Dot Matrix LCD Driver & Con -troller * Internal Driver :16 Common and 40 Segment Signal Output * Display Character Format : 5x 7 dots + Cursor, 5 x 10 dots + Cursor * Easy Interface with a 4-bit or 8-bit MPU ORDERING INFORMATION APU0066 R O M Code 001 : Standard 002 : Customer E Handling Code Package Type Q : QFP Y : Chip Package Type Handling Code TY : Tray ROM Code ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 1 www.anpec.com.tw APU0066 PRELIMINARY BLOCK DIAGRAM Power V1 Supply V2 for V3 LCD V4 Drive V5 Paralle / Serial Data Conversion Circuit 5 5 Character Generaotr ROM (CG ROM) 8320 bits Busy Flag Character Generaotr RAM (CG RAM) 512 bits Cursor Blink Control Circuit 4 D B 0 ~ DB 3 4 8 D B 4 ~ DB 7 8 Input Output Buffer R / W Segment Signal (S 1 ~ S 40 ) 8 Data Register (DR) 40-bit Shift Rregister 40 40-bit Latch Circuit 40 Segment Signal Driver 8 40 RS 7 E 7 8 8 Instruction Decoder (ID) Instruction Register (IR) Display Data RAM (DD RAM) 80 x 8 bits D 7 7 Address Counter (AC) 7 16 16 7 16-bit Shift Rregister OSC1 Timing Generation Circuit OSC2 Common Signal Driver Common Signal (C 1 ~ C 16 ) CLK1 CLK2 M VDD GND Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 2 www.anpec.com.tw APU0066 PRELIMINARY ABSOLUTE MAXIMUM RATINGSTA = 25C S ym b ol V DD V LC D V IN PD T OPR T STG P a r a m e te r O p e ra tin g Vo lta g e D rive r S u p p ly Vo lta g e In p u t Vo lta g e P o w e r D is s ip a tio n O p e ra tin g Tem p e ra tu re S to ra g e Tem p e ra tu re R a n g e R a tin g U n it -0 .3 ~ + 7 V D D - 1 3 .5 ~ V D D + 0 .3 -0 .3 ~ V D D + 0.3 500 -2 0 to + 7 5 -3 0 to + 8 5 V V V mW C C Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5 ) ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 3V 10%, VSS = 0V, TA = -30 ~ 85C) S ym bol Param eter V DD Operating Voltage I DD1 Operating Current (1) I DD2 V IH1 V IL1 V IH2 V IL2 V O H1 V LH1 V O H2 V LH2 VD CO M VD SEG Input Voltage 1 Input Voltage 2 Output Voltage 1 Output Voltage 2 Voltage Drop (2) I LKG Input Leakage Current I IL Input Low Current Test Conditions Ceram ic Resonator F O SC = 250KHz Resistor Oscillation External Clock Operation F O SC = 270KHz High Low High Low I O H = -0.1 m A High I O L = 0.1m A Low High I O = -40A Low I O = 40A COM I O = 0.05m A SEG V IN = 0 or V DD M in. APU0066 Typ. M ax. 2.7 3 3.3 0.3 0.5 0.17 0.3 1.9 -0.3 0.7V DD 2.0 0.8V DD -1 V DD 0.4 V DD 0.2V DD 0.4 0.2V DD 1 1.5 1 V mA E, DB 0 - DB 7 R/W, RS OSC 1 CLK1, CLK2. M, D C 1 ~ C 16 S 1 ~ S 40 -10 -50 -120 F EC 125 250 350 Duty Duty 45 50 55 % Rise Tim e 0.2 s V LCD1 V LCD2 Internal Clock Frequency (3) LCD Driving Voltage (4) OSC 1 0.2 s 270 350 KHz OSC 1 , OSC 2 1/5 bias 3 10 1/4 bias 3 10 V V1 - V5 Rf = 75K 2% V DD - V 5 KHz 190 Fall Tim e TF F O SC E RS, R/W, DB 0 - DB 7 A Frequency(3) External Clock DB 0 - DB 7 V V DD = 3V (test pull up R) TR Applicable Pin Unit Note: 1 : The supply current value from VDD when the power condition is as follows VDD = 5V, VSS = 0V, V = -2V (when VDD = 5V) 5 VDD = 3V, VSS = 0V, V = -2V (when VDD = 3V) 5 2 : The voltage drop from LCD bias terminals VDD, V , V and V to each common terminal (C ~ C ). And 1 4 5 1 16 also the voltage drop from LCD bias terminals VDD, V , V and V to each segment terminal (S ~ S ). 2 3 5 1 80 3 and 4 : Refer to oscillator circuit and input the voltage listed in the table below to V ~ V . 1 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 3 5 www.anpec.com.tw APU0066 PRELIMINARY DC Characteristics (VDD = 5V 10%, VSS = 0V, TA = -20 ~ 75C) Symbol VDD Parameter Operating Current (1) IDD2 ILKG IIL Min. Typ. Max. 4.5 5.5 Ceramic Resonator FOSC = 250KHz Resistor Oscillation External Clock Operation FOSC = 270KHz High Low High Low IOH = -0.205mA High IOL = 1.2mA Low High IO = -40A Low IO = 40A COM IO = 0.1mA SEG 0.55 0.8 0.35 0.6 2.2 -0.3 VDD - 1 -0.2 2.4 0.9VDD VDD 0.6 VDD 1 0.4 0.1VDD 1 1 1 Operating Voltage IDD1 VIH1 VIL1 VIH2 VIL2 VOH1 V LH1 VOH2 V LH2 VDCOM VDSEG APU0066 Test Conditions Input Voltage 1 Input Voltage 2 Output Voltage 1 Output Voltage 2 Voltage Drop (2) Input Leakage Current Input Low Current VIN = 0 or VDD -1 VDD = 5V (test pull up R) -50 -125 -250 Unit Applicable Pin V mA E, DB0 - DB7 R/W, RS OSC1 V CLK1, CLK2. M, D C1 ~ C16 S1 ~ S40 A FEC Frequency (3) 125 250 350 Duty Duty 45 50 55 % Rise Time 0.2 s External Clock TR VLCD1 V LCD2 VDD - V5 KHz OSC1 0.2 s 270 350 KHz OSC1, OSC2 1/5 bias 4.6 10 1/4 bias 3 10 V V 1 - V5 Internal Clock Frequency (3) Rf = 91K 2% LCD Driving Voltage (4) E RS, R/W, DB0 - DB7 190 Fall Time TF FOSC1 DB0 - DB7 Note : 1 : Applies to the current value flown in terminal VDD when power is input as follows; VDD = 5V, GND = 0V, V1 = 3.4V, V2 =1.8V, V3 = 0.2V, V4 = 1.4V and V5 = -3V. 2 : Applied to the voltage drop occurring from terminals VDD , V1, V4 and V5 to each common terminal (C1 - C16) when 0.1mA is flown in or out to and from all COM and SEG terminals, and also to voltage drop occurring from terminals VDD ,V2, V3 and V5 to each SEG terminal (S1 ~ S40). When the output level is at VDD , V1, V2 level , 0.1mA is flown out, while 0.1mA flow in when the output level is at V3, V4 or V5 level. This occurs when 5V or -5V is input to VDD, V1 and V3 or to V2, V4, and V5 respectively. 3 : Oscillator Circuit Resistor Circuit O S C1 External Clock Circuit O S C1 O S C2 Rf Frequency Input O S C2 Open R f : 91K 2% Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 4 www.anpec.com.tw APU0066 PRELIMINARY 4 : Input the voltage listed in the table below to V1 - V5 Duty Bias Power Supply V1 V2 V3 V4 V5 1/8, 1/11 1/4 1/16 1/5 VDD - VLCD / 4 VDD - VLCD / 2 VDD - VLCD / 2 VDD - 3VLCD / 4 VDD - VLCD VDD - VLCD / 5 VDD - 2VLCD / 5 VDD - 3VLCD / 5 VDD - 4VLCD / 5 VDD - VLCD VLCD is the LCD driving voltage, refer to the initial set of the instruction code. AC Characteristics (VDD = 5V 10%, VSS= 0V, TA = -20 ~ +75C) 1. Write mode Symbol TC TR TF TW TSU1 TH1 TSU2 TH2 RS Characteristic E Cycle Time E Rise Time E Fall Time E Pulse Width (High, Low) R/W and RS Set-up Time R/W and RS Hold Time Data Set-up Time Data Hold Time Min. 500 220 40 10 60 10 V IH1 V IH 1 V IL1 V IL1 Max. 25 25 - Unit ns ns ns ns ns ns ns ns Test Pin E E E E R/W, RS R/W,RS DB0 ~ DB7 DB0 ~ DB7 TH1 T S U1 R/W Typ. - V IL1 V IL1 TW E V IH 1 V IL1 T H1 TF V IH1 V IL1 T SU2 V IL1 T H2 TR V IH 1 V IH 1 Vaild Data D B 0 ~ DB 7 V IL1 V IL1 TC Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 5 www.anpec.com.tw APU0066 PRELIMINARY 2. Read mode Symbol TC TR TF TW TSU TH TD TDH RS Characteristic E Cycle Time E Rise Time E Fall Time E Pulse Width (High, Low) R/W and RS Set-up Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Min. Typ. Max. Unit Test Pin 500 220 40 10 20 - 25 25 120 - ns ns ns ns ns ns ns ns E E E E R/W, RS R/W,RS DB0 ~ DB7 DB0 ~ DB7 - V IH 1 V IH 1 V IL1 V IL 1 TH TSU V IL 1 R/W TW V IH 1 E T H1 TF V IL1 V IL1 V IL1 TR T DH TD V IH 1 V IH 1 D B 0 ~ D B7 Vaild Data V IL1 V IL1 TC 3. Interface mode with APU0065, APU0063 Symbol TWCKH TWCKL TSU TDH TCSU TDM Characteristic Clock Pulse Width High Clock Pulse Width Low Data Set-up Time Data Hold Time Clock Set-up Time M Delay Time Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 Min. 800 800 300 300 500 -1000 6 Typ. - Max. 1000 Unit ns ns ns ns ns ns Test Pin CKL CLK D D CLK M www.anpec.com.tw APU0066 PRELIMINARY 0.9 V D D 0.9 V D D C L K1 TWCKH T WCKH T CSU C L K2 0.9 V D D 0.9 V D D 0.1 V D D 0.1 V D D T CSU 0.1 V D D T WCKL D 0.9 V D D 0.9 V D D 0.1V D D 0.1V D D T SU M T DH 0.9 V D D T DM C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 DB7 DB6 DB5 DB4 DB3 DB2 52 51 50 49 48 47 46 45 44 43 42 41 34 M 33 V DD 32 CLK 2 31 CLK 1 30 V5 29 V4 28 D V3 S 25 27 S 33 V2 S 24 26 RS S 30 S 29 S 28 S 27 S 26 S21 S20 S19 S18 S17 S18 S15 S14 S13 S12 S11 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 7 13 14 15 16 17 18 19 20 21 22 23 24 OSC1 12 GND 11 S1 10 S2 9 S3 8 S4 7 S5 6 S6 5 S7 4 S8 3 S9 2 S10 1 S22 S 23 APU0066 25 S 31 80 S 32 71 R/W S 34 72 S 35 73 E 74 S 36 75 DB0 76 40 C13 53 39 C14 54 38 C15 55 37 C16 56 36 S40 57 35 S39 58 DB1 77 65 59 67 60 68 61 69 62 70 63 78 S 37 64 79 S 38 66 PIN CONFIGURATION _80 QFP TOP VIEW V1 OSC 2 www.anpec.com.tw PRELIMINARY APU0066 CHIP PAD ARRANGEMENT 60 14 59 13 58 12 57 11 C 15 C 61 C 16 C 62 C 40 C 63 S 39 S 64 C 10 5 50 4 49 3 48 2 47 1 C 51 C 6 C 52 C 7 C 53 C 8 C 54 C 9 C 55 DB 7 DB 45 6 DB 44 5 DB 43 4 DB 42 3 D B2 41 D B0 46 39 E 56 66 38 R/W D B1 S 37 67 37 RS 40 S 36 68 36 D 65 S 35 69 35 M S 38 S 34 70 34 APU0066 S 33 71 VDD S 32 33 (0,0) C L K2 72 32 S 31 73 V5 S 30 30 V4 C L K1 29 V3 31 28 V2 74 77 27 V1 S 29 78 26 O S C2 75 Chip size : 2670 x 2192.9 m Pad size : 80 x 80 m 79 25 1 S 21 2 S 20 3 S 19 4 S 18 5 S 17 6 S 16 7 S 15 8 S 14 9 S 13 10 S 12 11 S 11 12 S 10 13 S9 14 S8 15 S7 16 S6 17 S5 18 S4 19 S3 20 S2 21 S1 22 GND 23 O S C1 24 76 80 S 28 S 27 S 26 S 25 S 24 S 23 S 22 www.anpec.com.tw 8 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 APU0066 PRELIMINARY PAD LOCATION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN NAME S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CLK1 CLK2 VDD M D RS R/W E DB0 DB1 X -1,265.00 -1,140.00 -1,015.00 -890.00 -770.00 -650.00 -550.00 -450.00 -350.00 -250.00 -150.00 -50.00 50.00 150.00 250.00 350.00 450.00 550.00 650.00 770.00 890.00 1,015.00 1,140.00 1,265.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 1,270.00 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 Y -1,025.15 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,031.45 -1,024.55 -811.95 -691.95 -571.95 -451.95 -351.95 -251.95 -151.95 -51.95 48.05 148.05 248.05 348.05 448.05 568.05 688.05 808.05 PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 9 PIN NAME DB2 DB3 DB4 DB5 DB6 DB7 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 X 1,265.00 1,140.00 1,015.00 890.00 770.00 650.00 550.00 450.00 350.00 250.00 150.00 50.00 -50.00 -150.00 -250.00 -350.00 -450.00 -550.00 -650.00 -770.00 -890.00 -1,015.00 -1,140.00 -1,265.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 -1,270.00 Y 1,022.65 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,031.45 1,021.20 808.05 688.05 568.05 448.05 348.05 248.05 148.05 48.05 -51.95 -151.95 -251.95 -351.95 -451.95 -571.95 -691.95 -811.95 www.anpec.com.tw APU0066 PRELIMINARY PIN DESCRIPTION-QFP80 Pin (No) VDD (33) VSS (GND) (23) Input / Output Power V1 - V5 (26 - 30) Name Description Operating Voltage For logical circuit (+5V 10%) 0V (GND) Vegetative Supply Voltage Bias voltage level for LCD driving Interface Power Supply S1 - S40 (22 - 1, 80 - 63) Output Segment Output Segment signal output for LCD driving LCD C1 - C16 (47 - 62) Output Common Output Common signal output for LCD driving LCD OSC1, OSC2 (24) (25) Input (OSC1) Output (OSC2) CLK1 (31) CLK2 (32) Output M (34) D (35) E (38) R / W (37) Both pins connected to Rf resistor or ceramic resonator for internal oscillator circuit. In case of Oscillator external frequency use only, the frequency is input to (OSC1) terminal. Clock output terminal for the serially transferred Data latch clock data to be latched to the driver. Clock output terminal used when D terminal data Data shift clock output shifts the inside of the driver. Alternated signal for The alternating signal to convert LCD drive waveform to AC LCD driver output Character pattern data, which is corresponding, to each common signal, is supplied to driver serially. Display data interface High Selection Low Non selection Enable Start enable signal to read or write the data Read / Write RS (36) Register select DB0 - DB7 (39 - 46) Input / Output Data interface APU0065 or APU0063 R/W signal input is used to select the read/write mode High Low Register selection input Input Resistor or Ceramic Resonator Read mode Write mode MPU High Data register (for read and write) Instruction register (for write), Busy Low flag, address counter (for read) Used for data transfer between the MPU and APU0066. These terminals are for data bus with bi-directional three-state. Initial 4 bit (DB0 - DB3) are not used during 4 bit operation (DB7 can be used as a busy flag) Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 10 www.anpec.com.tw APU0066 PRELIMINARY INTERNAL LOGIC of INPUT / OUTPUT TERMINAL Input / Output Applicable Pin Logic Diagram VDO E No Pull Up Input VDO VDO RS, R / W With Pull Up VDO C L K 1 , CLK 2 , M, D Input VDO VDO VDO D B 0 ~ DB 7 Input / Output Data Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 11 www.anpec.com.tw APU0066 PRELIMINARY CONTROL and DISPLAY COMMAND Command RS Execution R/ Time DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W (fosc=250KHz) L L L L L L L L H 1.64ms Display Clear L Return Home L L L L L L L L Entry Mode Set L L L L L L L H Display ON / OFF L L L L L L H D C B 40s Shift L L L L L H S/ C R/ L X X 40s Set Function L L L L H DL N F X X 40s Set CG RAM Address L L L CG RAM address H (corresponds to cursor address) L L H DD RAM address Set DD RAM Address Write data H L Read data H H Read Data Read Busy Flag & Address L H H X I / D SH 40s 46s 46s Address counter used for both DD & CG RAM address Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 40s 40s Writ Data BF 1.64ms 12 0s Remark Cursor move to first digit I / D : set cursor Move direction H : Increase L : Decrease SH : Specifies shift of display H : display is Shifted L : display is not Shifted Display H : Display on L : display off Cursor H : Cursor on L : Cursor off Blinking H : Blinking on L : Blinking off SC : H : Display shift L : Cursor move R/L : H : Right shift L : Left shift DL : H : 8 bits interface L : 4 bits interface N: H : 2 line display L : 1 line display F: H : 5 x 10 dots L : 5 x 7 dots CG RAM data is sent and received after this setting DD RAM data is sent and received after this setting Write data into DD or CG RAM Read data from DD or CG RAM BF : H : Busy L : Ready Reads BF indication internal operating is being performed. Reads address counter contents www.anpec.com.tw APU0066 PRELIMINARY APPLICATION INFORMATION ACCORDING to LCD PANEL ~~ ~~ ~~ ~ ~~ ~~ ~ ~~ ~~ 1. LCD Panel : 8 character x 1 line character format ; 5 x 7 dots + 1 cursor line (1/4 bias, 1/8 duty) ........... C1 C8 APU0066 ............................................ S1 S 40 2. LCD Panel : 8 character x 1 line character format ; 5 x 10 dots + 1 cursor line (1/4 bias, 1/8 duty) ............... C1 APU0066 C 11 ................ S1 ........................................................ S 40 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 13 www.anpec.com.tw APU0066 PRELIMINARY 3. LCD Panel : 8 character x 2 line character format ; 5 x 7 dots + 1 cursor line (1/5 bias, 1/16 duty) ...... C1 C8 ....... C9 ................................ APU0066 C 16 S1 ...................................... S 40 4. LCD Panel : 16 character x 1 line character format ; 5 x 7 dots + 1 cursor line (1/5 bias, 1/16 duty) ...... C1 C8 ................. ........ APU0066 ................. S1 S 40 ........ C9 C 16 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 14 www.anpec.com.tw APU0066 PRELIMINARY 5. LCD Panel : 4 character x 2 line character format ; 5 x 7 dots + 1 cursor line (1/4 bias, 1/8 duty) ........ S1 S 20 ............ ........ C1 APU0066 C 8 ........ S 21 ............ S 40 BIAS VOLTAGE DIVIDE CIRCUIT APU0066 APU0066 VDD V1 V2 V3 V4 VDD V5 V2 V1 V3 V5 V4 V D D (+5V) V D D (+5V) R R R R R (-5V) or GND Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 R R R R (-5V) or GND 15 www.anpec.com.tw APU0066 PRELIMINARY STANDARD CHARACTER PATTERN Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 16 www.anpec.com.tw