M24256-BF M24256-BR M24256-BW M24256-DR 256 Kbit serial IC bus EEPROM with three Chip Enable lines Features Compatible with all I2C bus modes: - 1 MHz Fast-mode Plus - 400 kHz Fast mode - 100 kHz Standard mode Memory array: - 256 Kb (32 Kbytes) of EEPROM - Page size: 64 bytes M24xxx- DR: additional Write lockable Page (Identification page) Single supply voltage: - 1.7 V to 5.5 V - 1.8 V to 5.5 V - 2.5 V to 5.5 V SO8 (MN) 150 mils width TSSOP8 (DW) Noise suppression - Schmitt trigger inputs - Input noise filter Write - Byte write within 5 ms - Page write within 5 ms Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-up protection More than 1 million write cycles More than 40-year data retention Packages - ECOPACK2(R) (RoHS compliant and halogen-free) July 2011 WLCSP (CS) Doc ID 6757 Rev 24 UFDFPN8 (MB) 2 x 3 mm (MLP) 1/41 www.st.com 1 Contents M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 3 2/41 2.6.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 Write Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 Lock Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 16 3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.17 Reading the Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . 20 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents 3.18 Reading the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 6757 Rev 24 3/41 List of tables M24256-BF, M24256-BR, M24256-BW, M24256-DR List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. 4/41 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device select code (for memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (voltage range W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (voltage range W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 31 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 6757 Rev 24 5/41 Description 1 M24256-BF, M24256-BR, M24256-BW, M24256-DR Description The M24256-Bx devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 32 K x 8 bits. The M24256-DR is also an I2C-compatible EEPROM organized as 32 K x 8 bits, but it offers an additional page, named the Identification Page (64 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. Figure 1. Logic diagram 6## % % 3$! -XXX 3#, 7# 633 Table 1. !)G Signal names Signal name Function Direction E0, E1, E2 Chip Enable Inputs SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground Figure 2. Package connections E0 E1 E2 VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI04035e 1. See Package mechanical data section for package dimensions, and how to identify pin-1. 6/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 3. Description WLCSP connections (top view, marking side, with balls on the underside) VCC E1 E0 WC E2 SDA SCL VSS ai14712 Caution: As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UVlight. Doc ID 6757 Rev 24 7/41 Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial Data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code. When not connected (left floating), these inputs are read as Low (0,0,0). Figure 4. Device select code VCC VCC M24xxx M24xxx Ei Ei VSS VSS Ai12806 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 2.5 Signal description VSS ground VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions VCC has to rise continuously from 0 V up to VCC(min) (see Table 7, Table 8 and Table 9), and the rise time must not vary faster than 1 V/s. 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power on reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches an internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage defined in Table 7, Table 8 and Table 9. When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power on reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (where VCC decreases continuously), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal Write cycle in progress). Doc ID 6757 Rev 24 9/41 Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) Figure 5. Bus line pull-up resistor (k ) 100 10 4 k When tLOW = 1.3 s (min value for fC = 400 kHz), the Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. R bu s x C bu s = Here Rbus x Cbus = 120 ns 40 VCC Rbus 0n s IC bus master SCL M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Bus line pull-up resistor (k ) Figure 6. I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) 100 VCC When tLOW = 700 ns (max possible value for fC = 1 MHz), the Rbus x Cbus time constant must be below the 270 ns time constant line represented on the left. R bus x C bus = 270 10 5 ns R bus x C bus = 10 0 ns Here, Rbus x Cbus = 150 ns When tLOW = 400 ns (min value for fC = 1 MHz), the Rbus x Cbus time constant must be below the 100 ns time constant line represented on the left. Rbus IC bus master SCL M24xxx SDA Cbus 1 10 100 30 Bus line capacitor (pF) ai14795d 10/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 7. Signal description I2C bus protocol SCL SDA SDA Input Start condition SCL 1 SDA MSB 2 SDA Change Stop condition 3 7 8 9 ACK Start condition SCL 1 SDA MSB 2 3 7 8 9 ACK Stop condition AI00792c Table 2. b15 Table 3. b7 Most significant address byte b14 b13 b12 b11 b10 b9 b8 b3 b2 b1 b0 Least significant address byte b6 b5 b4 Doc ID 6757 Rev 24 11/41 Device operation 3 M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always slave in all communications. 3.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 3.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 3.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. 3.4 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. 12/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.5 Device operation Addressing the memory array To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 4 (on Serial Data (SDA), most significant bit first). The 4-bit device type identifier 1010b selects the memory array, the 4-bit device type identifier 1011b selects the Identification page. A device select code handling a value different than 1010b or 1011b is not acknowledged by the device. Table 4. Device select code (for memory array) Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 5. Operating modes RW bit WC(1) Bytes 1 X 1 Random Address Read 0 X 1 X Sequential Read 1 X 1 Byte Write 0 VIL 1 Start, device select, RW = 0 Page Write 0 VIL 64 Start, device select, RW = 0 Mode Current Address Read Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, Address 1 re-Start, device select, RW = 1 Similar to Current or Random Address Read 1. X = VIH or VIL. Doc ID 6757 Rev 24 13/41 Device operation Figure 8. M24256-BF, M24256-BR, M24256-BW, M24256-DR Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte addr ACK Byte addr NO ACK Data in Stop Dev sel Start Byte Write ACK R/W WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr NO ACK Data in 1 Data in 2 R/W WC (cont'd) NO ACK Data in N Stop Page Write (cont'd) NO ACK AI01120d 14/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.6 Device operation Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (Table 2) is sent first, followed by the least significant byte (Table 3). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after a data byte Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 8. 3.7 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9. 3.8 Page Write (memory array) The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same `row' in the memory: that is, the most significant memory address bits (b15-b6) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Doc ID 6757 Rev 24 15/41 Device operation 3.9 M24256-BF, M24256-BR, M24256-BW, M24256-DR Write Identification Page (M24256-D only) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The identification page is written by issuing a Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: Device Type Identifier = 1011b MSB address bits A15/A6 are don't care except for address bit A10 which must be `0'. LSB address bits A5/A0 define the byte address inside the identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 3.10 Lock Identification Page (M24256-D only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: Device Type Identifier = 1011b Address bit A10 must be `1'; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care. If the Identification Page is locked, the data bytes transferred during the ID Write instruction are not acknowledged (NoAck). 3.11 ECC (error correction code) and write cycling The M24256-Bx and M24256-D devices offer an ECC (error correction code) logic which compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write data by word (4 bytes) at address 4*N (where N is an integer) in order to benefit from the larger amount of Write cycles. The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. 16/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 9. Device operation Write mode sequences with WC = 0 (data write enabled) WC ACK ACK Byte addr Byte addr ACK Data in Stop Dev sel Start Byte Write ACK R/W WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr ACK Data in 1 Data in 2 R/W WC (cont'd) ACK Data in N Stop Page Write (cont'd) ACK AI01106d Doc ID 6757 Rev 24 17/41 Device operation M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 10. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next operation is addressing the memory YES Send Address and Receive ACK ReStart NO Stop Start condition YES Data for the Write operation Device select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d 3.12 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in tables17 and 18, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10, is: 18/41 Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.13 Device operation Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address. Figure 11. Read mode sequences ACK Data out Stop Start Dev sel R/W ACK Random Address Read Byte addr Dev sel * ACK NO ACK Data out N R/W ACK ACK Byte addr ACK Byte addr ACK Dev sel * Start Start Dev sel * R/W ACK Data out R/W ACK Data out 1 NO ACK Stop Start Dev sel Sequential Random Read ACK Byte addr R/W ACK Sequential Current Read ACK Start Start Dev sel * ACK Stop Current Address Read NO ACK ACK Data out 1 R/W NO ACK Stop Data out N AI01105d 3.14 Random Address Read (in memory array) A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Doc ID 6757 Rev 24 19/41 Device operation 3.15 M24256-BF, M24256-BR, M24256-BW, M24256-DR Current Address Read (in memory array) For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11, without acknowledging the byte. 3.16 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 11. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. 3.17 Reading the Identification Page (M24256-D only) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing a Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits A17/A6 are don't care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data will be read (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes). 20/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.18 Device operation Reading the lock status (M24256-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device will return an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that: 3.19 Start: the truncated command is not executed because the Start condition resets the device internal logic, Stop: the device is then set back into Standby mode by the Stop condition. Acknowledge in Read mode For all Read instructions, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. Doc ID 6757 Rev 24 21/41 Initial delivery state 4 M24256-BF, M24256-BR, M24256-BW, M24256-DR Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max. Unit Ambient Temperature with power applied -40 130 C Storage temperature -65 150 C Lead temperature during soldering See note (1) C VIO Input or output range -0.50 6.5 V VCC Supply voltage -0.50 6.5 V IOL DC output current (SDA = 0) 5 mA 3000 V VESD Electrostatic pulse voltage (Human Body Model) (2) ECOPACK(R) 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST 7191395 specification, and the European directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS) 2002/95/EC. 2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 ) 22/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 6 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating conditions (voltage range W) Symbol VCC TA Table 8. Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature (device grade 6) -40 85 C Ambient operating temperature (device grade 3) -40 125 C Operating conditions (voltage range R) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 C Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature -40 85 C Operating conditions (voltage range F) Symbol VCC TA Table 10. Parameter AC test measurement conditions Symbol Cbus Parameter Min. Load capacitance Max. 100 SCL input rise/fall time SDA input fall time Unit pF 50 ns Input levels 0.2VCC to 0.8VCC V Input and output timing reference levels 0.3VCC to 0.7VCC V Figure 12. AC test measurement I/O waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC 0.2VCC AI00825B Doc ID 6757 Rev 24 23/41 DC and AC parameters Table 11. Symbol M24256-BF, M24256-BR, M24256-BW, M24256-DR Input parameters Parameter(1) Test condition Min. Max. Unit CIN Input capacitance (SDA) 8 pF CIN Input capacitance (other pins) 6 pF ZL(2) Input impedance (E2, E1, E0, WC) VIN < 0.3VCC 30 k ZH(2) Input impedance (E2, E1, E0, WC) VIN > 0.7VCC 500 k 1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). Table 12. Symbol Ncycle Note: Memory cell characteristics Parameter Endurance Test condition Min. TA = 25C, 1.8V < Vcc < 5.5V Max. Unit - Write cycle 1,000,000 This parameter is not tested but established by characterization and qualification. To estimate endurance in a specific application, please refer to AN2014. Table 13. Symbol DC characteristics (voltage range W, device grade 3) Test conditions (in addition to Parameter those in Table 7 and Table 10) ILI VIN = VSS or VCC Input leakage current (SCL, SDA, E0, E1, E2) device in Standby mode ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ICC Supply current (Read) fc = 400 kHz ICC0 Supply current (Write) During tW Device not selected or VCC (2), Min. VIN = VSS Max. Unit 2 A 2 A 2 mA 5(1) mA 5 A ICC1 Standby supply current VIL Input low voltage (SCL, SDA, WC) -0.45 0.3 VCC V Input high voltage (SCL, SDA) 0.7VCC 6.5 V Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V 0.4 V VIH VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 24/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 14. Symbol ILI ILO ICC ICC0 ICC1 VIL VIH VOL DC and AC parameters DC characteristics (voltage range W, device grade 6) Parameter Test conditions (see Table 7 and Table 10) Min. Max. Unit 2 A 2 A VCC = 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) 1 mA VCC = 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) 2 mA 2.5 V < VCC < 5.5 V, fc = 1 MHz(1) (rise/fall time < 50 ns) 2.5 mA During tW, 2.5 V < VCC < 5.5 V 2(2) mA Device not selected(3), VIN = VSS or VCC, VCC = 2.5 V 2 A Device not selected(3), VIN = VSS or VCC, VCC = 5.5 V 3 A V Input leakage VIN = VSS or VCC current (SCL, SDA, E0, E1, device in Standby mode E2) Output leakage current Supply current (Read) Supply current (Write) Standby supply current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC Input low voltage (SCL, SDA, WC) -0.45 0.3VCC Input high voltage (SCL, SDA) 0.7VCC 6.5 Input high voltage (WC, E0, E1, E2) 0.7VCC VCC+0.6 V Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 0.4 V 1. Only for devices operating at fC max = 1 MHz (see Table 18). 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). Doc ID 6757 Rev 24 25/41 DC and AC parameters Table 15. Symbol M24256-BF, M24256-BR, M24256-BW, M24256-DR DC characteristics (voltage range R) Test conditions(1) (in addition to those in Table 8 and Table 10) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode 2 A ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2 A VCC = 1.8 V, fc= 400 kHz 0.8 mA fc= 1 MHz 2.5 mA During tW, 1.8 V < VCC < 2.5 V 2(2) mA 1 A ICC ICC0 Supply current (Read) Supply current (Write) selected(3), ICC1 Standby supply current Device not VIN = VSS or VCC, VCC = 1.8 V VIL Input low voltage (SCL, SDA, WC) 1.8 V VCC < 2.5 V -0.45 0.25 VCC V Input high voltage (SCL, SDA) 1.8 V VCC < 2.5 V 0.75VCC 6.5 V Input high voltage (WC, E0, E1, E2) 1.8 V VCC < 2.5 V 0.75VCC VCC+0.6 V Output low voltage IOL = 1 mA, VCC = 1.8 V 0.2 V VIH VOL 1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 C < TA < +85 C, please refer to Table 14 instead of this table. 2. Characterized value, not tested in production 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 26/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 16. Symbol DC and AC parameters DC characteristics (voltage range F) Parameter Test conditions (in addition to those in tables 9 and 10)(1) Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode 2 A ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2 A VCC = 1.7 V, fc= 400 kHz 0.8 mA fc= 1 MHz 2.5 mA During tW, 1.7 V < VCC < 2.5 V 2(2) mA 1 A ICC ICC0 ICC1 VIL VIH VOL Supply current (Read) Supply current (Write) Standby supply current Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA) Input high voltage (WC, E0, E1, E2) Output low voltage selected(3), Device not VIN = VSS or VCC, VCC = 1.7 V 1.7 V VCC < 2.5 V -0.45 0.25 VCC V 1.7 V VCC < 2.5 V 0.75VCC 6.5 V 1.7 V VCC < 2.5 V 0.75VCC VCC+0.6 V 0.2 V IOL = 1 mA, VCC = 1.7 V 1. If the application uses the voltage range F device with 2.5 V < Vcc < 5.5 V and -40 C < TA < +85 C, please refer to Table 14 instead of this table. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). Doc ID 6757 Rev 24 27/41 DC and AC parameters Table 17. M24256-BF, M24256-BR, M24256-BW, M24256-DR 400 kHz AC characteristics Test conditions specified in tables 7, 8, 9 and 10 Symbol Alt. Parameter Min.(1) Max.(1) Unit fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 600 ns tCLCH tLOW Clock pulse width low 1300 ns SDA (out) fall time 20(3) 120 ns tQL1QL2(2) tF 400 kHz tXH1XH2 tR Input signal rise time (4) (4) ns tXL1XL2 tF Input signal fall time (4) (4) ns tDXCX tSU:DAT Data in set up time 100 ns tCLDX tHD:DAT Data in hold time 0 ns tCLQX(5) tDH Data out hold time 100 ns tCLQV (6) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 600 ns tDLCL tHD:STA Start condition hold time 600 ns tCHDH tSU:STO Stop condition set up time 600 ns tDHDL tBUF Time between Stop condition and next Start condition 1300 ns tW tWR Write time 5 ms Pulse width ignored (input filter on SCL and SDA) 80 ns tNS(7) 900 ns 1. All values are referred to VIL(max) and VIH(min). 2. Characterized only, not tested in production. 3. With Cbus = 10 pF. 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC-bus specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 5. The IC-bus specification does not define a min value of the data hold time (tHD;DAT). The min value of tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the falling edge SCL. 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus x Cbus time constant is within the values specified in Figure 5. 7. Characterized only, not tested in production. 28/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 18. DC and AC parameters 1 MHz AC characteristics(1) Test conditions specified in tables 7, 8, 9 and 10 Symbol Alt. Parameter Min.(2) Max.(2) Unit 0 1 MHz - ns fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 300 tCLCH tLOW Clock pulse width low 400 - ns (3) ns tXH1XH2 tR Input signal rise time (3) tXL1XL2 tF Input signal fall time (3) (3) ns tQL1QL2(4) tF SDA (out) fall time(5) 20 120 ns tDXCX tSU:DAT Data in setup time 80 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(6) tDH Data out hold time 50 - ns tCLQV(7) tAA Clock low to next data valid (access time) 500 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tW tWR Write time - 5 ms Pulse width ignored (input filter on SCL and SDA) - 50 ns tNS(4) 1. Only new devices identified by the process letter K are qualified at 1 MHz (refer to TN0440 for more). 2. All values are referred to VIL(max) and VIH(min). 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC-bus specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 4. Characterized only, not tested in production. 5. With CL = 10 pF. 6. The IC-bus specification does not define a min value of the data hold time (tHD;DAT). The min value of tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the falling edge SCL. 7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus x Cbus time constant is within the values specified in Figure 6. Doc ID 6757 Rev 24 29/41 DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 13. AC waveforms T8,8, T8(8( T#(#, T#,#( 3#, T$,#, T8,8, 3$! )N T#($, T#,$8 T8(8( 3TART CONDITION 3$! )NPUT 3$! T$8#( #HANGE T#($( T$($, 3TART 3TOP CONDITION CONDITION 3#, 3$! )N T7 T#($( T#($, 3TOP CONDITION 7RITE CYCLE 3TART CONDITION T#(#, 3#, T#,16 3$! /UT T#,18 $ATA VALID T1,1, $ATA VALID !)F 30/41 Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. SO8N - 8-lead plastic small outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A 1. Drawing is not to scale. Table 19. SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.75 Max 0.0689 A1 0.1 A2 1.25 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.25 0.0039 0.0098 0.0492 0.1 0.0039 D 4.9 4.8 5 0.1929 0.1890 0.1969 E 6 5.8 6.2 0.2362 0.2283 0.2441 E1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h 0.25 0.5 0.0098 0.0197 k 0 8 0 8 L 0.4 1.27 0.0157 0.05 L1 1.04 0.0409 1. Values in inches are converted from mm and rounded to four decimal digits. Doc ID 6757 Rev 24 31/41 Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 15. TSSOP8 - 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 20. TSSOP8 - 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min A Max 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0 8 0.0394 0 N 8 8 1. Values in inches are converted from mm and rounded to four decimal digits. 32/41 Min 1.200 A1 A2 Typ Doc ID 6757 Rev 24 8 M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data Figure 16. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3. The circle in the top view of the package indicates the position of pin 1. Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.55 0.45 0.6 0.0217 0.0177 0.0236 A1 0.02 0 0.05 0.0008 0 0.002 b 0.25 0.2 0.3 0.0098 0.0079 0.0118 D 2 1.9 2.1 0.0787 0.0748 0.0827 D2 1.6 1.5 1.7 0.063 0.0591 0.0669 E 3 2.9 3.1 0.1181 0.1142 0.122 E2 0.2 0.1 0.3 0.0079 0.0039 0.0118 e 0.5 - - 0.0197 - - L 0.45 0.4 0.5 0.0177 0.0157 0.0197 L1 L3 ddd (2) 0.15 0.0059 0.3 0.0118 0.08 0.08 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Doc ID 6757 Rev 24 33/41 Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 17. WLCSP, 0.5 mm pitch, package outline Orientation reference D 2 3 1 A e2 e B C E D B G E e3 F e1 A2 A1 A 1. Drawing is not to scale. Table 22. WLCSP 0.5 mm pitch, package mechanical data(1) Inches(2) Millimeters Symbol Typ Min Max Typ Max A 0.60 0.55 0.65 0.0236 0.0217 0.0256 A1 0.245 0.22 0.27 0.0096 0.0087 0.0106 A2 0.355 0.330 0.380 0.0140 0.0130 0.0150 B O 0.311 O 0.0122 D 1.97 1.95 1.99 0.0776 0.0768 0.0783 E 1.785 1.765 1.805 0.0703 0.0695 0.0711 e 0.5 0.0197 e1 0.866 0.0341 e2 0.25 0.0098 e3 0.433 0.0170 F 0.552 0.502 0.602 0.0217 0.0198 0.0237 0.392 0.342 0.442 0.0154 0.0135 0.0174 G N (3) 8 1. Preliminary data. 2. Values in inches are converted from mm and rounded to four decimal digits. 3. N is the total number of terminals. 34/41 Min Doc ID 6757 Rev 24 8 M24256-BF, M24256-BR, M24256-BW, M24256-DR 8 Part numbering Table 23. Ordering information scheme Example: Part numbering M24256-B W MW 6 T P /AB Device type M24 = I2C serial access EEPROM Device function 256- = 256 Kbit (32 Kb x 8) Device family B: Without Identification page D: With additional Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package MN = SO8 (150 mils body width) DW = TSSOP8 MB = UFDFPN8 (MLP8) CS = WLCSP Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Automotive: device tested with high reliability certified flow(1) over -40 to 125 C Option blank = standard packing T = tape and reel packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process /A = F8L process (for WLCSP package ordering only) /AB = F8L process (for device grade 3 ordering only) 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 6757 Rev 24 35/41 Revision history 9 Revision history Table 24. Date Document revision history Revision Changes 29-Jan-2001 1.1 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated LGA8 and SO8(wide) packages added References to PSDIP8 changed to PDIP8, and Package Mechanical data updated 10-Apr-2001 1.2 LGA8 Package Mechanical data and illustration updated SO16 package removed 16-Jul-2001 1.3 LGA8 Package given the designator "LA" 02-Oct-2001 1.4 LGA8 Package mechanical data updated 13-Dec-2001 1.5 Document becomes Preliminary Data Test conditions for ILI, ILO, ZL and ZH made more precise VIL and VIH values unified. tNS value changed 12-Jun-2001 1.6 Document promoted to Full Datasheet 22-Oct-2003 2.0 Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. 3.0 LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified. AEC-Q100-002 compliance. VIL specification unified for SDA, SCL and WC 4.0 Initial delivery state is FFh (not necessarily the same as Erased). LGA package removed, TSSOP8 and SO8N packages added (see Package mechanical data section and Table 23: Ordering information scheme). Voltage range R (1.8V to 5.5V) also offered. Minor wording changes. ZL Test Conditions modified in Table 11: Input parameters and Note 2 added. ICC and ICC1 values for VCC = 5.5V added to Table 13: DC characteristics (voltage range W). Note added to Table 13: DC characteristics (voltage range W). Power On Reset paragraph specified. tW max value modified in Table 16: 400 kHz AC characteristics and note 4 added. Plating technology changed in Table 23: Ordering information scheme. Resistance and capacitance renamed in Figure 6. 02-Sep-2004 22-Feb-2005 36/41 M24256-BF, M24256-BR, M24256-BW, M24256-DR Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24. Date 05-May-2006 16-Oct-2006 02-Jul-2007 16-Oct-2007 Revision history Document revision history (continued) Revision Changes 5 Power On Reset paragraph replaced by Section 2.6: Supply voltage (VCC). Figure 4: Device select code added. ECC (error correction code) and write cycling added and specified at 1 Million cycles. ICC0 added and ICC1 specified over the whole voltage range in Table 13 and Table 14. PDIP8 package removed. Packages are ECOPACK(R) compliant. Small text changes. 6 M24256-BW and M24256-BR part numbers added. Section 3.11: ECC (error correction code) and write cycling updated. ICC and ICC1 modified in Table 14: DC characteristics (voltage range R). tW modified in Table 16: 400 kHz AC characteristics. SO8Narrow package specifications updated (see Table 19 and Figure 14). Blank option removed from below Plating technology in Table 23: Ordering information scheme. 7 Section 2.6: Supply voltage (VCC) modified. Section 3.11: ECC (error correction code) and write cycling modified. JEDEC standard and European directive references corrected below Table 6: Absolute maximum ratings. Rise/fall time conditions modified for ICC and VIH max modified in Table 13: DC characteristics (voltage range W) and Table 14: DC characteristics (voltage range R) Note 1 removed from Table 13: DC characteristics (voltage range W). SO8W package specifications modified in Section 7: Package mechanical data. Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) and Table 26: Available M24512-x products (package, voltage range, temperature grade) added. 8 Section 2.5: VSS ground added. Small text changes. VIO max changed and Note 1 updated to latest standard revision in Table 6: Absolute maximum ratings. Note removed from Table 11: Input parameters. VIH min and VIL max modified in Table 14: DC characteristics (voltage range R). Removed tCH1CH2, tCL1CL2 and tDH1DH2, and added tXL1XL2, tDL1DL2 and Note 3 in Table 16: 400 kHz AC characteristics. tXH1XH2, tXL1XL2 and Note 2 added to Table 17: 1 MHz AC characteristics. Figure 13: AC waveforms modified. Package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see Section 7: Package mechanical data). Doc ID 6757 Rev 24 37/41 Revision history Table 24. Date Document revision history (continued) Revision Changes 9 1 MHz frequency introduced (M24512-HR root part number). Section 2.6.3: Device reset modified. Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) modified, Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) added. tNS moved from Table 11 to Table 16. ILO test conditions modified in Table 13. Table 14: DC characteristics (voltage range R) and Table 17: 1 MHz AC characteristics modified. Small text changes. 10 Small text changes. M24256-BHR root part number added. Section 2.6.3: Device reset on page 9 updated. Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) on page 10 updated. Caution removed in Section 3.11: ECC (error correction code) and write cycling. 22-Apr-2008 11 M24512-W and M24256-BW offered in the device grade 3 option (automotive temperature range): - Table 7: Operating conditions (voltage range W), - Table 13: DC characteristics (voltage range W), - /AB Process letters added to Table 23: Ordering information scheme, - Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) and - Table 26: Available M24512-x products (package, voltage range, temperature grade) updated accordingly). Small text changes. 22-Dec-2008 12 WLCSP package added (see Figure 3: WLCSP connections (top view, marking side, with balls on the underside) and Section 7: Package mechanical data). 13 M24256-BF part number added (VCC = 1.7 V to 5.5 V voltage range added, see Table 9, Table 15, Table 16 and Table 25). ICC1 test conditions modified in Table 13: DC characteristics (voltage range W), Table 14: DC characteristics (voltage range R) and Table 15: DC characteristics (voltage range F). 14 M24512-DR part number and Identification page feature added. Command replaced by instruction in the whole document. UFDFPN8 added. Figure 6 updated. Section 2.6.2: Power-up conditions and Section 2.6.3: Device reset updated. tCLQX and tCLQV updated in Table 16, Note 5 and Note 8 added. tCLQX and tCLQV updated in Table 17, Note 6 and Note 9 added. Section 8: Part numbering updated. Reference to the SURE program removed in Section 5: Maximum rating. Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new M24512-R and M24256-BR (process letter K). 14-Dec-2007 27-Mar-2008 21-Jan-2009 05-Jun-2009 38/41 M24256-BF, M24256-BR, M24256-BW, M24256-DR Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24. Revision history Document revision history (continued) Date Revision 16-Jun-2009 15 Part numbers updated in cover page header. 20-Aug-2009 16 IOL added to Table 7: Operating conditions (voltage range W). Note 1and ICC modified in Table 13: DC characteristics (voltage range W); Note and ICC modified in Table 14: DC characteristics (voltage range R); 13-Oct-2009 17 Datasheet split to leave only devices with 256 Kbit capacity. M24256-DR part number added (see Table 26: Available M24256-DR products (package, voltage range, temperature grade). Figure 4: Device select code and Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) updated. VIO max modified in Table 6: Absolute maximum ratings. VIH modified in Table 13: DC characteristics (voltage range W), Table 14: DC characteristics (voltage range R) and Table 15: DC characteristics (voltage range F). In Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC characteristics: - tDL1DL2 changed to tQL1QL2 - tCHDX changed to tCHDL - tXH1XH2 and tXL1XL2 values removed - Notes modified Figure 13: AC waveforms modified. 05-Nov-2009 18 Section 3.9: Write Identification Page (M24256-D only) corrected.Section 3.17: Reading the Identification Page (M24256-D only) clarified. 10-Dec-2009 19 UFDFPN8 package is now offered (see Section 7: Package mechanical data, Table 23: Ordering information scheme and Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade). 19-Jan-2010 20 Revision number corrected at bottom of pages. 04-Mar-2010 21 Process description corrected in Table 23: Ordering information scheme. 22 Updated text in: Features, Section 1: Description, Section 3.1: Start condition, Section 3.6: Write operations, Section 3.9: Write Identification Page (M24256-D only), Section 3.10: Lock Identification Page (M24256-D only), Section 3.11: ECC (error correction code) and write cycling, Section 3.17: Reading the Identification Page (M24256-D only), Section 3.18: Reading the lock status (M24256-D only), Table 10: AC test measurement conditions, Section 8: Part numbering. Updated the following according to the IC_bus specification: Table 17: 400 kHz AC characteristics, Table 18: 1 MHz AC characteristics, Figure 13: AC waveforms. 21-Dec-2010 Changes Doc ID 6757 Rev 24 39/41 Revision history Table 24. Date 14-Feb-2011 05-Jul-2011 40/41 M24256-BF, M24256-BR, M24256-BW, M24256-DR Document revision history (continued) Revision Changes 23 Added caution under Figure 3: WLCSP connections (top view, marking side, with balls on the underside). Updated: - Description - Section 3.5: Addressing the memory array - Section 3.17: Reading the Identification Page (M24256-D only) - Section 3.18: Reading the lock status (M24256-D only) - Table 2: Most significant address byte - Table 6: Absolute maximum ratings - Table 17: 400 kHz AC characteristics - Table 18: 1 MHz AC characteristics Moved: - Table 2: Most significant address byte from Section 2.6.4 to Section 3.5 Deleted: - Table 3: Device select code to access the Identification page (M24256DR only) - Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) - Table 26: Available M24256-DR products (package, voltage range, temperature grade) 24 Added Table 12: Memory cell characteristics. Updated: - Section 1: Description - Table 6: Absolute maximum ratings - ICC0 maximum value in Table 14: DC characteristics (voltage range W, device grade 6), Table 15: DC characteristics (voltage range R) and Table 16: DC characteristics (voltage range F) Deleted all references to package SO8 (MW) 208 mils width. Doc ID 6757 Rev 24 M24256-BF, M24256-BR, M24256-BW, M24256-DR Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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