Power Management & Multimarket
Data Sheet
Revision 1.0, 2013-12-12
Final
ESD105-B1-02 Series
Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes
ESD105-B1-02ELS
ESD105-B1-02EL
TVS Diodes
Transient Voltage Suppressor Diodes
ESD105-B1-02 Series
Final Data Sheet 2 Revision 1.0, 2013-12-12
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™,
CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™,
EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™,
PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™,
SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™,
XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™,
REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership.
Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation
Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation.
FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of
Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of
INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP.
MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Revision History: Rev. 04, 2013-09-24
Page or Item Subjects (major cha nges since previous revision)
Revision 1.0, 2013-12-12
All Status change to Final
ESD105-B1-02 Series
Low Capacitan ce & Low Clamping Bi-directional ESD / Transient Protection
Final Data Sheet 3 Revision 1.0, 2013-12-12
1 Low Capacitance & Low Clamping Bi-directional ESD / Transient
Protection Diodes
1.1 Features
• ESD / Transient protection of signal lines exceeding standard:
–IEC61000-4-2 (ESD): ±30 kV air / ±25 kV contact discharge
–IEC61000-4-4 (EFT): ±50 A (5/50 ns)
–IEC61000-4-5 (Surge): ±5 A (8/20 μs)
• One-line diode with ultra-small form factor down to 0.62 x 0.32 x 0.31 mm² (0201) package size
• Bi-directional, symmetrical working voltage up to: VRWM =±5.5V
• Low capacitance CL=0.3pF (typical)
• Very low clamping voltage, low dynamic resistance: RDYN =0.36Ω (typ.)
• Pb-free package (RoHS compliant) and halogen free package
1.2 Application Examples
• USB 3.0. 10/100/1000 Ethernet, Firewire, DVI, HDMI, S-ATA, Display Ports
• Mobile HDMI Link, MDDI, MIPI, SWP, NFC
1.3 Product Description
Figure 1 Pin configuration and Schematic diagram
Table 1 Ordering Information
Type Package Configuration Marking code
ESD105-B1-02ELS TSSLP-2-4 1 line, bi-directional N
ESD105-B1-02EL TSLP-2-20 1 line, bi-directional N
a) Pin configuration
PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd
b) Schematic diagram
TSLP-2
TSSLP -2
Pin 1 Pin 2
Pin 1 Pin 2 Pin 1
Pin 2
Pin 1 marking
(lasered)
ESD105-B1-02 Series
Characteristics
Final Data Sheet 4 Revision 1.0, 2013-12-12
2 Characteristics
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1 Electrical Characteristics at TA= 25 °C, unless otherwise specified
Figure 2 Definitions of electrical characteristics
Table 2 Maximum Ratings at TA= 25 °C, unless otherwise specified 1)
1) Device is electrically symmetrical
Parameter Symbol Values Unit
Min. Typ. Max.
ESD2)
air discharge
contact discharge
2) VESD according to IEC61000-4-2
VESD
–
–
–
–
30
25
kV
Peak pulse current (tp = 8 / 20 μs)3)
3) IPP according to IEC61000-4-5
IPP ––5A
Peak pulse power3)
tp = 8 / 20 μs
PPK
––70
W
Operating temperature TOP -55 – 125 °C
Storage temperature Tstg -65 – 150 °C
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ESD105-B1-02 Series
Characteristics
Final Data Sheet 5 Revision 1.0, 2013-12-12
Table 3 DC Characteristics at TA= 25 °C, unless otherwise specified 1)
1) Device is electrically symmetrical
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Reverse working voltage VRWM ––5.5V
Reverse current IR–<120nAVR=5.5V
Trigger voltage Vt1 6.1––V
Holding voltage Vh6.18–VIR=1mA
Table 4 AC Characteristics at TA= 25 °C, unless otherwise specified
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Line capacitance CL– 0.3 0.45 pF VR=0V, f=1MHz
– 0.3 0.45 VR=0V, f=1GHz
Table 5 ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1)
1) Device is electrically symmetrical
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clamping voltage 2)
2) Please refer to Application Note AN210 [1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between ITLP1 = 10 A and
ITLP2 =50A.
VCL –1316VITLP =16A,
tp=100ns
–1922 ITLP =30A,
tp=100ns
Clamping voltage3)
3) IPP according to IEC61000-4-5 (tp=8/20µs)
– 8.5 11.5 IPP =2A, tp=8/20µs
–1114 IPP =5A, tp=8/20µs
Dynamic resistance2) RDYN – 0.36 0.45 Ωtp=100ns
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 6 Revision 1.0, 2013-12-12
3 Typical Characteristics at TA = 25 °C, unless otherwise specified
Figure 3 Reverse current: IR=f (VR)
Figure 4 Reverse current: IR=f(TA), VR=5.5V
10-11
10-10
10-9
10-8
10-7
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
IR [A]
VR [V]
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
30 40 50 60 70 80 90 100 110 120
IR [A]
TA [°C]
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 7 Revision 1.0, 2013-12-12
Figure 5 Line capacitance: CL=f (VR), f=1MHz
Figure 6 Peak pulse power: PPK =f (tp)
0.2
0.25
0.3
0.35
0.4
0.45
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
CL [pF]
VR [V]
f = 1 GHz
f = 1 MHz
0
100
200
300
400
500
600
700
10-7 10-6 10-5
PPK [W]
tp [s]
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 8 Revision 1.0, 2013-12-12
Figure 7 Clamping voltage (TLP): ITLP =f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge
Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0=50Ω,
tp=100ns, tr=0.6ns, ITLP and VTLP averaging window: t1=ns to t2= 60 ns, extraction of
dynamic resistance using squares fit to TLP characteristics between ITLP1 = 10 A and
ITLP2 = 50 A. Please refer to Application Note AN210[1]
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
ITLP [A]
Equivalent VIEC [kV]
VTLP [V]
ESD105-B1-02series
RDYN
RDYN = 0.36 Ω
RDYN = 0.36 Ω
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 9 Revision 1.0, 2013-12-12
Figure 8 Pulse current (IEC61000-4-5) versus clamping voltage: IPP =f(VCL)
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
IPP [A]
VCL [V]
ESD105-B1-02series
RDYN
RDYN = 0.9 Ω
RDYN = 0.9 Ω
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 10 Revision 1.0, 2013-12-12
Figure 9 IEC61000-4-2: VCL =f (t), 8 kV positive pulse from pin 1 to pin 2
Figure 10 IEC61000-4-2: VCL =f (t), 8 kV negative pulse from pin 1 to pin 2
-25
0
25
50
75
100
125
150
-50 0 50 100 150 200 250 300 350 400 450
VCL [V]
tp [ns]
Scope: 6 GHz, 20 GS/s
VCL-max-peak = 135 V
VCL-30ns-peak = 10 V
-150
-125
-100
-75
-50
-25
0
25
-50 0 50 100 150 200 250 300 350 400 450
VCL [V]
tp [ns]
Scope: 6 GHz, 20 GS/s
VCL-max-peak = -134 V
VCL-30ns-peak = -11 V
ESD105-B1-02 Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Final Data Sheet 11 Revision 1.0, 2013-12-12
Figure 11 IEC61000-4-2: VCL =f (t), 15 kV positive pulse from pin 1 to pin 2
Figure 12 IEC61000-4-2: VCL =f (t), 15 kV negative pulse from pin 1 to pin 2
-50
-25
0
25
50
75
100
125
150
175
200
-50 0 50 100 150 200 250 300 350 400 450
VCL [V]
tp [ns]
Scope: 6 GHz, 20 GS/s
VCL-max-peak = 183 V
VCL-30ns-peak = 14 V
-200
-175
-150
-125
-100
-75
-50
-25
0
25
50
-50 0 50 100 150 200 250 300 350 400 450
VCL [V]
tp [ns]
Scope: 6 GHz, 20 GS/s
VCL-max-peak = -185 V
VCL-30ns-peak = -14 V
ESD105-B1-02 Series
Application Information
Final Data Sheet 12 Revision 1.0, 2013-12-12
4 Application Information
Figure 13 Insertion loss measured in 50 Ω environment
Figure 14 Insertion loss vs. frequency of ESD1 05-B1-02xx in a 50 Ω system
ESD105-B1-02series_insertion_loss.vsd
Networkanalysor
50 Ohm port2
ESD105-B1-02series
Insertion Loss
in the application
Line Line
Networkanalysor
50 Ohm port1
-5
-4
-3
-2
-1
0
1 10 100 1000 10000
Insertion Loss [dB]
f [MHz]
ESD105-B1-TSLP 0V / 3dB @ 14410MHz
ESD105-B1-TSSLP 0V / 3dB @ 18142MHz
ESD105-B1-02 Series
Application Information
Final Data Sheet 13 Revision 1.0, 2013-12-12
Figure 15 Single line, bi-directional ESD / Transient protection
Application_ES D5V3S 1B-02LS.vsd
ESD
sensitive
device
1
2
Co nne cto r
Protected signal line
The protection diode should be placed very close to the location
wher e the ESD or other tr ansients can occur to keep loops and
inductances as small as possible .
Pin 2 (or pin 1) should be connected directly to a ground plane on
the board .
I/ O
ESD105-B1-02 Series
Package Information
Final Data Sheet 14 Revision 1.0, 2013-12-12
5 Package Information
5.1 TSSLP-2-4
Figure 16 TSSLP-2-4 Package outline
Figure 17 TSSLP-2-4 Footprint
Figure 18 TSSLP-2-4 Packing
Figure 19 TSSLP-2-4 Marking (example)
TSSLP-2-3-PO V01
±0.05
0.32
1
2
±0.035
0.2 1)
0.62 ±0.05
+0.01
0.31-0.02
1) Dimension applies to plated terminals
Cathode
marking
1)
±0.035
0.26
0.05 MAX.
Bottom viewTop view
0.355
0.27
0.19
0.19
0.19
Copper Solder mask Stencil apertures
0.57
0.24
0.62
0.32
0.24
0.14
TSSLP-2-3-FP V02
Ex
4
Ey
0.35
Cathode
marking
8
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
ESD105-B1-02 Series
Package Information
Final Data Sheet 15 Revision 1.0, 2013-12-12
5.2 TSLP-2-20
Figure 20 TSLP-2-20 Package outline
Figure 21 TSLP-2-20 Footprint
Figure 22 TSLP-2-20 Packing
Figure 23 TSLP-2-20 Marking (example)
TSLP-2-19, -20-PO V01
±0.05
0.6
1
2
±0.05
0.65
±0.035
0.25 1)
1±0.05
0.05 MAX.
+0.01
0.31-0.02
1) Dimension applies to plated terminals
Cathode
marking
1)
±0.035
0.5
Bottom viewTop view
TSLP-2-19, -20-FP V01
0.45
0.28 0.28
0.38
0.93
Copper Solder mask Stencil aperture
s
0.35
1
0.6
0.35
0.3
0.76
4
1.16
0.4
Cathode
marking
8
TSLP-2-19, -20-TP V02
Type code
Cathode marking
TSLP-2-19, -20-MK V01
12
ESD105-B1-02 Series
References
Final Data Sheet 16 Revision 1.0, 2013-12-12
References
[1] Infineon Technologies AG, “Effective ESD Protection Design at System Level Using VF-TLP
Characterization Methodology”, Application Note 210, RF and Protection Devices, April 22, 2010, Rev.1.0
[2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
Published by Infineon Technologies AG
www.infineon.com