Description
Available in PGA (PUMA 2), JLCC (PUMA 67) and
Gullwing (PUMA 77) footprints. The PUMA **S4000
is a 4 Mbit SRAM module, user configurable as
128K x 32, 256K x 16 or 512K x 8. The device is
available with fast access times of 20, 25 and
35ns. The device may be screened in accordance
with MIL-STD-883C.
Pin Functions
A0~A16 Address Input D0~D31 Data Inputs/Outputs
CS1~4 Chip Select WE1~4 Write Enables
OE Output Enable Vcc Power (+5V)
GND Ground
Features
•4 Megabit SRAM module.
•Fast Access Times of 20/25/35 ns.
•Output Configurable as 32 / 16 / 8 bit wide.
•Upgradeable footprint.
•Operating Power 3740 / 2310 / 1595 mW (Max).Low
Power Standby (L version) 220 mW (Max).
•TTL Compatible Inputs and Outputs.
•May be screened in accordance with MIL-STD-883.
•PUMA 2 - 66 pin ceramic PGA.
•PUMA 67 - 68 pin ceramic JLCC.
•PUMA 77 - 68 pin ceramic Gullwing.
Block Diagram
PUMA 67S4000 and 77S4000
Block Diagram
PUMA 2S4000, 67S4000A/B and 77S4000A/B
128K x 32 SRAM Module
PUMA2S4000 -20/25/35
PUMA 67S4000/A/B-20/25/35
PUMA 77S4000/A/B-20/25/35
Issue 4.5 : August 2002
D16-23
D0-7
D8-15
D24-31
CS1
CS2
CS3
CS4
OE
WE
A0-A16
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
D16~23
D0~7
D8~15
D24~31
CS1
CS2
CS3
CS4
OE
WE4
A0~A16
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
WE3
WE2
WE1
Elm Road, West Chirton, North Shields, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
2
Capacitance (VCC=5V±10%,TA=25°C) Note: (1) On the standard module, WE = 30 pF max.
Parameter Symbol Test Condition typ max Unit
Input Capacitance Address, OE CIN1 VIN =0V - 30 pF
WE1~4(1), CS1~4 CIN2 VIN =0V - 16 pF
I/O Capacitance D0~D31 CI/O VI/O=0 V - 30 pF (8 bit mode)
Input Leakage Current ILI1 VIN=0V to VCC -8 - 8 µA
Output Leakage Current ILO CS(1)=VIH or OE=VIH, VI/O=0V to VCC -8 - 8 µA
WE=VIL
Operating Supply Current 32 bit ICC32 Min cycle,duty=100%,II/O=0mA,CS=VIL - - 680 mA
16 bit ICC16 As above - - 420 mA
8 bit ICC8 Min cycle,duty=100%,II/O=0mA,CS=VIL - - 290 mA
Standby Supply Current (TTL) ISB1 CS(1)≥VIH VCC = 5.5V - - 160 mA
-L Version ISB2 CS(1)
≥VIH, VIL≤VIN≥VIH, f = 0 Hz - - 40 mA
Output Voltage Low VOL IOL = 8.0mA - - 0. 4 V
Output Voltage High VOH IOH = -4.0mA 2. 4 - - V
Notes: (1) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be
operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
DC Electrical Characteristics (VCC=5V±10%,TA=-55°C to +125°C)
Parameter Symbol Test Condition min typ max Unit
Recommended Operating Conditions
min typ max
Supply Voltage VCC 4.5 5.0 5.5 V
Input High Voltage VIH 2.2 - 6.0 V
Input Low Voltage VIL -0.5 - 0.8 V
Operating Temperature TA0- 70°C
TAI -40 - 85 °C (Suffix I)
TAM -55 - 125 °C (Suffix M, MB)
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to GND(2) VT-0.5V to +7.0 V
Power Dissipation PT 4 W
Storage Temperature TSTG -65 to +150 °C
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
These parameters are calculated, not measured.
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
3
Operating Modes
The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
modules.
Note: CS above is accessed through CS1~4 (and WE by WE1~4 on the PUMA 2S4000, 67S4000A, 77S4000A). For correct
operation, CS1~ 4 (and WE1~4) must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or
singly for 8 bit operation.
1 = VIH,
0 = VIL,
X = Don't Care
166
30pF
I/O Pin
1.76V
Ω
Mode CS OE WE VCC Current I/O Pin Reference Cycle
Not Selected 1 X X ISB1,ISB2 High Z Power Down
Output Disable 0 1 1 ICC High Z -
Read 0 0 1 ICC DOUT Read Cycle
Write 0 X 0 ICC DIN Write Cycle
AC Test Conditions Output Load
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*Vcc=5V±10%
*PUMA module is tested in 32 bit mode.
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
4
Write Cycle
20 25 35
Parameter Symbol min max min max min max Unit
Write Cycle Time tWC 20 - 25 - 35 - ns
Chip Selection to End of Write tCW 15 - 16 - 20 - ns
Address Valid to End of Write tAW 15 - 16 - 20 - ns
Address Setup Time tAS 0- 0- 0-ns
Write Pulse Width tWP 15 - 15 - 20 - ns
Write Recovery Time tWR 0- 5- 5-ns
Data to Write Time Overlap tDW 015 10- 15-ns
Output Active from End of Write tOW 15-3-3-ns
Data Hold from Write Time tDH 2* - 2* - 2* - ns
Write to Output High Z tWHZ 5- 010 010ns
AC OPERATING CONDITIONS
Read Cycle
20 25 35
Parameter Symbol min max min max min max Units
Read Cycle Time tRC 20 - 25 - 35 - ns
Address Access Time tAA -20-25-35ns
Chip Select Access Time tACS -20-25-35ns
Output Enable to Output Valid tOE -9-8-12ns
Output Hold from Address Change tOH 5-5-5-ns
Chip Selection to Output in Low Z tCLZ 6-5-5-ns
Output Enable to Output in Low Z tOLZ 0-0-0- ns
Chip Deselection to Output in High Z(3) tCHZ 09-15-15ns
Output Disable to Output in High Z(3) tOHZ 09-15-15ns
* Note : Only applies to PUMA 67S4000/A otherwise tDH (min) = 0
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
5
Write Cycle No.1 Timing Waveform
Read Cycle Timing Waveform (1,2)
Notes:
(1) During the Read Cycle, WE is high for the modules.
(2) Address valid prior to or coincident with CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
t
t
t
t
RC
AA
OE
OH
A0~A16
OE
CS1~4
t
OHZ(3)
t
OLZ
t
ACS
t
CLZ
t
CHZ(3)
Data Valid
D0~31
High-Z
t
AS(3)
t
AW
t
CW(4)
t
WC
A0~A16
OE
CS1~4
t
WP(1)
t
OHZ(3,9)
WE1~4
D0~31out
t
t
DW
DH
D0~31in
(6)
t
WR
(2)
t
OW
High-Z
High-Z
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
6
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.2 Timing Waveform (5)
CS1~4
t
WR(2)
t
CW
(4)
(6)
t
AW
t
WC
A0~A16
t
t
t
WP(1)
DW
t
DH
WE1~4
D0~31out
D0~31in
WHZ(3,9)
t
AS(3)
t
OW
t
OH
(7)
(8)
High-Z
High-Z
WE above refers to WE1~4 on the PUMA 2S4000, 67S4000A AND 77S4000A.
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
7
Package Details
PUMA 67S4000
24.99 ( 0.9 84) sq.
24.89 ( 0.9 80) sq.
(0.202) max
R=0.76 (0.03 0 ) typ.
1.27
(0.050) typ.
0.64
(0.025) min
21.08 ( 0.8 30)
0.43
(0.017) typ.
0.10 (0.004)
25.40 ( 1.0 00) sq.
24.49 ( 0.9 64) sq.
1.35 (0.053)
0.94 (0.037)
5.13
20.57 ( 0.8 10) sq.
20.07 ( 0.7 90) sq.
24.13 ( 0.9 50) sq.
23.11 ( 0.9 10) sq.
21.37 ( 0.8 40)
PUMA 77S4000
PUMA 2S4000
SOLDER OVER 50 TO 350 µIN
CH NICKEL
LEAD FINISH IS 300 µINCH
MINIMUM
15.24 (0.60 ) typ
27.69 (1.0 9 0) s quare
4.83 (0.190)
4.32 (0.170)
1.27 (0.050)
1.52 (0.060)
27.08 (1.0 6 6) s quare
6.86 (0.270) max
1.27 (0.050)
1.66 (0.026)
10.67 (0.4 2 0)
10.16 (0.4 0 0)
2.54 (0.010)
3.81 (0.150) ref
2.54 (0.010)
1.02 (0.040)
0.53 (0.021)
0.38 (0.015)
0.10 (0.004)
24.13 (0.950) sq.
20.57 (0.810) sq.
1.27
(0.050)
0.43
(0.017)
1.78
(0.070)
5.44
(0.214) max
25.15 (0.990) sq.
22.61 (0.890)
sq.
0.76
(0.030)
24.67 (0.970)
sq.
22.10 (0.870)
sq.
20.10 (0.790) sq.
23.62 (0.930) sq.
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
8
Pin Definitions
PUMA 67S4000 / PUMA 77S4000 PUMA 67S4000A / PUMA 77S4000A
1
12
23
VIEW
FROM
ABOVE
2
13
24
3
14
25
4
15
26
5
16
27
6
17
28
7
18
29
8
19
30
9
20
31
10
21
32
11
22
33
34
45
56
35
46
57
36
47
58
37
48
59
38
49
60
39
50
61
40
51
62
41
52
63
42
53
64
43
54
65
44
55
66
D8
WE2
D15
D9
CS2
D14
D10
GND
D13
A13
D11
D12
A14
A10
OE
A15
A11
NC
A16
A12
WE1
NC
VCC
D7
D0
CS1
D6
D1
NC
D5
D2
D3
D4
D24
VCC
D31
D25
CS4
D30
D26
WE4
D29
A6
D27
D28
A7
A3
A0
NC
A4
A1
A8
A5
A9
WE3
D23
D16
CS3
D22
D17
GND
D21
D18
D19
D20
A2
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
NC
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
Vcc
CS3
CS4
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OE
CS2
NC
GND
Vcc
A11
A12
A13
A14
A15
A16
CS1
NC
NC
WE2
WE3
WE4
WE1
PUM A 67S4000A
VIEW
FROM
ABOVE
PUMA 2S4000 PUMA 67S4000B / PUMA 77S4000B
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
NC
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
Vcc
CS3
CS4
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OE
CS2
NC
GND
Vcc
A11
A12
A13
A14
A15
A16
CS1
NC
NC WE1
PUM A 67S4000
VIEW
FROM
ABOVE
NC
NC
NC
PUMA 67/ 77E4001B
VIEW
FROM
ABOVE
44
NC
A0
A1
A2
A3
A4
A5
/CS3
GND
/CS4
/WE1
A6
A7
A8
A9
A10
Vcc
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vcc
A11
A12
A13
A14
A15
A16
/CS1
/OE
/CS2
NC
NC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
NC
NC
/WE2
/WE3
/WE4
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
9
Military Screening Procedure
MultiChip Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
SCREENING
MB MULTICHIP MODULE SCREENING FLOW
SCREEN TEST METHOD LEVEL
Visual and Mechanical
Internal visual 2010 Condition B or manufacturers equivalent 100%
Temperature cycle 1010 Condition C (10 Cycles,-65oC to +150oC) 100%
Constant acceleration 2001 Condition B (Y1 & Y2) (10,000g) 100%
Burn-In
Pre-Burn-in electrical Per applicable device specifications at TA=+25oC 100%
Burn-in TA=+125oC,160hrs minimum. 100%
Final Electrical Tests Per applicable Device Specification
Static (DC) a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Functional a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Switching (AC) a) @ TA=+25oC and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC 10%
Hermeticity 1014
Fine Condition A 100%
Gross Condition C 100%
Quality Conformance Per applicable Device Specification Sample
External Visual 2009 Per vendor or customer specification 100%
PUMA 2/67/77S4000/A/B - 20/25/35 Issue 4.5 August 2002
10
PUMA 2S4000ALMB- 20
Spee d 20 = 20 ns
25 = 25 ns
35 = 35 ns
Screening Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature
MB = Processed in
accordance with MIL-STD-883
Power Blank = Standard Power
L = Low Power
WE Option Blank = Single WE (PUMA 67 / 77 only)
WE1~4 (PUMA 2 only)
A = WE1~4 (PUMA 67 / 77 only)
B = Pinout variant
Organisation 4000 = 128Kx 32, user confiurable as
256K x 16 and 512K x 8
Technology S = SRAM MEMORY
Package PUMA 2 = JEDEC 66 Pin Ceramic PGA
package
PUMA 67 = JEDEC 68 J-Leaded Ceramic
Surface Mount package
PUMA 77 = JEDEC 68 Leaded Gull Wing
Ceramic Surface Mount package
Ordering Information
Note :
Although this data is believed to be accurate, the information contained herein is not intended to, and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of a
company director.
