LME49724
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LME49724 High Performance, High Fidelity, Fully-Differential Audio Operational Amplifier
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1FEATURES DESCRIPTION
The LME49724 is an ultra-low distortion, low noise,
2• Drives 600ΩLoads with Full Output Signal high slew rate fully-differential operational amplifier
Swing optimized and fully specified for high performance,
• Optimized for Superior Audio Signal Fidelity high fidelity applications. Combining advanced
• Output Short Circuit Protection leading-edge process technology with state of the art
circuit design, the LME49724 fully-differential audio
• PSRR and CMRR Exceed 100dB (typ) operational amplifier delivers superior audio signal
• Available in SO PowerPad Package amplification for outstanding audio performance. The
LME49724 combines extremely low voltage noise
APPLICATIONS density (2.1nV/√Hz) with vanishingly low THD+N
(0.00003%) to easily satisfy the most demanding
• Ultra High Quality Audio Amplification audio applications. To ensure that the most
• High Fidelity Preamplifiers and Active Filters challenging loads are driven without compromise, the
• Simple Single-Ended to Differential LME49724 has a high slew rate of ±18V/μs and an
Conversion output current capability of ±80mA. Further, dynamic
range is maximized by an output stage that drives
• State of the Art D-to-A Converters 600Ωloads to 52VP-P while operating on a ±15V
• State of the Art A-to-D input Amplifiers supply voltage.
• Professional Audio The LME49724's outstanding CMRR (102dB), PSRR
• High Fidelity Equalization and Crossover (125dB), and VOS (0.2mV) results in excellent
Networks operational amplifier DC performance.
• High Performance Line Drivers and Receivers The LME49724 has a wide supply range of ±2.5V to
±18V. Over this supply range the LME49724’s input
circuitry maintains excellent common-mode and
power supply rejection, as well as maintaining its low
input bias current. The LME49724 is unity gain
stable. This Fully-Differential Audio Operational
Amplifier achieves outstanding AC performance while
driving complex loads with capacitive values as high
as 100pF.
Table 1. Key Specifications
Power Supply Voltage Range ±2.5V to ±18V
RL= 2kΩ0.00003% (typ)
THD+N (AV= 1, VOUT = 3VRMS, fIN = 1kHz) RL= 600Ω0.00003% (typ)
Input Noise Density 2.1nV/√Hz (typ)
Slew Rate ±18V/μs (typ)
Gain Bandwidth Product 50 MHz (typ)
Open Loop Gain (RL= 600Ω) 125 dB (typ)
Input Bias Current 60nA (typ)
Input Offset Voltage 0.2mV (typ)
DC Gain Linearity Error 0.000009%
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
-
+
-
+
8
3
VIN-
2
6
1
4
7
5
VIN+
VOCM
VCC
VOUT+ VOUT-
ENABLE
VEE
LME49724
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Typical Application
Figure 1. Typical Application Circuit
Connection Diagram
Figure 2. 8-Pin SO PowerPad
See DDA0008B Package
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PIN DESCRIPTIONS
Pin Name Pin Function Type
1 VIN- Input pin Analog Input
Sets the output DC voltage. Internally set by a resistor divider to the
2 VOCM midpoint of the voltages on the VCC and VEE pins. Can be forced Analog Input
externally to a different voltage (50kΩinput impedance).
3 VCC Positive power supply pin. Power Supply
Output pin. Signal is inverted relative to VIN-where the feedback loop is
4 VOUT+ Analog Output
connected.
Output pin. Signal is inverted relative to VIN+ where the feedback loop is
5 VOUT- Analog Output
connected.
6 VEE Negative power supply pin or ground for a single supply configuration. Power Supply
Enables the LME49724 when the voltage is greater than 2.35V above
the voltage on the VEE pin. Disable the LME49724 by connecting to the
7 ENABLE Analog Input
same voltage as on the VEE pin which will reduce current consumption to
less than 0.3mA (typ).
8 VIN+ Input pin Analog Input
Exposed pad for improved thermal performance. Connect to the same
Exposed Pad potential as the VEE pin or electrically isolate.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Power Supply Voltage (VS= VCC + |VEE |) 38V
Storage Temperature −65°C to 150°C
Input Voltage (VEE) – 0.7V to (VCC) + 0.7V
Output Short Circuit Continuous
Power Dissipation (4) Internally Limited
ESD Rating (5) 2000V
ESD Rating (6) 200V
Junction Temperature (TJMAX) 150°C
Soldering Information Vapor Phase (60sec.) 215°C
Infrared (60sec.) 220°C
Thermal Resistance θJA (MR) 49.6°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
(5) Human body model, applicable std. JESD22-A114C.
(6) Machine model, applicable std. JESD22-A115-A.
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Operating Ratings (1)(2)
Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage Range ±2.5V ≤VS≤±18V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
Electrical Characteristics (1)(2)
The following specifications apply for VS= ±15V, RL= 2kΩ, fIN = 1kHz, and TA= 25°C, unless otherwise specified.
LME49724 Units
Symbol Parameter Conditions (Limits)
Typical (3) Limit (4)
POWER SUPPLY
±2.5V V (min)
VSOperating Power Supply ±18V V (max)
VO= 0V, IO= 0mA
ICCQ Total Quiescent Current Enable = GND 10 15 mA (max)
Enable = VEE 0.3 0.5 mA (max)
PSRR Power Supply Rejection Ratio VS= ±5V to ±15V (5) 125 95 dB (min)
VENIH Enable High Input Voltage Device active, TA= 25°C (6) VEE + 2.35 V
VENIL Enable Low Input Voltage Device disabled, TA= 25°C (6) VEE + 1.75 V
DYNAMIC PERFORMANCE
AV= 1, VOUT = 3VRMS
THD+N Total Harmonic Distortion + Noise RL= 2kΩ0.00003 %
RL= 600Ω0.00003 0.00009 % (max)
AV= 1, VOUT = 3VRMS
IMD Intermodulation Distortion 0.0005 %
Two-tone, 60Hz & 7kHz 4:1
GBWP Gain Bandwidth Product 50 35 MHz (min)
VOUT = 1VP-P, –3dB
FPBW Full Power Bandwidth referenced to output magnitude 13 MHz
at f = 1kHz
SR Sew Rate RL= 2kΩ±18 ±13 V/μs (min)
AV= –1, 10V step, CL= 100pF
tSSettling time 0.2 μs
settling time to 0.1%
–10V < VOUT < 10V, RL= 600Ω125 100 dB (min)
AVOL Open-Loop Voltage Gain –10V < VOUT < 10V, RL= 2kΩ125 dB
–10V < VOUT < 10V, RL= 10kΩ125 dB
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
(5) PSRR is measured as follows: VOS is measured at two supply voltages, ±5V and ±15V. PSRR = | 20log(ΔVOS/ΔVS) |.
(6) The ENABLE threshold voltage is determined by VBE voltages and will therefore vary with temperature. The typical values represent the
most likely parametric norms at TA= +25°C.
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Electrical Characteristics (1)(2) (continued)
The following specifications apply for VS= ±15V, RL= 2kΩ, fIN = 1kHz, and TA= 25°C, unless otherwise specified.
LME49724 Units
Symbol Parameter Conditions (Limits)
Typical (3) Limit (4)
NOISE
μVRMS
Equivalent Input Noise Voltage fBW = 20Hz to 20kHz 0.30 0.64 (max)
eNf = 1kHz 2.1 nV/√Hz
Equivalent Input Noise Density f = 10Hz 3.7 (max)
INPUT CHARACTERISTICS
VOS Offset Voltage ±0.2 ±1 mV (max)
Average Input Offset Voltage Drift vs
ΔVOS/ΔTemp –40°C ≤TA≤85°C 0.5 μV/°C
Temperature
IBInput Bias Current VCM = 0V 60 200 nA (max)
IOS Input Offset Current VCM = 0V 10 65 nA (max)
Input Bias Current Drift vs
ΔIOS/ΔTemp –40°C ≤TA≤85°C 0.1 nA/°C
Temperature VCC – 1.5 V (min)
VIN-CM Common-Mode Input Voltage Range ±14 VEE + 1.5 V (min)
CMRR Common-Mode Rejection –10V < VCM < 10V 102 95 dB (min)
Differential Input Impedance 16 kΩ
ZIN Common-Mode Input Impedance –10V < VCM < 10V 500 MΩ
OUTPUT CHARACTERISTICS
RL= 600Ω52 50 VP-P (min)
VOUTMAX Maximum Output Voltage Swing RL= 2kΩ52 VP-P
RL= 10kΩ53 VP-P
IOUT-CC Instantaneous Short Circuit Current 80 mA
fIN = 10kHz
ROUT Output Impedance Closed-Loop 0.01 Ω
Open-Loop 23 Ω
CLOAD Capacitive Load Drive Overshoot CL= 100pF 5 %
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Typical Performance Characteristics
THD+N THD+N
vs vs
Frequency Frequency
VS= ±2.5V, VO= 0.5VRMS, Differential Input VS= ±2.5V, VO= 0.8VRMS, Differential Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 3. Figure 4.
THD+N THD+N
vs vs
Frequency Frequency
VS= ±15V, VO= 3VRMS, Differential Input VS= ±15V, VO= 10VRMS, Differential Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 5. Figure 6.
THD+N THD+N
vs vs
Frequency Frequency
VS= ±18V, VO= 3VRMS, Differential Input VS= ±18V, VO= 10VRMS, Differential Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±2.5V, RL= 600Ω, Differential Input VS= ±15V, RL= 600Ω, Differential Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 9. Figure 10.
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±18V, RL= 600Ω, Differential Input VS= ±2.5V, RL= 2kΩ, Differential Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 11. Figure 12.
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±15V, RL= 2kΩ, Differential Input VS= ±18V, RL= 2kΩ, Differential Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±2.5V, RL= 10kΩ, Differential Input VS= ±15V, RL= 10kΩ, Differential Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 15. Figure 16.
THD+N THD+N
vs vs
Output Voltage Frequency
VS= ±18V, RL= 10kΩ, Differential Input VS= ±2.5V, VO= 0.5VRMS, Single-ended Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 17. Figure 18.
THD+N THD+N
vs vs
Frequency Frequency
VS= ±2.5V, VO= 0.8VRMS, Single-ended Input VS= ±15V, VO= 3VRMS, Single-ended Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
THD+N THD+N
vs vs
Frequency Frequency
VS= ±15V, VO= 5VRMS, Single-ended Input VS= ±18V, VO= 3VRMS, Single-ended Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW
Figure 21. Figure 22.
THD+N THD+N
vs vs
Frequency Output Voltage
VS= ±18V, VO= 5VRMS, Single-ended Input VS= ±2.5V, RL= 600Ω, Single-ended Input
RL= 600Ω, 2kΩ, 10kΩ, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 23. Figure 24.
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±15V, RL= 600Ω, Single-ended Input VS= ±18V, RL= 600Ω, Single-ended Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 25. Figure 26.
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Typical Performance Characteristics (continued)
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±2.5V, RL= 2kΩ, Single-ended Input VS= ±15V, RL= 2kΩ, Single-ended Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 27. Figure 28.
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±18V, RL= 2kΩ, Single-ended Input VS= ±2.5V, RL= 10kΩ, Single-ended Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 29. Figure 30.
THD+N THD+N
vs vs
Output Voltage Output Voltage
VS= ±15V, RL= 10kΩ, Single-ended Input VS= ±18V, RL= 10kΩ, Single-ended Input
f = 20Hz, 1kHz, 20kHz, 80kHz BW f = 20Hz, 1kHz, 20kHz, 80kHz BW
Figure 31. Figure 32.
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Typical Performance Characteristics (continued)
PSRR PSRR
vs vs
Frequency Frequency
VS= ±2.5V, RL= 600Ω, Inputs to GND VS= ±15V, RL= 600Ω, Inputs to GND
VRIPPLE = 200mVP-P, 80kHz BW VRIPPLE = 200mVP-P, 80kHz BW
Figure 33. Figure 34.
PSRR PSRR
vs vs
Frequency Frequency
VS= ±18V, RL= 600Ω, Inputs to GND VS= ±2.5V, RL= 2kΩ, Inputs to GND
VRIPPLE = 200mVP-P, 80kHz BW VRIPPLE = 200mVP-P, 80kHz BW
Figure 35. Figure 36.
PSRR PSRR
vs vs
Frequency Frequency
VS= ±15V, RL= 2kΩ, Inputs to GND VS= ±18V, RL= 2kΩ, Inputs to GND
VRIPPLE = 200mVP-P, 80kHz BW VRIPPLE = 200mVP-P, 80kHz BW
Figure 37. Figure 38.
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Typical Performance Characteristics (continued)
PSRR PSRR
vs vs
Frequency Frequency
VS= ±2.5V, RL= 10kΩ, Inputs to GND VS= ±15V, RL= 10kΩ, Inputs to GND
VRIPPLE = 200mVP-P, 80kHz BW VRIPPLE = 200mVP-P, 80kHz BW
Figure 39. Figure 40.
PSRR CMRR
vs vs
Frequency Frequency
VS= ±18V, RL= 10kΩ, Inputs to GND VS= ±2.5V, VCMRR = 1VP-P
VRIPPLE = 200mVP-P, 80kHz BW RL= 600Ω, 2kΩ, 10kΩ
Figure 41. Figure 42.
CMRR CMRR
vs vs
Frequency Frequency
VS= ±15V, VCMRR = 1VP-P VS= ±18V, VCMRR = 1VP-P
RL= 600Ω, 2kΩ, 10kΩRL= 600Ω, 2kΩ, 10kΩ
Figure 43. Figure 44.
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Typical Performance Characteristics (continued)
Output Voltage Output Voltage
vs vs
Load Resistance Load Resistance
VS= ±2.5V, RL= 500Ω– 10kΩVS= ±15V, RL= 500Ω– 10kΩ
THD+N ≤1%, 80kHz BW THD+N ≤1%, 80kHz BW
Figure 45. Figure 46.
Output Voltage Output Voltage
vs vs
Load Resistance Supply Voltage
VS= ±18V, RL= 500Ω– 10kΩRL= 600Ω, 2kΩ, 10kΩ, THD+N ≤1%
THD+N ≤1%, 80kHz BW 80kHz BW
Figure 47. Figure 48.
Supply Current
vs
Supply Voltage
VIN = 0V, RL= No Load
Figure 49.
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APPLICATION INFORMATION
GENERAL OPERATION
The LME49724 is a fully differential amplifier with an integrated common-mode reference input (VOCM). Fully
differential amplification provides increased noise immunity, high dynamic range, and reduced harmonic
distortion products.
Differential amplifiers typically have high CMRR providing improved immunity from noise. When input, output,
and supply line trace pairs are routed together, noise pick up is common and easily rejected by the LME49724.
CMRR performance is directly proportional to the tolerance and matching of the gain configuring resistors. With
0.1% tolerance resistors the worst case CMRR performance will be about 60dB (20LOG(0.001)).
A differential output has a higher dynamic range than a single-ended output because of the doubling of output
voltage. The dynamic range is increased by 6dB as a result of the outputs being equal in magnitude but opposite
in phase. As an example, a single-ended output with a 1VPP signal will be two 1VPP signals with a differential
output. The increase is 20LOG(2) = 6dB. Differential amplifiers are ideal for low voltage applications because of
the increase in signal amplitude relative to a single-ended amplifier and the resulting improvement in SNR.
Differential amplifiers can also have reduced even order harmonics, all conditions equal, when compared to a
single-ended amplifier. The differential output causes even harmonics to cancel between the two inverted outputs
leaving only the odd harmonics. In practice even harmonics do not cancel completely, however there still is a
reduction in total harmonic distortion.
OUTPUT COMMON-MODE VOLTAGE (VOCM pin)
The output common-mode voltage is the DC voltage on each output. The output common-mode voltage is set by
the VOCM pin. The VOCM pin can be driven by a low impedance source. If no voltage is applied to the VOCM pin,
the DC common-mode output voltage will be set by the internal resistor divider to the midpoint of the voltages on
the VCC and VEE pins. The input impedance of the VOCM pin is 50kΩ. The VOCM pin can be driven up to VCC -
1.5V and VEE + 1.5V. The VOCM pin should be bypassed to ground with a 0.1μF to 1μF capacitor. The VOCM pin
should be connected to ground when the desired output common-mode voltage is ground reference. The value
of the external capacitor has an effect on the PSRR performance of the LME49724. With the VOCM pin only
bypassed with a low value capacitor, the PSRR performance of the LME49724 will be reduced, especially at low
audio frequencies. For best PSRR performance, the VOCM pin should be connected to stable, clean reference.
Increasing the value of the bypass capacitor on the VOCM pin will also improve PSRR performance.
ENABLE FUNCTION
The LME49724 can be placed into standby mode to reduce system current consumption by driving the ENABLE
pin below VEE + 1.75V. The LME49724 is active when the voltage on the ENABLE pin is above VEE + 2.35V. The
ENABLE pin should not be left floating. For best performance under all conditions, drive the ENABLE pin to the
VEE pin voltage to enter standby mode and to ground for active operation when operating from split supplies.
When operating from a single supply, drive the ENABLE pin to ground for standby mode and to VCC for active
mode.
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FULLY DIFFERENTIAL OPERATION
The LME49724 performs best in a fully differential configuration. The circuit shown in Figure 50 is the typical fully
differential configuration.
Figure 50. Fully Differential Configuration
The closed-loop gain is shown in Equation 1 below.
AV= RF/ Ri(V/V)
where
• RF1 = RF2
• Ri1 = Ri2
• Using low value resistors will give the lowest noise performance (1)
SINGLE-ENDED TO DIFFERENTIAL CONVERSION
For many applications, it is required to convert a single-ended signal to a differential signal. The LME49724 can
be used for a high performance, simple single-to-differential converter. Figure 51 shows the typical single-to-
differential converter circuit configuration.
Figure 51. Single-Ended Input to Differential Output
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SINGLE SUPPLY OPERATION
The LME49724 can be operated from a single power supply, as shown in Figure 52. The supply voltage range is
limited to a minimum of 5V and a maximum of 36V. The common-mode output DC voltage will be set to the
midpoint of the supply voltage. The VOCM pin can be used to adjust the common-mode output DC voltage on the
outputs, as described previously, if the supply voltage midpoint is not the desired DC voltage.
Figure 52. Single Supply Configuration
DRIVING A CAPACITIVE LOAD
The LME49724 is a high speed op amp with excellent phase margin and stability. Capacitive loads up to 100pF
will cause little change in the phase characteristics of the amplifiers and are therefore allowable.
Capacitive loads greater than 100pF must be isolated from the output. The most straightforward way to do this is
to put a resistor in series with the output. This resistor will also prevent excess power dissipation if the output is
accidentally shorted.
THERMAL PCB DESIGN
The LME49724's high operating supply voltage along with its high output current capability can result in
significant power dissipation. For this reason the LME49724 is provided in the exposed DAP SO PowerPad
package for improved thermal dissipation performance compared to other surface mount packages. The exposed
pad is designed to be soldered to a copper plane on the PCB which then acts as a heat sink. The thermal plane
can be on any layer by using multiple thermal vias under and outside the IC package. The vias under the IC
should have solder mask openings for the entire pad under the IC on the top layer but cover the vias on the
bottom layer. This method prevents solder from being pulled away from the thermal vias during the reflow
process resulting in optimum thermal conductivity.
Heat radiation from the PCB plane area is best accomplished when the thermal plane is on the top or bottom
copper layers. The LME49724 should always be soldered down to a copper pad on the PCB for both optimum
thermal performance as well as mechanical stability.
The exposed pad is for heat transfer and the thermal plane should either be electrically isolated or connected to
the same potential as the VEE pin. For high frequency applications (f > 1MHz) or lower impedance loads, the pad
should be connected to a plane that is connected to the VEE potential.
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49724
LME49724
www.ti.com
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
SUPPLY BYPASSING
The LME49724 should have its supply leads bypassed with low-inductance capacitors such as leadless surface
mount (SMT) capacitors located as close as possible to the supply pins. It is recommended that a 10μF tantalum
or electrolytic capacitor be placed in parallel with a 0.1μF ceramic or film type capacitor on each supply pin.
These capacitors should be star routed with a dedicated ground return plane or large trace for best THD
performance. Placing capacitors too far from the power supply pins, especially with thin connecting traces, can
lead to excessive inductance, resulting in degraded high-frequency bypassing. Poor high-frequency bypassing
can result in circuit instabilities. When using high bandwidth power supplies, the value and number of supply
bypass capacitors should be reduced for optimal power supply performance.
BALANCE CABLE DRIVER
With high peak-to-peak differential output voltage and plenty of low distortion drive current, the LME49724 makes
an excellent balanced cable driver. Combining the single-to-differential configuration with a balanced cable driver
results in a high performance single-ended input to balanced line driver solution.
Although the LME49724 can drive capacitive loads up to 100pF, cable loads exceeding 100pF can cause
instability. For such applications, series resistors are needed on the outputs before the capacitive load.
ANALOG-TO-DIGITAL CONVERTER (ADC) APPLICATION
Figure 53 is a typical fully differential application circuit for driving an analog-to-digital converter (ADC). The
additional components of R5, R6, and C7are optional components and are for stability and proper ADC sampling.
ADC's commonly use switched capacitor circuitry at the input. When the ADC samples the signal the current
momentarily increases and may disturb the signal integrity at the sample point causing a signal glitch.
Component C7is significantly larger than the input capacitance of a typical ADC and acts as a charge reservoir
greatly reducing the effect of the signal sample by the ADC. Resistors R5and R6decouple the capacitive load,
C7, for stability. The values shown are general values. Specific values should be optimized for the particular ADC
loading requirements.
The output reference voltage from the ADC can be used to drive the VOCM pin to set the common-mode DC
voltage on the outputs of the LME49724. A buffer may be needed to drive the LME49724's VOCM pin if the ADC
cannot drive the 50kΩinput impedance of the VOCM pin.
In order to minimize circuit distortion when using capacitors in the signal path, the capacitors should be
comprised of either NPO ceramic, polystyrene, polypropylene or mica composition. Other types of capacitors
may provide a reduced distortion performance but for a cost improvement, so capacitor selection is dependent
upon design requirements. The performance/cost tradeoff for a specific application is left up to the user.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LME49724
LME49724
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
*Value is application and converted dependent.
Figure 53. Typical Analog-to-Digital Converter Circuit
DISTORTION MEASUREMENTS
The vanishing low residual distortion produced by the LME49724 is below the capabilities of commercially
available equipment. This makes distortion measurements more difficult than simply connecting a distortion
meter to the amplifier’s inputs and outputs. The solution, however, is quite simple: an additional resistor. Adding
this resistor extends the resolution of the distortion measurement equipment.
The LME49724’s low residual distortion is an input referred internal error. As shown in Figure 54, adding a
resistor connected between the amplifier’s inputs changes the amplifier’s noise gain. The result is that the error
signal (distortion) is increased. Although the amplifier’s closed-loop gain is unaltered, the feedback available to
correct distortion errors is reduced, which means that measurement resolution increases. To ensure minimum
effects on distortion measurements, keep the value of R5low. The distortion reading on the audio analyzer must
be divided by a factor of (R3+ R4)/R5, where R1= R2and R3= R4, to get the actual measured distortion of the
device under test. The values used for the LME49724 measurements were R1, R2, R3, R4= 1kΩand R5= 20Ω.
This technique is verified by duplicating the measurements with high closed-loop gain and/or making the
measurements at high frequencies. Doing so produces distortion components that are within the measurement
equipment’s capabilities.
18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49724
LME49724
www.ti.com
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
Figure 54. THD+N and IMD Distortion Test Circuit
PERFORMANCE VARIATIONS
The LME49724 has excellent performance with little variation across different supply voltages, load impedances,
and input configuration (single-ended or differential). Inspection of the THD+N vs Frequency and THD+N vs
Output Voltage performance graphs (See Typical Performance Characteristics reveals only minimal differences
with different load values. Figure 55 and Figure 56 below show the performance across different supply voltages
with the same output signal level and load. Figure 55 has plots at ±5V, ±12V, ±15V, and ±18V with a 3VRMS
output while Figure 56 has plots at ±12V, ±15V, and ±18V with a 10VRMS output. Both figures use a 600Ωload.
The performance for each different supply voltage under the same conditions is so similar it is nearly impossible
to discern the different plots lines.
Figure 55. THD+N vs FREQUENCY with RL= 600Ω
VOUT = 3VRMS, Differential Input, 80kHz BW
VS= ±5V, ±12V, ±15V, and ±18V
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LME49724
LME49724
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Figure 56. THD+N vs FREQUENCY with RL= 600Ω
VOUT = 10VRMS, Differential Input, 80kHz BW
VS= ±12V, ±15V, and ±18V
Whether the input configuration is single-ended or differential has only a minimal affect on THD+N performance
at higher audio frequencies or higher signal levels. For easy comparison, Figure 57 and Figure 58 are a
combination of the performance graphs found in Typical Performance Characteristics.
Figure 57. THD+N vs FREQUENCY with RL= 10kΩ
VOUT = 3VRMS, VS= ±15V, 80kHz BW
Single-ended and Differential Input
20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49724
LME49724
www.ti.com
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
Figure 58. THD+N vs OUTPUT VOLTAGE with RL= 10kΩ
f = 20Hz, 1kHz, 20kHz, VS= ±15V, 80kHz BW
Single-ended and Differential Input
Power Supply Rejection Ratio does not vary with load value nor supply voltage. For easy comparison, Figure 59
and Figure 60 below are created by combining performance graphs found in Typical Performance
Characteristics.
Figure 59. PSRR vs FREQUENCY with RL= 600Ω
VS= ±2.5V, ±15V, and ±18V, 80kHz BW
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LME49724
LME49724
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Figure 60. PSRR vs FREQUENCY with VS= ±15V
RL= 600Ω, 2kΩ, and 10kΩ, 80kHz BW
Although supply current may not be a critical specification for many applications, there is also no real variation in
supply current with no load or with a 600Ωload. This is a result of the extremely low offset voltage, typically less
than 1mV. Figure 61 shows the supply current under the two conditions with no real difference discernable.
Figure 61. Supply Current vs Supply Voltage
RL= No Load and 600Ω
22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49724
LME49724
www.ti.com
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
Demo Board Schematic
Figure 62. Demonstration Board Circuit
Build of Materials
Table 2. Reference Demo Board Bill of Materials
Designator Value Tolerance Part Description Comment
R1, R2, R3, R41kΩ1% 1/8W, 0603 Resistor
R5, R640.2Ω1% 1/8W, 0603 Resistor
C1, C21000pF 10% 0603, NPO Ceramic Capacitor, 50V
C3, C4, C8, C90.1μF –20%, +80% 0603, Y5V Ceramic Capacitor, 25V
C5, C610μF 20% Size C (6032), Tantalum Capacitor, 25V
C72700pF 10% 0805, NPO Ceramic Capacitor, 50V
U1LME49724MR
J1, J2, J3, J4SMA coaxial connector Inputs & Outputs
J50.100" 1x3 header, vertical mount VDD, VEE, GND
J6, J7, J8, J9, J10, Inputs, Outputs, VOCM,
0.100" 1x2 header, vertical mount
J11 Enable
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LME49724
LME49724
SNAS438A –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Rev Date Description
1.0 11/12/08 Initial release.
A 04/04/13 Changed layout of National Data Sheet to TI format.
24 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49724
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jun-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LME49724MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L49724
MR
LME49724MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L49724
MR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jun-2016
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LME49724MRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LME49724MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
4202561/G
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jun-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LME49724MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L49724
MR
LME49724MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L49724
MR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jun-2016
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LME49724MRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LME49724MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8 0.15
0.00
2.71
2.11
3.4
2.8 0.25
GAGE PLANE
1.27
0.40
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
9
TYP
6.2
5.8
1.7 MAX
A
NOTE 3
5.0
4.8
B4.0
3.8
www.ti.com
EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.71)
(3.4)
SOLDER MASK
OPENING
(1.3)
TYP
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
9
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.71)
(3.4)
BASED ON
0.125 THICK
STENCIL
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
9
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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