Order this deta sheet by MCM514Z56AID MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256K x 4 CMOS Dynamic RAM Static Column The MCM514258A is a 1.Op CMOS high-speed, dynamic random access memory. It is organized as 262,144 four-bit words and fabricated with CMOS sihcon-gate process technology. Advanced circuit design and fine line processing provide high petiormance, improved retiabihty, and low cost. The MCM514256A requires only nine address lines; row and column address inputs are multiplexed. The device is packaged in a standard 300-mil dual-in-line plastic package (DIP), a W-roil SOJ plastic package, and a 100-mil zig-zag in-tine plastic package (ZIPI. Three-State Data Output . . ~ . 0 Static Column Mode TTL-Compatible Inputs and Output ~ Onlv Refresh ~ Befo~e ~ Refresh Hidden Refresh 512 Cycle, 8 ms Refresh O Unlatched Data Out at Cycle End Allows Two Dimensional Fast Access Time (tRAC): MCM514256A-70= 70 ns (Max) MCM51425SA-60= 80 ns (Max) MCM51425BA-10= 100 ns (Max) . LOWActive Power Dissipation: MCM514258A-70 =440 mW (Max) MCM514258A-80 =365 mW (Max) CASE 886 MOTOROLA @MOTOROM INC., lW @ = DS~ (Replaces ADll~) BLOCK DIAGRAM I m b \ AO~ Al ~ nurrrn t NO.2 C1OCK GENERATOR~111 COLUMN ADORESS BUFFERS (9) --11 COLUMN 11' !0 nr~nnrn II I r, I !31W" ii - StNSt A6~ Al ~ AB~ AM 110GATING BUFFERS [9] Y . 19: _E `* ----512X4 ,> This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it ia advised that normal precautions be taken to avoid application of any voltaga higher than maximum rated voltages to this high-impadance circuit, a MOTOROLA 2 McM51mA B DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V k 10%, TA = O to 70C, Unless Othewise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Symbol Min Typ Max Unit Notes Vcc 4.5 5.0 5.5 v 1 Vss o 0 0 Logic High Voltage, All inputs vlH 2.4 -- 6.5 v Logic Low Voltaga, All Inputs vlL -1.0 - 0.8 v 1 1J,, " y;\:3G,i :?:;. ,.*?{-Sk, ,:*J. Characteristic Symbol VCC Power Supply Current MCM51425BA-70, tRC = 130 ns MCM51425BA-SO, tRC = 150 ns MCM51425BA-10, tRC = 180 ns Current During ~ tRC = 130 ns tRC = 150 ns tRC= 160 ns Output Leakage Current (~= Output Low Voltage (lOL =4.2 mA) Refresh Cycle .:+, ,... V) VIH, O V~Vout=5.5 Output High Voltage (IOH = -5 mA) CAPACITANCE Before ~ :: "$~:, .,. `~-.:,t~,,,, .. .It$a \ ,t~`,ist3) y,,,..' ~.~:.~.,$:, `~::l.y~ \,$\ >.! ,.... .:,3$ - (f= 1.0 MHz, TA =25Cl~~'~$'#V, \ $< ~rimater ,.,}<t .`~.::,,,, ~bi;?.$,." ~: >,.<, Input Capacitance .,$ ,& $!*'; :,,.. , ,\ ,... ,. .YI~.?,..:*,\.\.*. , ,+.:,.,r V) ,<~$%~ `"$ ...*, ::]R. \ ,s!: .SQ ,' "F:.,`;~,> ..i~} ?\-\\i.}it,, x~.'\$:~\'.! .,,,,. .~,i~;<. ,.:,,,. ~r 2 ~t, &:$<$ --,il{,, , "~'~i2.o ,;.:~ ,,"4..:,. ,, , ,,~: ~,' ICC3 \:* $:,~ .<?.. .*l,A**8. 60 .~,~.\\ .....'.. s ,.. .~,*-S..<.S* 70 >:*.,\ x$ -- ,%<,~,?$b> 60 VCC Power Supply \ @~i@/ `$ Notas *$:J .,: "t S,*$ *, ICC2 VCC Power Supply MCM514256A-70, MCM51425BA-80, MCM51425BA-10, Input Leakage Currant (O V=~ns6.5 Max \t::!` ,-.,i,~~.~'" -- -- -- Current During RAS only Refresh Cycles (~=VIH) tRC = 130 ns tRC = 150 ns tRC = 160 ns ---- Current During Static Column Mode Cycle (RAS = CS =VIL) ~,.~~~-' ~b. ,,,. `~. tsc =40'ns :.: .,, ~*:,:,. .?:.:\ ;.,' tsc = 45 ns ,,, ,>$$;$ ".*W ~,:.k, tsc = W ns .$h, ---- ..'. ,,: .;, ?{., :.l Current (Standby) (RAS = CS = VCC -0.2 V) ICC5 ~~, ,:, VCC Power Supply MCM514256A-70, MCM514258A-80, MCM514258A-10, Min Iccl ---- VCC Power Supply Current (Standby) (RAS =CS = VIH) VCC Powar Supply MCM514256A-70, MCM514258A-SO, MCM514258A-10, ,+~ ,>., ..$!$:, ii,,<,, $'.;,:.k~it.:t >C CHARACTERISTICS -- -- -- 60 50 40 - 1.0 -- -- -- 60 70 60 1CC6 mA mA 2 mA 2,4 mA mA 2 Ilkg(l) - 10 10 PA [lkg(0) - 10 10 pA VOH 2.4 - v vOL - 0.4 v Symbol Max Unit Notas ~n. 5 pF 3 7 pF 3 Periodically Sampled Rather Than 100% Tested) AO-A8 ------ -- G, RAS, CS, W Output Capacitance (~s Vl#~~&isable Output) DQO-DW Cout 7 pF 3 ,+. ,#. ~$ ,I?>,..>J'. NOTES: .,,~i:.:~+.$!:' 1. All voltages ref~(e~edrto VSS. 2. Current is a f&~~&of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open, 3. Capacita&~e~~red with a Boonton Meter or effective capacitance calculated from the equation: C= lAt/AV. 4. Meas$~'*@~th'6ne address transition per static column mode cycle. MCM514258A MOTOROLA 3 AC OPERATING CONDITIONS (VCC = 5.0 V f 10%, READ, WRITE, AND I Parameter I READ-WRITE I Symbol Random Read or Write Cycle Time tRELREL tRc Read-Write Cycle Time tRELREL tRMw McM51425sA-m Max Min Max - 150 - 160 - ns 5 1S5 - 2ffi - 245 - ns 5 - 45 - 55 - na -- 110 - 135 - ns ?+$ ~e~~., I tRAP - 70 - so -, 1~ I tCELQV I tCAC - 25 - 25 - tAVoV tAA - 35 - 40 to Output in Low-Z tsc .n.m" tRFl OV ~Afl fi,f VVLUV I tA,,A, -n Lv v I - I SE -" I -175 o - o - Output Buffer and Turn-Off Delay tCEH~ tOFF o 20 0 20 Output Data Hold Time from Column Address t~~ tAOH 5 - 5 Output Data Enable Time from Write Q,un\, I - 90 - I m 3 "50 toa -,,, , m -- - Transition Time (Rise and Fall) h ,,h, ,,, LL, 1tncunrl tRELREH ; Pulse Width (Static Column Mode) CS to RAS Hold Time m ~to ~ ~ Pulw = Pulse Width (Static Column Mode) ~ to ~ tRAs I tCELREH tRSH tRELCEH trcu -"", , tCELCEH tcs Width Delav Time tfi,., I tRCl =EU ! tm.efi -"mab ,LL" L" Hold Time tcFl CFU trsr I 70 "[- 7n. .- I I fime I ~ Precharge Time Etom I-- CS Precharge Time tmrl a,; I -nz~v I tafim -nfiu .+$'',,2:`+??2.:25 60 : I+i.li" ., j tcEuDcl ,$*DO ~"-1 :bnr ,Gr,nc L I .J. Precharge Time (Static Column Mode) Row Address Setup Time Row Address Hold Time I tCEHCEL: `i ~&N ,*wLg &ak&*cp tCE&~"# % . .! .,< ..:. tASR tA?$ -k ihsi e-. .. . , ,..~ ., ..\,p `:+ *:b\ !Pcl ,.- ,,. ,:(<-:~.?' `~~s:$ tCE~X Column Address SetuD Time Column Address Hold Time Write Address Hold Time Referen.\*';q,@ns tRE~ Column Address Hold Time Ref&nc~ to ,.,..1~,~,. ) *J.&), ~'...>!,.' \$+fJ ... m tR E~X ,',,, ., $ Column Address to ~~- Lea$~ke , ..,,,, . ~.~?~ , `t::,.,$.:. >\\. .,., ,,,,. >,2,> NOTES: tRAU , .-, , tame 1 .- R ?K ". I I _- 1 1 I 6 ns 11 -- ns IK ," -Insl I lm Io,ooo ns 100,OOO 100 100,OOO ns - 30 - ns - 100 - ns 10,OOO 30 10,OOO ns Im,ooo ~ 30 25 100,OOO na ns ,0 ,2 40 20 '50 ns 13 ~1- -' ns 15 - ns ns - _ 10 - 10 - o, - o - o - ns 10 - 10 . - 15 - ns I -- ,- 5 10 ,0 n 10 I n 15 - 15 - 20 - 55 - m - 75 - tAR 85 - 95 - 115 - 1 I 35 I - I 4ol- 6, 10 30 tcAH tRAL ns ns tAwR 1 tAVREH I 170j 10,OOO I I ~,$F9$?' ,$ ..- - X.3. ~* .$- -4*45$1 $*~<:p&, j ,1 `"J5 ~~t,- Io,ooo 1 `<*'!I<, r lM~~"5 ."",--::, 25 70 3 I :,,. q~''?r~ i;f'$'- +, o "P: "k ~:?:,>,. ;i~, -- ,.,>,,,,,, ., ~, -n 1`~ELCEL 1 RASI to Column Address Delav ~ I , - -- tcn RAS Pulse Width Max 130 tCEL~ m I-- Min 40 ] _ Time -RAS Precharge MCM5I4256A-10 Unit Notes Min" 100 I Access Time from Laat Write t AilA\l tAVAV Access Time from Column Address ~ Noted) ",,,., . . t tcRhA\Al 1 Static Column Mode Read-Write Cycle Time Access Time from CS Unless Otherwise MCM514256A-70 I Standard IAlternata I Access Time from RAS AND CHARACTERISTICS to 70C, (See Notes 1, -, z. 3. -,-.and .-. ~i, CYCLES Static Column Mode Cycle Time I TA=O I I 50/- a ns ns ns ns (continued) are reference levels for measuring timing of input signals. Transition timas are measured between VIH and VIL. 1. VIH min a~~~~$,~'ax 2. An ini~a~'~~ of 200@ is required after power-up followed by 8 ~ cycles before proper device operetion is guaranteed. 3. Th:,t~~*&h kme specification appties for all input signals. In addition to meeting the transition rate specification, all input signals must tr~sltl~n %etwean VI H and VI L (or between VI L and VI H) in a monotonic mannar. 4:i*W$urements ~~~~~spacifications tT = 5.0 ns. for tRC (rein) and tRMW (rein) are used only to indicate cycle time at which proper operation over the full temperature ~:t,~~kge (OCSTA S70C) is aesurad. `~$. "tieasured with a current Ioed equivalent to 2 ~L ( -200 @, +4 mA) loads and 100 pF with the data output trip points set at ,, V0H=2.O V and VOL=O.8 V. 7. Aesumas that tRCD StRCD (maX). 8. Assumes that tRCD ~tRCD (maX). 9. Assumes that tRAD =tRAD (meX). 10. Assumes that tLwAD =tLwAD (maX). (max) and/or tGz define the time at which the output achieves the open circuit condition and is not referenced to output voltage 11. ~FF levels. 12. Operation within the tRCD (maxi limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max} limit, then access time is controlled exclusively by tCAC. 13. Oparation within the tRAD (max) hmit ensures that tRAC (max) can be met. tRAD (max) ia specified as a reference point onl~ if tRAD is greater than the spacified tRAD (maX), then access time iS controlled exclusively by tAA. MOTOROLA 4 MCM514258A B B READ, WRITE. AND READ-WRITE -- CYCLES (Continued) Symbol McM51mA-70 McM51mA-so MCM51425SA-10 Parameter Unit Notes -- Column Address Hold Time Re ferenced to Standard Alternate Min Max Min Max Min Max tREHAX tAH 10 - 10 - 10 - ns 14 20 30 20 35 25 45 ns 15 -- tLwAD Last Write to Column Address Delay Time -- Last Write to Column Address Hold Time lMLAX]tAHLW Read Command SetuD Time Referenced to I Read Command Hold Time Referenced to ~5 "-,,. I tcruw m Read Command Hold Time Referenced to RAS mLAv ... , .",, I tnru tREH~ 1 1651 tRrc ,,-- tiM~Fl . . . ,--- 1 tRRM ,, . 1 Write Command Hold Time (Output Data Disable) tCEHWH Write Command Hold Time Referenced to. RAS tRELWH g5 I -Insl ol- - I ol- 0 I - Ins ol- ol- ol- ol- 0 I1 - Ins I 1 1 I 1 75 111111 [ ~CH 15 I - 15 1111 ~CR 55 I - *,\ 1 1 1 1 ol- I 20 - 75<$' `<~:b:+$~" ns ~Y.*,.,:: ,,.,,,,,. .,{-(,, ,.>, ! - ~ wLWH WP 15 - 15 Write Inactive Time WHWL WI 10 - 10 WLREH tRWL 20 - 20 20 - 20 o - q,~$$ `_ Write Command to RAS Lead Time Leed Time WLCEH tCWL Data In Setup Time tDVCEL tDS Data In Hold Time tCELDX tDH 15 - Data In Hold Time Referenced to ~ tRELDX tDHR 55 Refresh Period tRVRV tRFSH - - ** $$*,L,$ 8 +4;$ " ""_ :*:* Write Command Setup Time (Output Data Disable) WLCEL Wcs = `CELWL. tcwD tRELWL tRWD tAWD ~ to Write Delay (RW Cycle) to Write Delay (RW Cycle) Column Address to Write Delay Time = Setup Time for ~ ~ Hold Time for ~ ~ = Precharge to ~ Before RAS Refresh Before ~ = Refresh Active Time Precharge Time for ~ Before ~ tA~L o tRELcE ~.&&p<v:`" ....,. `o ,.':;,; o -- ns - ns - ns - ns 18 18 - 20 - ns - 75 - ns 8 - 8 ms - 0 - ns 17 55 _ 65 _ n5 ,7 `"3*&' - 110 - 135 - ns 17 . - 70 - In -- in -- n. - 30 - 30 - ns - o - ns - m - ns `& . 30 ," ..).;'~~::' $:~t. tREH@$~' .,$,t,:~pc o - o t&&~ 40 - 40 ~tCpT ns "' - `$$ghi - J @%>,% .+$j,wH~ - --,$?~~ *%:$6 "" *'.<*** .:: g 25 ,*..~.,,:,:*>,. ,. <j$,*..:*' ~ 25 ,.$..~$ .:,,,, ,,,., tCFI FI, &;&R T 10 ---- R--,..%W. I 1 - Write Command Pulse Width Write Command to ~ I 1 - I 85 ," 1 - 1 ns , 1 17 ," \ ~$+' ,i!;:< ,4,,), . t;, \ ?1 ):;:+3.> .. 3*) NOTES: . ` .>' ,?,i,. $$. 14. tAH must ,~e~e~?br a read cycle. 15. OperatiqWwti the tLWAD (,max) timit ensures that tALW (max) can be met. tLWAD (max) ia specified as a reference point onl~ if tLWAD controlled exclusively by tAA. is g(~~r<t~pn the specified tLWAD (max) timit, then access time iS 16. ~~~~At@H or tRcH must be satisfied for a read cycle. 17.+*~j'''~c5, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical ..$++$,~%racteristicsonly; if ~CS >~cs (rein) and ~CH Z~CH (rein), the cycle is an early write cycle and the data out pin will remain (high impedance) throughout the entire CyCle; if tcwD2tCwD (rein), tRwD 2tRwD (rein), and tAWD>tAWD (rein), the ~.~&@en CirCUit `~$ cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 18. These parameters are referenced to ~ Iesding edge in random write cycles and to ~ leading edge in late write or read-write cycles. MCM51425SA MOTOROLA 5 READ CYCLE `Rc~ ,. MOTOROU 6 McM51qA = CONTROLLED UTE WRITE CYCLE VIH- E VIL- VIHNOH Dao-oa3 VILNOL- McM51aA MOTOROLA 7 STATIC COLUMN MODE READ CYCLE VIH- m Vll - VIHADDRESSES VIL- VIHVILVIH- VILVIHVIL- VDH - VOL - MOTOROM 8. . .. . -., . McM51mA STATIC COLUMN VIH4 m MODE EARLY WRITE CYCLE (B) (~ is Don't Care) tRAsc r Vll - tASR+ e 1 4 - D ~'EADw'lTE4 *'EA""W"TE McM51mA MOTORO~ 9 STATIC COLUMN V[H- MODE READ/WRITE MIXED CYCLE 4k m VJL - tcsR--tcpN~ VIH- R E "L tcHR > 4 VILtoFF -- ~ VOH Doo-oa3 voL - 4 HIGH Z Q ,, MOTOROU 10 McM51mA HIDDEN $" VIH- REFRESH CYCLE (READ) t 000.003 ~lL- I D McM51mA' MOTORO~ 11 = BEFORE RAS REFRESH COUNTER TEST CYCLE VIHNOHDOO-D03 VILNoL - HIGH Z tCLz j * DATA OUT a MOTOROU 12 McM51mA B DEVICE INITIALIZATION On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight active cycles of the row address strobe [clock) to initialize all dynamic nodes within the RAM. During an extended inactive state (greater than 8 millisecondswith the device powered up), a wake up sequence of, eight active cycles is necessary to assure proper operation. ADDRESSING THE RAM The nine address pins on the device are time multiplexed at the beginning, of a memory cycle by the row address strobe (~) clock, into two separate 9-bit address fields. A total of eighteen address bits, nine rows and nine columns, will decode one of the 282,144 bit locations in the device, ~ active transition latches the row address field. Column addresses are not latched, hence the""static column" designation of this device. Chip select (~) active transition (active = VIL, tRCD minimum) follows RAS on all read, write, or read-write cycles, and is independent of column address. The static column feature allows greater flexibility in setiing up the external external column addresses into the RAM. There are two other variations in addressing the 2WK x 4 RAM: RAS only refresh cycle and ~ before RAS refresh cycle. Both are discussed in separate sections that follow. READ CYCLE When either the ~ or ~ clock transitions to inactive, the output Wiii switch to High Z, tOFF or tGZ after inactive transition. WRITE CYCLE The DRAM may be writien with any of four cycles: early write, late write and "static column mode" early write, and read-write. Earlyand late write modes are discussedhere, while static column mode write operations are covered in another section, .':\.:$,( A write cycle begins as described in AD DRESSINGi'~&mJ RAM. Write mode is enabled by the transition of ~$o~~t]ke (VIL level). Early and late write modes are distingu~~.~~the active transition of ~ with respect to ~ lea~~.@@. Minimum active time tRAS and tcs, and prech~$ti~"~Rp apply `:%**: to write mode, as in the read mode. ~.,$&, ..,:,,J*? An early write cycle is characterized;~,~ active transition at minimum time tWCS before ~ "Wtiv+~ransition. Column address set up and hold times (@*&]%cAH), and data in (D) set up and hold times (tDS,,,,fi F&% referenced to ~ in an early write cycle. ~ a@~;, ,i&locks must `stay active for # .~.',,> tRWL and tCWL, respe*$~~after the start of the early write operation to complw$the ~cle. Q remains High:<~<@ghout an early write cycle because ~ active trans~o~~r&edes or coincides with ~ active transition, kee~~~~&@~out buffers disabled effectively disabling ,?: E. .. . `"A 1~$.writecycle (referred to as ~ con~olled write) occurs ww& transition is made atier CS active transition. The DRAM may be read with four different cycles: random .@gc$@e tran@on could be delayed for almost 10 microseread cycle, read-write cycle, and "static column mode" read, ~m~s after CS active transition, (tRAD + tASC + tRWL+ and read-write. The, random read cycle is outlined here, while , *@TStRAS, if other timing minimums (tASC, tRWL, and tT) the other cycles are discussed in separate sections. ,.jp are maintained. Column address and D timing parameters are The random read cycle begins as described in ADDR~@referenced to ~ active transition in a late write cycle. Output ING THE RAM, with RAS active transition latching t% da buffers are enabled by ~ active transition but Q may be sired row. The write (~) input level must be high (~J#~&*s indeterminate-see note 17 of AC operating conditions table. (minimum) before the = active transition, to #@l@read Parameters tRWL and tCWL also apply to late write cycles. mode. A valid column address can be provid#.t~$.@~y time independent of the ~ ~*$ii;bnSitiOn. (tRAD minimUm), READ-WRITE CYCLE Both the RAS and ~ clocks trigger ~,s~b~hce of events A read-write cycle petiorms a read and then a write at the which are controlled by several dela,@ ~$~nai clocks. The same address, during the same cycle. This cycle is basically internal clocks are linked in such a:~~~~~~hat the read access a late write cycle, as discussed in the WRITE CYCLE section, time of the device is independ@t ~ the address multiplex >>, * ~: except ~ must remain high for tCWD and/OrtAWD minimum, window. Both ~ and outD@BMW (~) control read access to guarantee valid Q before writing the bit. time: ~ and ~ must be ,pct~~dnd column address must ba and' tRAC-tGA minimUm, respecvalid) by tRCD maXimA#$ STATIC COLUMN MODE CYCLES tively, to guarantee ~'ti~'~~ta out (Q) at tRAC (access time ,.3 J-. ~;.'. . from RAS activ~.~~%~lon). If either tRCD maximum is exStatic column mode refers to multiple successive data opceeded or ~ .Si{.,. a@~s$ransition does not occur in time, read erations petiormed at any or all 512 column locations on the access ti~~~w$et~rmined by the ~ and/or ~ clock active selected row of the 258x 4 dynamic RAM during one ~ transition *C~CYtGA). cycle. Read access time of multiple operations (t~ or tCAC) is considerably faster than the regular ~ clock access time Th@~w~&~d ~ clocks must remain active for a minimum ti~2~$of~sand tcs, respectively, to complete the read cycle. tRAC. Multiple operations can be performed simply by keeping Th~j@mn address must remain valid for tAH after RAS ~ active. ~ may be toggled between active and inactive ina~ve transition to complete the read cycle, ~ must remain states at any time within the RAS cycle. high throughout the cycle, and for time tRRH or tRCH after Once the timing requirements for the initial read, write, or RAS or ~ inactive transition, respectively, to maintain the read-write cycle are met and ~ remains low, the device is data at that bit location. Once ~ transitions to inactive, it ready for the next operation, Operations can be intermixed in must remain inactive for a minimum time of tRp to precharge any order, at any column address, subject to normal operating the internal device circuitw for the next active cvcle. Q isvalid, conditions previously described. Every write operation must but not latched, as long as the ~ and ~ clocks are active: be clocked with either ~ or~, as indicated in static column D McM51mA MOTOROU 13 mode early write cycle timing diagrams A and B. Column address and D timing parameters are referenced to the signal clocking the write operation. = must be toggled inactive (tCp) to petiorm a read operation atier an early write operation (to turn output on), as indicated in static column mode read/ write mixed cycle timing diagram. The maximum number of consecutive operations is limited by tRASC. The cycle ends when ~ transitions to inactive, REFRESH CYCLES The dynamic RAM design is based on capacitor charge storage for each bit in the array, This charge degrades with time and temperature, thus each bit must be periodically refreshad (recharged) to maintain the correct bit state. Bits in the MCM514258A require refresh every 8 milliseconds. Refresh is accomplished by cycling through the 512 row addresses in sequence within the specified refresh time, All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh impties a row refresh every 15,6 microseconds for the MCM51 4258A. Burst refresh, a refresh of all 512 rows consecutively, must be performed every 8 milliseconds on the MCM514258A. A normal read, write, or read-write operation to the RAM will refresh all the bits (2M) associated with the particular row decoded. Three other methods of refresh, RAS only refresh, ~ before RAS refresh, and hidden refresh are available on this device for greater system flexibility. RAS-Only Refresh that generates the row address to be refreshed. External address tinesare ignored during the automatic refresh cycle. The output buffer remains at the same state it was in during the previous cycle (hidden refresh). Hidden Refresh Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding ~ active at the end of a read or write cycle, while ~ cycles inactive for tRp and back to active, sta~ the hidden refresh. This is essentially the execution of a ~ before ~ refresh from a cycle in pro'$~ss .*,.:>;:,*..*:<$.:~ ~ (see Figure 1). ,:,,,~<:,.. ~'~~iij.>, , The internal refresh counter of this devi~~~@e tested with a ~ before RAS refresh coun~~'~$e~:' This test is petiormed with a read-write operati~@~~~$\#g the test, the internal refresh counter generates tti~~o~ .,..\& address, while the external address supplies the co@k address. The entire array is refreshed afier 512 test cy~~% indicated by the check data written in each ro~~@e&~C~ before RAS refresh counter test cycle tim~qfram. The test can be pe"@*d after a minimum of eight ~ before ~ initia~~ion'~)cles. Test procedure: ..~, , ~<~ 1. Write "~,'~~~~a~memory ,,e\. 2. ,,, cells with normal write mode. Select.@$,olu@n address, read "U' out and write"1" into the ~[~ ~~'performing the ~ before RAS refresh ~un% test, read-write cycle. Repeat this operation `~?~times. $S'"':aeati the"1 "s which were writien in step 2 in normal read ~-only refresh consists of ~ transition to active, latching "":.J$$.,,,> " `:i~~&ode. the row address to be refreshed, while ~ remains high (VIH) .y,~,.;. `~,~;~i Using the same column address as in step 2, read ."1" throughout the cycle. An external counter is employed to `~,,,> out and write "V' into the cell by petiorming the ~ ~,~~.. ensure all rows are refreshed within the specified .Iimit.~;y ,,. ~ before RAS refresh counter test, read-write cycle. ,,+ :3/,,, Repeat this operation 512 times. `i*, ,%2,$. `":i ~ Bafore RAS Refresh , .~y.,$t:ll ~.,.,.:,~,, 5. Read "W'S which were written at in"step 4 in normal read mode. ~ before ~ refresh is enabled bv bringing @~@;?&before Figure 1. Hidden Refresh Cycle MOTOROM 14 9 McM51mA 4 B ORDERING INFORMATION (Order by Full Pati Number) MCM Motorola Memo~ Prefix 51-A --T- I X XX XX - II k Full Pati Numbers- MCM5142WAP70 MCM514257APB0 MCM5142%AP1O MCM5142%AJ70 MCM5142%AJB0 MCM5142WAJ1O Shipping Method (R2 = Tape & Reel, Blank= Rails) Spead (70=70 ns, W=W ns, 10= 100 ns) Package (P= Plastic DIP, J = Plastic SO with J leads, Z= Plastic ZIP) ,,, *'X,l, $J,$<,. ,,. ,'~ ,'$:. `!(:,,: 1+ts., ,:w~bx ~< `:, ~ , , .$. J,\*,\ ,,., ,,X$.$+ .*.,,,?,i MCM5142~AJ70R2 MCM5142%AJWR2 MCM5142WAJ1OR2 MCM5142%~ ~$:-' MCM5142fl~ " MCM51$3*W ,hi,.s~~' ..:{. -'?/:,, ,, ?:,$>%<' $4, Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume anv Iiabilitv arising out of the application or use of anv product or circuit described herein; neither does it convev anv license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or svstems intended for surgical implant into the bodv or intended to support or sustain life. BuVer agrees to noti~ Motorola of anv such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and @ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Eaual Employment ODDortunitv/Ati rmative Action EmDlover. MCM51-A MOTOROU 15 ,. PACUGE a$ DIMENSIONS P PACWGE PUSTIC CASE ~A-01 rc ~~J I+ IO.25IO.O1O) @l -F DETAIL *D 1. DIMENSIONING AND TOLER~*~~iNSl Y14,5M, 1982, ..$(` ,..> .:JY 2. CONTROLLINGDIMENS~@~tfi~. 3. DIMENSION "~ T,Qm~R~LEAO WHEN FORMEDPARALL~&. i 20PL TI B@] PLASTIC CASE ~-~:"a~ ,, <::.,4s.,.,,.),$ .,.t,{.*,,,*.:,>, ,y:~ .~':~ ~.'. .~?.., .,.: ,J ,,>.?.:&,y,)s*~ ~,',.\.' Z 20PL 1+1 0.18 (0.007) @ I T I@ @]~~\ <W ~ D E F G H K L M N P R s 17,27 7.50 7.74 3.26 3.75 0.39 0,50 2,24 2.48 0.67 0.81 1.27 BSC - 0,50 0.89 I 1,14 `2.54 BSC 10" w 1,14 0.89 8.39 8.63 6,61 6.96 0,77 1.01 0,670 0,680 0.295 0,305 0.128 0.146 0.015 0,020 0.088 0,098 0,026 0.032 0.050 BSC - 0:020 0.035 I 0,045 0.100 Bsc p 10" 0.035 0,045 0.330 0.340 0.260 0,275 0,030 0,040 NOTES: 1. DIMENSIONINGANO TOLERANCINGPERANSI Y14.5M, 1982, 2. CONTROLLINGDIMENSION: INCH, 3. DIMENSIONA&800 NOT INCLUDE MOLD PROTRUSION,MOLD PROTRUSIONSHALL NOT EXCEED0.15 (0,0061PERSIOE, 4. OIM R TO BE DETERMINEDAT DATUM .T., 5. FORLEAD IDENTIFICATIONPURPOSES,PIN POSITIONS6,7,6,19, 20,&21 ARE NOT USED, 1. DIMENSIONING ANO TOLERANCINGPER ANSI Y14.5M, 1982, 2. CONTROLLINGDIMENSION: INCH, 3, DIMENSION `,H TO CENTEROF LEADWHEN FORMEDPARALLEL. 4, DIMENSIONS `,A, ,,5, ANO ,,s', Do NOT INCLUDE MOLD PROTRUSION, 5. MOLD FLASH OR PROTRUSIONSHALL NO1 EXCEED0.25 (0,010), Literature Distribution Centers: ( USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; P.O. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong. JAPAN: Nippon Motorola Ltd.; 3-20-1 Minamiazabu, Minato-ku, Tokyo 106 Japan, --