SST37VF010-70-3C-PHE - Microchip Technology, Inc.

S71151-10-000 5/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MTP is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit (x8)

Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FEATURES:

• Organized as 128K x8 / 256K x8 / 512K x8

• 2.7-3.6V Read Operation

• Superior Reliability

– Endurance: At least 1000 Cycles

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 10 mA (typical)

– Standby Current: 2 µA (typical)

• Fast Read Access Time:

– 70 ns

• Latched Address and Data

• Fast Byte-Program Operation:

– Byte-Program Time: 15 µs (typical)

– Chip Program Time:

2 seconds (typical) for SST37VF010

4 seconds (typical) for SST37VF020

8 seconds (typical) for SST37VF040

• Electrical Erase Using Programmer

– Does not require UV source

– Chip-Erase Time: 100 ms (typical)

• CMOS I/O Compatibility

• JEDEC Standard Byte-wide Flash

EEPROM Pinouts

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP

– Non-Pb (lead-free) packages available

PRODUCT DESCRIPTION

The SST37VF010/020/040 devices are 128K x8 / 256K x8

/ 512K x8 CMOS, Many-Time Programmable (MTP), low

cost flash, manufactured with SST’s proprietary, high per-

formance CMOS SuperFlash technology. The split-gate

cell design and thick-oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST37VF010/020/040 can be electrically

erased and programmed at least 1000 times using an

external programmer, e.g., to change the contents of

devices in inventory. The SST37VF010/020/040 have to be

erased prior to programming. These devices conform to

JEDEC standard pinouts for byte-wide flash memories.

Featuring high performance Byte-Program, the

SST37VF010/020/040 provide a typical Byte-Program time

of 15 µs. Designed, manufactured, and tested for a wide

spectrum of applications, these devices are offered with an

endurance of at least 1000 cycles. Data retention is rated at

greater than 100 years.

The SST37VF010/020/040 are suited for applications that

require infrequent writes and low power nonvolatile stor-

age. These devices will improve flexibility, efficiency, and

performance while matching the low cost in nonvolatile

applications that currently use UV-EPROMs, OTPs, and

mask ROMs.

To meet surface mount and conventional through hole

requirements, the SST37VF010/020/040 are offered in 32-

lead PLCC, 32-lead TSOP, and 32-pin PDIP packages.

See Figures 2, 3, and 4 for pin assignments.

Device Operation

The SST37VF010/020/040 devices are nonvolatile mem-

ory solutions that can be used instead of standard flash

devices if in-system programmability is not required. It is

functionally (Read) and pin compatible with industry stan-

dard flash products.The device supports electrical Erase

operation via an external programmer.

Read

The Read operation of the SST37VF010/020/040 is con-

trolled by CE# and OE#. Both CE# and OE# have to be low

for the system to obtain data from the outputs. Once the

address is stable, the address access time is equal to the

delay from CE# to output (TCE). Data is available at the out-

put after a delay of TOE from the falling edge of OE#,

assuming the CE# pin has been low and the addresses

have been stable for at least TCE-TOE. When the CE# pin is

high, the chip is deselected and a standby current of only 2

µA (typical) is consumed. OE# is the output control and is

used to gate data from the output pins. The data bus is in

high impedance state when either CE# or OE# is VIH. Refer

to Figure 5 for the timing diagram.

SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

Byte-Program Operation

The SST37VF010/020/040 are programmed by using an

external programmer. The programming mode is activated

by asserting 11.4-12V on OE# pin and VIL on CE# pin.

The device is programmed using a single pulse (WE# pin

low) of 15 µs per byte. Using the MTP programming algo-

rithm, the Byte-Program process continues byte-by-byte

until the entire chip has been programmed. Refer to Figure

11 for the flowchart and Figure 7 for the timing diagram.

Chip-Erase Operation

The only way to change a data from a “0” to “1” is by

electrical erase that changes every bit in the device to

“1”. The SST37VF010/020/040 use an electrical Chip-

Erase operation. The entire chip can be erased in 100

ms (WE# pin low). In order to activate erase mode, the

11.4-12V is applied to OE# and A9 pins while CE# is

low. All other address and data pins are “don’t care”.

The falling edge of WE# will start the Chip-Erase oper-

ation. Once the chip has been erased, all bytes must

be verified for FFH. Refer to Figure 10 for the flowchart

and Figure 6 for the timing diagram.

Product Identification Mode

The Product Identification mode identifies the devices as

SST37VF010, SST37VF020, and SST37VF040 and man-

ufacturer as SST. This mode may be accessed by the hard-

ware method. To activate this mode, the programming

equipment must force VH (11.4-12V) on address A9. Two

identifier bytes may then be sequenced from the device

outputs by toggling address line A0. For details, see Table 3

for hardware operation.

Design Considerations

The SST37VF010/020/040 should have a 0.1 µF ceramic

high frequency, low inductance capacitor connected

between VDD and GND. This capacitor should be placed as

close to the package terminals as possible.

OE# and A9 must remain stable at VH for the entire dura-

tion of an Erase operation. OE# must remain stable at VH

for the entire duration of the Program operation.

FIGURE 1: Functional Block Diagram

TABLE 1: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST37VF010 0001H C5H

SST37VF020 0001H C6H

SST37VF040 0001H C2H

T1.2 1151

Y-Decoder

I/O Buffers

1151 B1.1

Address Buffer

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 2: Pin Assignments for 32-lead PLCC

FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

A16

VDD

WE#

A12

A15

A16

VDD

WE#

A17

A12

A15

A16

A18

VDD

WE#

A17

32-lead PLCC

Top View

1151 32-plcc P02a.4

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

SST37VF010 SST37VF020 SST37VF040SST37VF040 SST37VF020 SST37VF010

1151 32-tsop P01.1

Standard Pinout

Top View

A11

A13

A14

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

SST37VF040 SST37VF020 SST37VF010 SST37VF010 SST37VF020 SST37VF040

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 4: Pin Assignments for 32-pin PDIP

Note: X = VIL or VIH (or VH in case of OE# and A9)

VH = 11.4-12V

TABLE 2: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

Address Inputs To provide memory addresses.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Program cycles.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

WE# Write Enable To program or erase (WE# = VIL pulse during Program or Erase)

OE# Output Enable To gate the data output buffers during Read operation when low

VDD Power Supply To provide 3.0V supply (2.7-3.6V)

VSS Ground

NC No Connection Unconnected pins.

T2.1 1151

TABLE 3: Operation Modes Selection

Mode CE# WE# A9OE# DQ Address

Read VIL VIH AIN VIL DOUT AIN

Output Disable VIL XX V

IH High Z AIN

Standby VIH X X X High Z X

Chip-Erase VIL VIL VHVHHigh Z X

Byte-Program VIL VIL AIN VHDIN AIN

Program/Erase Inhibit X VIH X X High Z X

XXXV

IL or VIH High Z/ DOUT X

Product Identification VIL VIH VHVIL Manufacturer’s ID (BFH)

Device ID1

1. Device ID = C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040

AMS2 - A1=VIL, A0=VIL

AMS2 - A1=VIL, A0=VIH

2. AMS = Most significant address

AMS = A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

T3.2 1151

32-pin

PDIP

Top View

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

SST37VF010 SST37VF020 SST37VF040

SST37VF040 SST37VF020 SST37VF010

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

1151 32-pdip P02b.2

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . “with-Pb” units1: 240°C for 3 seconds

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . “non-Pb” units: 260°C for 3 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Certain “with-Pb” package types are capable of 260°C for 3 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF

See Figures 8 and 9

TABLE 4: Read Mode DC Operating Characteristics VDD=2.7-3.6V (TA = 0°C to +70°C (Commercial))

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD VDD Read Current Address input=VILT/VIHT

, at f=1/TRC Min

VDD=VDD Max

12 mA CE#=VIL, OE#=VIHT

, all I/Os open

ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.3 V IOH=-100 µA, VDD=VDD Min

IHSupervoltage Current for A9200 µA CE#=OE#=VIL, A9=VH Max

T4.6 1151

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

TABLE 5: Program/Erase DC Operating Characteristics VDD=2.7-3.6V (TA = 25°C±5°C)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD VDD Erase or Program Current 20 mA CE#=VIL, OE#=VH, VDD=VDD Max, WE#=VIL

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VHSupervoltage for A9 and OE# 11.4 12 V

IHA9 Supervoltage Current for A9200 µA OE#=VH Max, A9=VH Max,

VDD=VDD Max, CE# = VIL

IHOE# Supervoltage Current for OE# 3 mA CE#=VIL, OE#=11.4-12V,

VDD=VDD Max, WE#=VIL

T5.2 1151

TABLE 6: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T6.1 1151

TABLE 7: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 1151

TABLE 8: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.3 1151

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

AC CHARACTERISTICS

TABLE 9: Read Cycle Timing Parameters VDD = 2.7-3.6V (TA = 0°C to +70°C (Commercial))

Symbol Parameter

SST37VF010-70

SST37VF020-70

SST37VF040-70

UnitsMin Max

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 25 ns

TOHZ1OE# High to High-Z Output 25 ns

TOH1Output Hold from Address Change 0 ns

T9.3 1151

TABLE 10: Program/Erase Cycle Timing Parameters VDD = 2.7-3.6V (TA = 25°C±5°C)

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TCES CE# Setup Time 1 µs

TCEH CE# Hold Time 1 µs

TAS Address Setup Time 1 µs

TAH Address Hold Time 1 µs

TDS Data Setup Time 1 µs

TDH Data Hold Time 1 µs

TPRT OE# Rise Time for Program and Erase 50 ns

TVPS OE# Setup Time for Program and Erase 1 µs

TVPH OE# Hold Time for Program and Erase 1 µs

TPW WE# Program Pulse Width 15 25 µs

TEW WE# Erase Pulse Width 100 200 ms

TVR OE#/A9 Recovery Time for Erase 1 µs

TART A9 Rise Time to 12V during Erase 50 ns

TA9S A9 Setup Time during Erase 1 µs

TA9H A9 Hold Time during Erase 1 µs

T10.1 1151

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 5: Read Cycle Timing Diagram

FIGURE 6: Chip-Erase Timing Diagram

1151 F03.0

ADDRESS

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

1151 F04.0

TA9H

TVR

TVPH

TVPS

TCEH

TPRT

VDD

VSS

OE#

WE#

VIH

VIL

DQ7-0

CE#

ADDRESS

(EXCEPT A9)

TA9S

TART

TCES

TEW

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 7: Byte-Program Timing Diagram

1151 F05.0

DATA VALID

ADDRESS VALID

TAH

TCEH

TAS

TDS

TDH

VDD

HIGH-Z

VSS

TCES

TPW

TVPH

TPRT

TVPS

OE#

WE#

DQ7-0

CE#

ADDRESS

TPC

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 8: AC Input/Output Reference Waveforms

FIGURE 9: A Test Load Example

1151 F06.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 V) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1151 F07.1

TO TESTER

TO DUT

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 10: Chip-Erase Algorithm

Start

A9 = VH, OE# = VH

OE#/A9 = VIL or VIH

CE# = VIL

Wait TVR Recovery Time

Erase 100ms pulse

(WE# = VIL)

Read Device

Device Passed

Compare all

bytes to FF

Device Failed

1151 F08.0

WE# = VIH

Ye s

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 11: Byte-Program Algorithm

*See Figure 10

Start

Erase*

OE# = VH

Address = First Location;

Load Data

CE# = VIL

OE# = VIL

Program 15 µs pulse

(WE# = VIL)

Read Device

Device Passed

Compare all bytes

to original data

Increment Address

Device Failed

1151 F09.2

Last Address?

Wait TVR

Ye s

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

PRODUCT ORDERING INFORMATION

Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC

P = PDIP

W = TSOP (type 1, die up, 8mm x 14mm)

Operating Temperature

C = Commercial = 0° to +70°C

Minimum Endurance

3 = 1,000 cycles

Read Access Speed

70 = 70 ns

Device Density

040 = 4 Mbit

020 = 2 Mbit

010 = 1 Mbit

Voltage

V = 2.7-3.6V

Product Series

37 = Many-Time Programmable Flash

Flash memories with flash pinout

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 37 VF 040 - 70 - 3C - NH E

XX XX XXXX - XXX -XX-XXX X

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

Valid combinations for SST37VF010

SST37VF010-70-3C-NHE SST37VF010-70-3C-WHE SST37VF010-70-3C-PHE

Valid combinations for SST37VF020

SST37VF020-70-3C-NHE SST37VF020-70-3C-WHE SST37VF020-70-3C-PHE

Valid combinations for SST37VF040

SST37VF040-70-3C-NHE SST37VF040-70-3C-WHE SST37VF040-70-3C-PHE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

*Not recommended for new designs.

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

PACKAGING DIAGRAMS

FIGURE 12: 32-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30°

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 13: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

SST Package Code: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0°- 5°

DETAIL

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

FIGURE 14: 32-pin Plastic Dual In-line Pins (PDIP)

SST Package Code: PH

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7°

4 PLCS.

.600 BSC

.100 BSC

.150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065

1.655

1.645

.012

.008

.625

.600

.550

.530

Data Sheet

1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash

SST37VF010 / SST37VF020 / SST37VF040

TABLE 11: Revision History

Number Description Date

02 •2002 Data Book Feb 2002

03 •Part number changes - see page 14 for additional information

•Clarified the Test Conditions for VDD Read Current parameter in Table 4 on page 5

– Address input = VILT/VIHT

– CE#=OE#=VILT

Mar 2003

04 •2004 Data Book

•Added non-Pb MPNs and removed footnote (See page 14)

Nov 2003

05 •Removed 90 ns parts, related footnote, and MPNs (See page 14)

•Added 70 ns parts and MPNs for the PH package

•Changed Byte-Program time from 10 µs to 15 µs

•Updated chip program times

•Separated Supervoltage Current for A9 and OE# in Table 5 on page 6

May 2004

06 •Added non-Pb 32-PDIP MPNs for 1, 2, and 4 Mbit devices

•Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on

page 5

Dec 2004

07 •Changed program voltage from 12.6V to 12V globally Aug 2006

08 •EOLed all valid combinations of SST37VF512, See S71151(03).

•Removed 64K x 8 organization and leaded parts

Apr 2007

09 •File name correction Apr 2008

10 •Fixed mistake in document status by removing “EOL” May 2008

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036