1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories Data Sheet FEATURES: * Organized as 128K x8 / 256K x8 / 512K x8 * 2.7-3.6V Read Operation * Superior Reliability - Endurance: At least 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) - Standby Current: 2 A (typical) * Fast Read Access Time: - 70 ns * Latched Address and Data * Fast Byte-Program Operation: - Byte-Program Time: 15 s (typical) - Chip Program Time: 2 seconds (typical) for SST37VF010 4 seconds (typical) for SST37VF020 8 seconds (typical) for SST37VF040 * Electrical Erase Using Programmer - Does not require UV source - Chip-Erase Time: 100 ms (typical) * CMOS I/O Compatibility * JEDEC Standard Byte-wide Flash EEPROM Pinouts * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 32-pin PDIP - Non-Pb (lead-free) packages available PRODUCT DESCRIPTION The SST37VF010/020/040 devices are 128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the SST37VF010/020/040 provide a typical Byte-Program time of 15 s. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST37VF010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. (c)2008 Silicon Storage Technology, Inc. S71151-10-000 5/08 1 To meet surface mount and conventional through hole requirements, the SST37VF010/020/040 are offered in 32lead PLCC, 32-lead TSOP, and 32-pin PDIP packages. See Figures 2, 3, and 4 for pin assignments. Device Operation The SST37VF010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.The device supports electrical Erase operation via an external programmer. Read The Read operation of the SST37VF010/020/040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a standby current of only 2 A (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is VIH. Refer to Figure 5 for the timing diagram. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Byte-Program Operation Product Identification Mode The SST37VF010/020/040 are programmed by using an external programmer. The programming mode is activated by asserting 11.4-12V on OE# pin and VIL on CE# pin. The device is programmed using a single pulse (WE# pin low) of 15 s per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-by-byte until the entire chip has been programmed. Refer to Figure 11 for the flowchart and Figure 7 for the timing diagram. The Product Identification mode identifies the devices as SST37VF010, SST37VF020, and SST37VF040 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (11.4-12V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. Chip-Erase Operation TABLE 1: Product Identification The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". The SST37VF010/020/040 use an electrical ChipErase operation. The entire chip can be erased in 100 ms (WE# pin low). In order to activate erase mode, the 11.4-12V is applied to OE# and A9 pins while CE# is low. All other address and data pins are "don't care". The falling edge of WE# will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 10 for the flowchart and Figure 6 for the timing diagram. Address Data 0000H BFH SST37VF010 0001H C5H SST37VF020 0001H C6H SST37VF040 0001H C2H Manufacturer's ID Device ID T1.2 1151 Design Considerations The SST37VF010/020/040 should have a 0.1 F ceramic high frequency, low inductance capacitor connected between VDD and GND. This capacitor should be placed as close to the package terminals as possible. OE# and A9 must remain stable at VH for the entire duration of an Erase operation. OE# must remain stable at VH for the entire duration of the Program operation. X-Decoder Memory Address SuperFlash Memory Address Buffer Y-Decoder CE# OE# A9 WE# I/O Buffers Control Logic DQ7 - DQ0 1151 B1.1 FIGURE 1: Functional Block Diagram (c)2008 Silicon Storage Technology, Inc. S71151-10-000 2 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 A17 A17 NC WE# WE# WE# VDD VDD VDD A18 NC NC A16 A16 A16 A15 A15 A15 A12 A12 A12 SST37VF010 SST37VF020 SST37VF040 Data Sheet 4 3 2 1 32 31 30 29 SST37VF040 SST37VF020 SST37VF010 SST37VF010 SST37VF020 SST37VF040 A7 A7 5 A14 A14 A14 A6 A6 A6 6 28 A13 A13 A13 A5 A5 A5 7 27 A8 A8 A8 A4 A4 A4 8 26 A9 A9 A9 A3 A3 A3 9 25 A11 A11 A11 A2 A2 A2 10 24 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 32-lead PLCC Top View DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ2 VSS DQ3 DQ4 DQ5 DQ6 1151 32-plcc P02a.4 DQ1 SST37VF040 SST37VF020 SST37VF010 A7 FIGURE 2: Pin Assignments for 32-lead PLCC SST37VF040 SST37VF020 SST37VF010 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST37VF010 SST37VF020 SST37VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1151 32-tsop P01.1 FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) (c)2008 Silicon Storage Technology, Inc. S71151-10-000 3 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet SST37VF010 SST37VF020 SST37VF040 SST37VF040 SST37VF020 SST37VF010 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1151 32-pdip P02b.2 FIGURE 4: Pin Assignments for 32-pin PDIP TABLE 2: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. WE# Write Enable To program or erase (WE# = VIL pulse during Program or Erase) OE# Output Enable To gate the data output buffers during Read operation when low VDD Power Supply To provide 3.0V supply (2.7-3.6V) VSS Ground NC No Connection Unconnected pins. T2.1 1151 1. AMS = Most significant address AMS = A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040 TABLE 3: Operation Modes Selection Mode CE# WE# A9 OE# Read VIL VIH AIN VIL Output Disable VIL X X VIH High Z AIN Standby VIH X X X High Z X Chip-Erase VIL VIL VH VH High Z X Byte-Program VIL VIL AIN VH DIN AIN X VIH X X High Z X X X X VIL or VIH High Z/ DOUT X VIL VIH VH VIL Manufacturer's ID (BFH) Device ID1 AMS2 - A1=VIL, A0=VIL AMS2 - A1=VIL, A0=VIH Program/Erase Inhibit Product Identification DQ Address DOUT AIN T3.2 1151 1. Device ID = C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040 2. AMS = Most significant address AMS = A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040 Note: X = VIL or VIH (or VH in case of OE# and A9) VH = 11.4-12V (c)2008 Silicon Storage Technology, Inc. S71151-10-000 4 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . "with-Pb" units1: 240C for 3 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "non-Pb" units: 260C for 3 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Certain "with-Pb" package types are capable of 260C for 3 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range AC CONDITIONS OF TEST Ambient Temp VDD 0C to +70C 2.7-3.6V Commercial Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 8 and 9 TABLE 4: Read Mode DC Operating Characteristics VDD=2.7-3.6V (TA = 0C to +70C (Commercial)) Limits Symbol Parameter IDD VDD Read Current ISB Standby VDD Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max 12 mA CE#=VIL, OE#=VIHT, all I/Os open 15 A CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage IH Supervoltage Current for A9 V VDD=VDD Max 0.2 V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min 200 A CE#=OE#=VIL, A9=VH Max VDD-0.3 T4.6 1151 (c)2008 Silicon Storage Technology, Inc. S71151-10-000 5 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 5: Program/Erase DC Operating Characteristics VDD=2.7-3.6V (TA = 25C5C) Limits Symbol Parameter IDD VDD Erase or Program Current Min Max Units 20 mA Test Conditions CE#=VIL, OE#=VH, VDD=VDD Max, WE#=VIL ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VH Supervoltage for A9 and OE# IHA9 Supervoltage Current for A9 IHOE# Supervoltage Current for OE# 11.4 12 V 200 A OE#=VH Max, A9=VH Max, VDD=VDD Max, CE# = VIL 3 mA CE#=VIL, OE#=11.4-12V, VDD=VDD Max, WE#=VIL T5.2 1151 TABLE 6: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Write Operation 100 s TPU-WRITE 1 T6.1 1151 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T7.0 1151 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: Reliability Characteristics Symbol Parameter NEND1 Endurance TDR 1 ILTH1 Minimum Specification Data Retention Latch Up Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T8.3 1151 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2008 Silicon Storage Technology, Inc. S71151-10-000 6 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters VDD = 2.7-3.6V (TA = 0C to +70C (Commercial)) SST37VF010-70 SST37VF020-70 SST37VF040-70 Symbol Parameter Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 CE# Low to Active Output 0 ns OE# Low to Active Output 0 ns 70 ns CE# High to High-Z Output 25 ns OE# High to High-Z Output 25 ns Output Hold from Address Change 0 ns T9.3 1151 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Program/Erase Cycle Timing Parameters VDD = 2.7-3.6V (TA = 25C5C) Symbol Parameter Min Max Units TBP Byte-Program Time TCES CE# Setup Time TCEH CE# Hold Time 1 s TAS Address Setup Time 1 s TAH Address Hold Time 1 s TDS Data Setup Time 1 s TDH Data Hold Time 1 s TPRT OE# Rise Time for Program and Erase 50 ns TVPS OE# Setup Time for Program and Erase 1 s TVPH OE# Hold Time for Program and Erase 1 s TPW WE# Program Pulse Width 15 25 s TEW WE# Erase Pulse Width 100 200 ms 20 s 1 s TVR OE#/A9 Recovery Time for Erase 1 s TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 s TA9H A9 Hold Time during Erase 1 s T10.1 1151 (c)2008 Silicon Storage Technology, Inc. S71151-10-000 7 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TAA TRC ADDRESS TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ DATA VALID HIGH-Z DATA VALID 1151 F03.0 FIGURE 5: Read Cycle Timing Diagram ADDRESS (EXCEPT A9) CE# TCEH DQ7-0 VH OE# TVPS VDD VSS TVPH TPRT VH TVR TA9S A9 VIH VIL TART TA9H TEW WE# TCES 1151 F04.0 FIGURE 6: Chip-Erase Timing Diagram (c)2008 Silicon Storage Technology, Inc. S71151-10-000 8 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TPC ADDRESS ADDRESS VALID TAH TAS CE# TCEH TDS TDH DQ7-0 DATA VALID HIGH-Z VH VDD OE# TVPS TPRT TPW VSS TVPH WE# TCES 1151 F05.0 FIGURE 7: Byte-Program Timing Diagram (c)2008 Silicon Storage Technology, Inc. S71151-10-000 9 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1151 F06.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 V) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 8: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1151 F07.1 FIGURE 9: A Test Load Example (c)2008 Silicon Storage Technology, Inc. S71151-10-000 10 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Start A9 = VH, OE# = VH CE# = VIL Erase 100ms pulse (WE# = VIL) WE# = VIH OE#/A9 = VIL or VIH Wait TVR Recovery Time Read Device Compare all bytes to FF No Yes Device Passed Device Failed 1151 F08.0 FIGURE 10: Chip-Erase Algorithm (c)2008 Silicon Storage Technology, Inc. S71151-10-000 11 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Start Erase* OE# = VH Address = First Location; Load Data CE# = VIL Program 15 s pulse (WE# = VIL) Increment Address Last Address? No OE# = VIL Yes Wait TVR Read Device Compare all bytes to original data No Yes Device Passed Device Failed 1151 F09.2 *See Figure 10 FIGURE 11: Byte-Program Algorithm (c)2008 Silicon Storage Technology, Inc. S71151-10-000 12 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet PRODUCT ORDERING INFORMATION SST 37 XX VF 040 XX XXXX - 70 - XXX - 3C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Operating Temperature C = Commercial = 0 to +70C Minimum Endurance 3 = 1,000 cycles Read Access Speed 70 = 70 ns Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit Voltage V = 2.7-3.6V Product Series 37 = Many-Time Programmable Flash Flash memories with flash pinout 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". (c)2008 Silicon Storage Technology, Inc. S71151-10-000 13 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Valid combinations for SST37VF010 SST37VF010-70-3C-NHE SST37VF010-70-3C-WHE SST37VF010-70-3C-PHE Valid combinations for SST37VF020 SST37VF020-70-3C-NHE SST37VF020-70-3C-WHE SST37VF020-70-3C-PHE Valid combinations for SST37VF040 SST37VF040-70-3C-NHE SST37VF040-70-3C-WHE SST37VF040-70-3C-PHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. * Not recommended for new designs. (c)2008 Silicon Storage Technology, Inc. S71151-10-000 14 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 FIGURE 12: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH (c)2008 Silicon Storage Technology, Inc. S71151-10-000 15 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 FIGURE 13: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH (c)2008 Silicon Storage Technology, Inc. S71151-10-000 16 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .100 BSC .022 .016 .150 .120 0 15 .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 FIGURE 14: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH (c)2008 Silicon Storage Technology, Inc. S71151-10-000 17 5/08 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 11: Revision History Number Description Date 02 * 2002 Data Book 03 * * 04 * * 2004 Data Book Added non-Pb MPNs and removed footnote (See page 14) Nov 2003 05 * * * * * Removed 90 ns parts, related footnote, and MPNs (See page 14) Added 70 ns parts and MPNs for the PH package Changed Byte-Program time from 10 s to 15 s Updated chip program times Separated Supervoltage Current for A9 and OE# in Table 5 on page 6 May 2004 06 * * Added non-Pb 32-PDIP MPNs for 1, 2, and 4 Mbit devices Clarified the solder temperature profile under "Absolute Maximum Stress Ratings" on page 5 Dec 2004 07 * Changed program voltage from 12.6V to 12V globally Aug 2006 08 * * EOLed all valid combinations of SST37VF512, See S71151(03). Removed 64K x 8 organization and leaded parts Apr 2007 09 * File name correction Apr 2008 10 * Fixed mistake in document status by removing "EOL" May 2008 Feb 2002 Part number changes - see page 14 for additional information Clarified the Test Conditions for VDD Read Current parameter in Table 4 on page 5 - Address input = VILT/VIHT - CE#=OE#=VILT Mar 2003 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2008 Silicon Storage Technology, Inc. S71151-10-000 18 5/08