TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Complete PWM Power Control
D
3.6-V to 40-V Operation
D
Internal Undervoltage-Lockout Circuit
D
Internal Short-Circuit Protection
D
Oscillator Frequency . . . 20 kHz to 500 kHz
D
Variable Dead Time Provides Control Over
Total Range
D
±3% Tolerance on Reference Voltage
(TL5001A)
D
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The TL5001 and TL5001A incorporate on a single
monolithic chip all the functions required for a
pulse-width-modulation (PWM) control circuit. De-
signed primarily for power-supply control, the
TL5001/A contains an error amplifier, a regulator, an
oscillator, a PWM comparator with a dead-time-con-
trol input, undervoltage lockout
(UVLO), short-circuit protection (SCP), and an open-collector output transistor. The TL5001A has a typical
reference voltage tolerance of ±3% compared to ±5% for the TL5001.
The error-amplifier common-mode voltage ranges from 0 V to 1.5 V. The noninverting input of the error amplifier
is connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by connecting
an external resistor between DTC and GND. The oscillator frequency is set by terminating RT with an external
resistor to GND. During low VCC conditions, the UVLO circuit turns the output off until VCC recovers to its normal
operating range.
The TL5001C and TL5001AC are characterized for operation from –20°C to 85°C. The TL5001I and TL5001AI are
characterized for operation from –40°C to 85°C. The TL5001Q and TL5001AQ are characterized for operation from
–40°C to 125°C. The TL5001M and TL5001AM are characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TASMALL OUTLINE
(D) PLASTIC DIP
(P) CERAMIC DIP
(JG) CHIP CARRIER
(FK)
20°Cto85°C
TL5001CD TL5001CP — —
–
20°C
to
85°C
TL5001ACD TL5001ACP — —
40°Cto85°C
TL5001ID TL5001IP — —
–
40°C
to
85°C
TL5001AID TL5001AIP — —
40°Cto125°C
TL5001QD — — —
–
40°C
to
125°C
TL5001AQD — — —
55°Cto125°C
— — TL5001MJG TL5001MFK
–
55°C
to
125°C
— — TL5001AMJG TL5001AMFK
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL5001CDR).
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
OUT
VCC
COMP
FB
GND
RT
DTC
SCP
D, JG OR P PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
RT
NC
DTC
NC
NC
VCC
NC
COMP
NC
NC
OUT
NC
GND
NC
FB
NC
SCP
NC
NC
FK PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic for typical application
TL5001/A
FB
COMP
VO
DTC
RT
VI+
SCP
VCC
+
TPS1101
GND
8
7
6
5
2
1
3
4
VO
functional block diagram
GND
8
OUT
SCP
COMP
FB
5
3
4–
+
DTC
RT 67
Comparator 2
SCP
PWM/DTC
Comparator
OSC
Comparator 1
SCP
Amplifier
Error
UVLO
VCC
21
1 V
1.5 V 1 V
Reference
Voltage
IDT
2.5 V
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
voltage reference
A 2.5-V regulator operating from VCC is used to power the internal circuitry of the TL5001 and TL5001A and as a
reference for the error amplifier and SCP circuits. A resistive divider provides a 1-V reference for the error amplifier
noninverting input which typically is within 2% of nominal over the operating temperature range.
error amplifier
The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and generates
an error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting the error-amplifier
gain (see Figure 1), using the following expression:
VO = (1 + R1/R2) (1 V)
To PWM
Comparator
Vref = 1 V
4
VI(FB)
3
+
–
R2
R1
COMP
FB
Compensation
Network
TL5001/A
GND
8
Figure 1. Error-Amplifier Gain Setting
The error-amplifier output is brought out as COMP for use in compensating the dc-to-dc converter control loop for
stability. Because the amplifier can only source 45 µA, the total dc load resistance should be 100 kΩ or more.
oscillator/PWM
The oscillator frequency (fosc) can be set between 20 kHz and 500 kHz by connecting a resistor between RT and
GND. Acceptable resistor values range from 15 kΩ to 250 kΩ. The oscillator frequency can be determined by using
the graph shown in Figure 5.
The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value of
approximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input voltage
to the triangular wave and turns the output transistor off whenever the triangular wave is greater than the lesser of
the two inputs.
dead-time control (DTC)
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for boost
and flyback converters. A current source generates a reference current (IDT) at DTC that is nominally equal to the
current at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates a dead-time
reference voltage (VDT), which the PWM/DTC comparator compares to the oscillator triangle wave as described
in the previous section. Nominally, the maximum duty cycle is 0% when VDT is 0.7 V or less and 100% when VDT
is 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the source impedance of
RT is relatively high (1250 Ω), choosing RDT for a specific maximum duty cycle, D, is accomplished using the
following equation and the voltage limits for the frequency in question as found in Figure 1 1 (V oscmax and Voscmin
are the maximum and minimum oscillator levels):
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dead-time control (DTC) (continued)
RDT
+ǒ
Rt
)
1250
Ǔƪ
D
ǒ
Voscmax –Voscmin
Ǔ)
Voscmin
ƫ
Where
RDT and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (CDT) as shown in Figure 2. During
soft start, the voltage at DTC is derived by the following equation:
VDT
[
IDTRDT
ǒ
1–e
ǒ
–t
ń
RDTCDT
ǓǓ
TL5001/A
DTC
CDT RDT
6
Figure 2. Soft-Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RDTCDT, should
be t0/3 to t0/5. The TL5001/A remains off until VDT ≈ 0.7 V , the minimum ramp value. CDT is discharged every time
UVLO or SCP becomes active.
undervoltage-lockout (UVLO) protection
The undervoltage-lockout circuit turns the output transistor off and resets the SCP latch whenever the supply voltage
drops too low (approximately 3 V at 25°C) for proper operation. A hysteresis voltage of 200 mV eliminates false
triggering on noise and chattering.
short-circuit protection (SCP)
The TL5001/A includes short-circuit protection (see Figure 3), which turns the power switch off to prevent damage
when the converter output is shorted. When activated, the SCP prevents the switch from being turned on until the
internal latching circuit is reset. The circuit is reset by reducing the input voltage until UVLO becomes active or until
the SCP terminal is pulled to ground externally.
When a short circuit occurs, the error-amplifier output at COMP rises to increase the power-switch duty cycle in an
attempt to maintain the output voltage. SCP comparator 1 starts an RC timing circuit when COMP exceeds 1.5 V.
If the short is removed and the error-amplifier output drops below 1.5 V before time out, normal converter operation
continues. If the fault is still present at the end of the time-out period, the timer sets the latching circuit and turns
off the TL5001/A output transistor.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-circuit protection (SCP) (continued)
Q1
12 kΩ
185 kΩ
RSCP
Q2
SCP
Comparator 2
Vref = 1 V
SCP
Comparator 1
1.5 V
From Error
Amp
CSCP
To Output
Drive Logic
SCP
5
2.5 V
Figure 3. SCP Circuit
The timer operates by charging an external capacitor (CSCP), connected between the SCP terminal and ground,
towards 2.5 V through a 185-kΩ resistor (RSCP). The circuit begins charging from an initial voltage of approximately
185 mV and times out when the capacitor voltage reaches 1 V. The output of SCP comparator 2 then goes high,
turns on Q2, and latches the timer circuit. The expression for setting the SCP time period is derived from the following
equation:
VSCP
+
(2.5
*
0.185)
ǒ
1
*
e–t
ń
t
Ǔ)
0.185
Where
τ = RSCPCSCP
The end of the time-out period, tSCP, occurs when VSCP = 1 V. Solving for CSCP yields:
CSCP
+
12.46
tSCP
Where
t is in seconds, C in µF.
tSCP must be much longer (generally 10 to 15 times) than the converter start-up period or the converter will not start.
output transistor
The output of the TL5001/A is an open-collector transistor with a maximum collector current rating of 21 mA and
a voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is lower
than both the DTC voltage and the error-amplifier output voltage, the UVLO circuit is inactive, and the short-circuit
protection circuit is inactive.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 41 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier input voltage, VI(FB) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO, OUT 51 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO, OUT 21 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output peak current, IO(peak), OUT 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating ambient temperature range, TA: TL5001C, TL5001AC –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . .
TL5001I, TL5001AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . .
TL5001Q, TL5001AQ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . .
TL5001M, TL5001AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW 145 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P1000 mW 8.0 mW/°C640 mW 520 mW 200 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VCC 3.6 40 V
Amplifier input voltage, VI(FB) 0 1.5 V
Output voltage, VO, OUT 50 V
Output current, IO, OUT 20 mA
COMP source current 45 µA
COMP dc load resistance 100 kΩ
Oscillator timing resistor, Rt15 250 kΩ
Oscillator frequency, fosc 20 500 kHz
TL5001C, TL5001AC –20 85
O
p
erating ambient tem
p
erature TA
TL5001I, TL5001AI –40 85
°C
Operating
ambient
temperature
,
T
ATL5001Q, TL5001AQ –40 125
°C
TL5001M, TL5001AM –55 125
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 100 kHz (unless otherwise noted)
reference
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Output voltage COMP connected to FB 0.95 1 1.05 0.97 1 1.03 V
Input regulation VCC = 3.6 V to 40 V 2 12.5 2 12.5 mV
TA = –20°C to 25°C (C suffix) –10 –1 10 –10 –1 10
Output voltage change with temperature TA = –40°C to 25°C (I suffix) –10 –1 10 –10 –1 10 mV/V
TA = 25°C to 85°C–10 –2 10 –10 –2 10
†All typical values are at TA = 25°C.
undervoltage lockout
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Upper threshold voltage TA = 25°C 3 3 V
Lower threshold voltage TA = 25°C 2.8 2.8 V
Hysteresis TA = 25°C 100 200 100 200 mV
Reset threshold voltage TA = 25°C 2.1 2.55 2.1 2.55 V
†All typical values are at TA = 25°C.
short-circuit protection
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
SCP threshold voltage TA = 25°C 0.95 1.00 1.05 0.97 1.00 1.03 V
SCP voltage, latched No pullup 140 185 230 140 185 230 mV
SCP voltage, UVLO standby No pullup 60 120 60 120 mV
Input source current TA = 25°C–10 –15 –20 –10 –15 –20 µA
SCP comparator 1 threshold voltage 1.5 1.5 V
†All typical values are at TA = 25°C.
oscillator
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Frequency Rt = 100 kΩ100 100 kHz
Standard deviation of frequency 15 15 kHz
Frequency change with voltage VCC = 3.6 V to 40 V 1 1 kHz
TA = –40°C to 25°C–4–0.4 4 –4–0.4 4 kHz
Frequency change with temperature TA = –20°C to 25°C–4–0.4 4 –4–0.4 4 kHz
TA = 25°C to 85°C–4–0.2 4 –4–0.2 4 kHz
Voltage at RT 1 1 V
†All typical values are at TA = 25°C.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 100 kHz (unless otherwise noted) (continued)
dead-time control
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Out
p
ut (source) current
TL5001C V(DT) = 1.5 V 0.9 × IRT‡1.1 × IRT 0.9 × IRT‡1.1 × IRT
µA
Output
(source)
current
TL5001I V(DT) = 1.5 V 0.9 × IRT‡1.2 × IRT 0.9 × IRT‡1.2 × IRT µ
A
In
p
ut threshold voltage
Duty cycle = 0% 0.5 0.7 0.5 0.7
V
Input
threshold
voltage
Duty cycle = 100% 1.3 1.5 1.3 1.5
V
†All typical values are at TA = 25°C.
‡Output source current at RT
error amplifier
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Input voltage VCC = 3.6 V to 40 V 0 1.5 0 1.5 V
Input bias current –160 –500 –160 –500 nA
Out
p
ut voltage swing
Positive 1.5 2.3 1.5 2.3 V
Output
voltage
swing
Negative 0.3 0.4 0.3 0.4 V
Open-loop voltage amplification 80 80 dB
Unity-gain bandwidth 1.5 1.5 MHz
Output (sink) current VI(FB) = 1.2 V, COMP = 1 V 100 600 100 600 µA
Output (source) current VI(FB) = 0.8 V, COMP = 1 V –45 –70 –45 –70 µA
†All typical values are at TA = 25°C.
output
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Output saturation voltage IO = 10 mA 1.5 2 1.5 2 V
Off state current
VO = 50 V, VCC = 0 10 10
µA
Off
-
state
current
VO = 50 V 10 10 µ
A
Short-circuit output current VO = 6 V 40 40 mA
†All typical values are at TA = 25°C.
total device
PARAMETER
TEST CONDITIONS
TL5001C, TL5001I TL5001AC, TL5001AI
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Standby supply current Off state 1 1.5 1 1.5 mA
Average supply current Rt = 100 kΩ1.4 2.1 1.4 2.1 mA
†All typical values are at TA = 25°C.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 100 kHz (unless otherwise noted)
reference
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
MIN TYP†MAX MIN TYP†MAX
Out
p
ut voltage
TA = 25°C
0.95 1.00 1.05 0.97 1.00 1.03
V
Output
voltage
TA = MIN to MAX
0.93 0.98 1.07 0.94 0.98 1.06
V
Input regulation TA = MIN to MAX VCC = 3.6 V to 40 V 2 12.5 2 12.5 mV
Output voltage change with temper-
ature TA = MIN to MAX *–6 2 *6 *–6 2 *6 %
†All typical values are at TA = 25°C.
*Not production tested.
undervoltage lockout
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
U
pp
er threshold voltage
TA = MIN, 25°C 3.00 3.00
V
Upper
threshold
voltage
TA = MAX 2.55 2.55
V
Lower threshold voltage
TA = MIN, 25°C 2.8 2.8
V
Lower
threshold
voltage
TA = MAX 2.0 2.0
V
Hysteresis TA = MIN to MAX 100 200 100 200 mV
Reset threshold voltage
TA = MIN, 25°C 2.10 2.55 2.10 2.55
V
Reset
threshold
voltage
TA = MAX 0.35 0.63 0.35 0.63
V
†All typical values are at TA = 25°C.
short-circuit protection
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
MIN TYP†MAX MIN TYP†MAX
SCP threshold voltage
TA = MIN, 25°C 0.95 1.00 1.05 0.97 1.00 1.03
V
SCP
threshold
voltage
TA = MAX 0.93 0.98 1.07 0.94 0.98 1.06
V
SCP voltage, latched TA = MIN to MAX No pullup 140 185 230 140 185 230 mV
SCP voltage, UVLO standby TA = MIN to MAX No pullup 60 120 60 120 mV
Equivalent timing resistance TA = MIN to MAX 185 185 kΩ
SCP comparator 1 threshold voltage TA = MIN to MAX 1.5 1.5 V
†All typical values are at TA = 25°C.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 100 kHz (unless otherwise noted) (continued)
oscillator
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
MIN TYP†MAX MIN TYP†MAX
Frequency TA = MIN to MAX Rt = 100 kΩ100 100 kHz
Standard deviation of frequency TA = MIN to MAX 2 2 kHz
Frequency change with voltage TA = MIN to MAX VCC = 3.6 V to 40 V 1 1 kHz
Fre
q
uenc
y
chan
g
e with
TA= MIN to MAX
Q suffix *–6 3 *6 *–6 3 *6
kHz
Frequency
change
with
temperature
T
A =
MIN
to
MAX
M suffix *–9 5 *9 *–9 5 *9
kHz
Voltage at RT TA = MIN to MAX 1 1 V
†All typical values are at TA = 25°C.
*Not production tested.
dead-time control
TEST CONDITIONS
TL5001Q, TL5001M TL5001AQ, TL5001AM
UNIT
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Output (source)
current TA = MIN to MAX V(DT) = 1.5 V 0.9 × IRT‡1.1 × IRT 0.9 × IRT‡1.1 × IRT µA
TA=25°C
Duty cycle = 0% 0.5 0.7 0.5 0.7
Input threshold
T
A =
25°C
Duty cycle = 100% 1.3 1.5 1.3 1.5
V
voltage
TA= MIN to MAX
Duty cycle = 0% 0.4 0.7 0.4 0.7
V
T
A =
MIN
to
MAX
Duty cycle = 100% 1.3 1.7 1.3 1.7
†All typical values are at TA = 25°C.
‡Output source current at RT
error amplifier
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Input bias current TA = MIN to MAX –160 –500 –160 –500 nA
Output volta
g
ePositive
TA= MIN to MAX
1.5 2.3 1.5 2.3 V
Out ut
voltage
swing Negative
T
A =
MIN
to
MAX
0.3 0.4 0.3 0.4 V
Open-loop voltage
amplification TA = MIN to MAX 80 80 dB
Unity-gain bandwidth TA = MIN to MAX 1.5 1.5 MHz
Output (sink) current TA = MIN to MAX VI(FB) = 1.2 V , COMP = 1 V 100 600 100 600 µA
Out
p
ut (source) current
TA = MIN, 25°C
VI(FB)=08V
COMP = 1 V
–45 –70 –45 –70
µA
Output
(source)
current
TA = MAX
V
I(FB) =
0
.
8
V
,
COMP
=
1
V
–30 –45 –30 –45 µ
A
†All typical values are at TA = 25°C.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 100 kHz (unless otherwise noted) (continued)
output
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
MIN TYP†MAX MIN TYP†MAX
Output saturation voltage TA = MIN to MAX IO = 10 mA 1.5 2 1.5 2 V
Off state current
TA= MIN to MAX
VO = 50 V, VCC = 0 10 10
µA
Off
-
state
current
T
A =
MIN
to
MAX
VO = 50 V 10 10 µ
A
Short-circuit output current TA = MIN to MAX VO = 6 V 40 40 mA
†All typical values are at TA = 25°C.
total device
PARAMETER TEST CONDITIONS TL5001Q,
TL5001M TL5001AQ,
TL5001AM UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
Standby supply current Off state TA = MIN to MAX 1 1.5 1 1.5 mA
Average supply current TA = MIN to MAX Rt = 100 kΩ1.4 2.1 1.4 2.1 mA
†All typical values are at TA = 25°C.
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
2.3 V
SCP Timing Period
3 V
DTC
OSC
COMP
1 V
0 V
PWM/DTC
Comparator
OUT
SCP
Comparator 1
SCP
SCP
Comparator 2
VCC
1.5 V
NOTE A: The waveforms show timing characteristics for an intermittent short circuit and a longer short circuit that is sufficient to activate SCP.
Figure 4. PWM Timing Diagram
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
100 k
10 k
1 M
10 k 100 k 1 M
f
VCC = 6 V
DT Resistance = Rt
TA = 25°C
Rt – Timing Resistance – Ω
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
– Oscillator Frequency – Hz
osc
Figure 6
94
92
90
88
– 50 – 25 0
96
98
100
25 50 75 100
TA – Ambient Temperature – °C
OSCILLATION FREQUENCY
vs
AMBIENT TEMPERATURE
f – Oscillation Frequency – kHz
osc
VCC = 6 V
Rt = 100 kΩ
DT Resistance = 100 kΩ
Figure 7
REFERENCE OUTPUT VOLTAGE
vs
POWER-SUPPLY VOLTAGE
– Reference Output Voltage – VVref
VCC – Power-Supply Voltage – V
1
0.8
0.4
0.2
0
1.8
0.6
0123456
1.4
1.2
1.6
2
78910
TA = 25°C
FB and COMP
Connected Together
Figure 8
– Reference Output Voltage Fluctuation – %
TA – Ambient Temperature – °C
∆Vref
REFERENCE OUTPUT VOLTAGE FLUCTUATION
vs
AMBIENT TEMPERATURE
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
– 0.2
– 0.4
– 0.8
– 50 – 25 0
0.2
0.4
0.6
25 50 75 100
0
VCC = 6 V
FB and COMP
Connected Together
– 0.6
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
1
0.5
0
2
1.5
010203040
– Average Supply Current – mA
VCC – Power-Supply Voltage – V
Rt = 100 kΩ
TA = 25 °C
AVERAGE SUPPLY CURRENT
vs
POWER-SUPPLY VOLTAGE
ICC
Figure 10
1
0.9
0.8
0
– 50 – 25 0
– Average Supply Current – mA
1.1
1.2
1.3
25 50 75 100
TA – Ambient Temperature – °C
VCC = 6 V
Rt = 100 kΩ
DT Resistance = 100 kΩ
ICC
AVERAGE SUPPLY CURRENT
vs
AMBIENT TEMPERATURE
Figure 11
1.5
1.2
0.6
0.3
0
1.8
0.9
10 k 100 k 1 M 10 M
PWM Triangle Wave Amplitude Voltage – V
fosc – Oscillator Frequency – Hz
Voscmin (zero duty cycle)
VCC = 6 V
TA = 25 °C
PWM TRIANGLE WAVE AMPLITUDE VOLTAGE
vs
OSCILLATOR FREQUENCY
Voscmax (100% duty cycle)
Figure 12
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
OUTPUT (SINK) CURRENT
– Error Amplifier Output Voltage – V
VO
IO – Output (Sink) Current – mA
1.5
1
0.5
00 0.2 0.4
2
2.5
3
0.6
VCC = 6 V
VI(FB) = 1.2 V
TA = 25 °C
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
1.5
1
0.5
002040
– Error Amplifier Output Voltage – V
2
2.5
3
60 80 100 120
VO
IO – Output (Source) Current – µA
VCC = 6 V
VI(FB) = 0.8 V
TA = 25 °C
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
OUTPUT (SOURCE) CURRENT
Figure 14
2.43
2.42
2.41
2.40
– 50 – 25 0
– Error Amplifier Output Voltage – V
2.44
2.45
2.46
25 50 75 100
VO
TA – Ambient Temperature – °C
VCC = 6 V
VI(FB) = 0.8 V
No Load
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
Figure 15
180
160
140
120
– 50 – 25 0
– Error Amplifier Output Voltage – mV
200
220
240
25 50 75 100
VO
TA – Ambient Temperature – °C
VCC = 6 V
VI(FB) = 1.2 V
No Load
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
Figure 16
30
20
0
– 10
– 20
40
10
10 k 100 k 1 M 10 M
– Error Amplifier Open-Loop Gain – dB
f – Frequency – Hz
VCC = 6 V
TA = 25 °C
AV
Error Amplifier Open-Loop Phase Shift
φ
AV
ERROR AMPLIFIER OPEN-LOOP GAIN AND
PHASE SHIFT
vs
FREQUENCY
–180°
–210°
–240°
–270°
–300°
–330°
–360°
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
60
40
20
00 0.5 1
80
100
120
1.5 2
DTC Voltage – V
OUTPUT DUTY CYCLE
vs
DTC VOLTAGE
Output Duty Cycle – %
VCC = 6 V
Rt = 100 kΩ
TA = 25 °C
Figure 18
6
4
2
002040
– SCP Time-Out Period – ms
8
10
12
60 80 100 120
VCC = 6 V
Rt = 100 kΩ
DT Resistance = 200 kΩ
TA = 25 °C
CSCP – SCP Capacitance – nF
tSCP
SCP TIME-OUT PERIOD
vs
SCP CAPACITANCE
Figure 19
– 30
– 20
– 10
00– 10 – 20
– DTC Output Current –
– 40
– 50
– 60
– 30 – 40 – 50 – 60
DT Voltage = 1.3 V
TA = 25 °C
IO – RT Output Current – µA
AµIO(DT)
DTC OUTPUT CURRENT
vs
RT OUTPUT CURRENT
Figure 20
1
0.5
0
2
1.5
0 5 10 15 20
– Output Saturation Voltage – V
IO – Output (Sink) Current – mA
VCE
VCC = 6 V
TA = 25 °C
OUTPUT SATURATION VOLTAGE
vs
OUTPUT (SINK) CURRENT
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
U1
TL5001/A
FB
COMP
VO
DTC
RT
GND
C1
100 µF
10 V
VI
5 V +R1
470 Ω
SCP
VCC
L1
20 µH
C2
100 µF
10 V
3.3 V
GND
+
CR1
MBRS140T3
Q1
TPS1101
C6
0.012 µF
R4
5.1 kΩ
R5
7.50 kΩ
1%
R2
56 kΩ
R3
43 kΩ
R6
3.24 kΩ
1%
C5
0.1 µF
C4
1 µF
C3
0.1 µF
GND
8
7
6
5
2
1
3
4
Partial Bill of Materials:
U1 TL5001/A Texas Instruments
Q1 TPS1 101 T exas Instruments
LI CTX20-1 or Coiltronics
23 turns of #28 wire on
Micrometals No. T50-26B core
C1 TPSD107M010R0100 AVX
C2 TPSD107M010R0100 AVX
CR1 MBRS140T3 Motorola
R7
2.0 kΩ
C7
0.0047 µF
+
NOTES: A. Frequency = 200 kHz
B. Duty cycle = 90% max
C. Soft-start time constant (TC) = 5.6 ms
D. SCP TC = 70 msA
Figure 21. Step-Down Converter
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
E. Falls within JEDEC MS-012
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/C 11/95
28 TERMINALS SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.740
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
121314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Falls within JEDEC MS-004
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9958301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9958301Q2A
TL5001
MFKB
5962-9958301QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958301QPA
TL5001M
5962-9958302Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9958302Q2A
TL5001
AMFKB
5962-9958302QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958302QPA
TL5001AM
TL5001ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001ACDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL5001AIP
TL5001AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL5001AIP
TL5001AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9958302Q2A
TL5001
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
AMFKB
TL5001AMJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL5001AMJG
TL5001AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958302QPA
TL5001AM
TL5001AQD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ
TL5001AQDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5001AQ
TL5001AQDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ
TL5001AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5001AQ
TL5001CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 TL5001CP
TL5001CP-P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type TL5001CP
TL5001CP-PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type TL5001CP
TL5001CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 TL5001CP
TL5001CPS ACTIVE SO PS 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM T5001
TL5001CPSG4 ACTIVE SO PS 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM T5001
TL5001CPSLE OBSOLETE SO PS 8 TBD Call TI Call TI
TL5001CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 T5001
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TL5001CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 T5001
TL5001ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL5001IP
TL5001IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL5001IP
TL5001IPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Z5001
TL5001IPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Z5001
TL5001MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9958301Q2A
TL5001
MFKB
TL5001MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL5001MJG
TL5001MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9958301QPA
TL5001M
TL5001QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q
TL5001QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5001Q
TL5001QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q
TL5001QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5001Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL5001, TL5001A, TL5001AM, TL5001M :
•Catalog: TL5001A, TL5001
•Automotive: TL5001A-Q1, TL5001A-Q1
•Military: TL5001M, TL5001AM
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 5
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL5001ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AQDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL5001IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001IPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TL5001QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL5001ACDR SOIC D 8 2500 340.5 338.1 20.6
TL5001AIDR SOIC D 8 2500 340.5 338.1 20.6
TL5001AQDR SOIC D 8 2500 367.0 367.0 35.0
TL5001AQDRG4 SOIC D 8 2500 367.0 367.0 35.0
TL5001CDR SOIC D 8 2500 340.5 338.1 20.6
TL5001CPSR SO PS 8 2000 367.0 367.0 38.0
TL5001IDR SOIC D 8 2500 340.5 338.1 20.6
TL5001IPSR SO PS 8 2000 367.0 367.0 38.0
TL5001QDR SOIC D 8 2500 367.0 367.0 35.0
TL5001QDRG4 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2013
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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